CN112256499A

CN112256499A - Power failure monitoring method and device, electronic equipment and computer readable storage medium

Info

Publication number: CN112256499A
Application number: CN202010889025.7A
Authority: CN
Inventors: 季冬冬; 张广乐; 刘畅
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2020-08-28
Filing date: 2020-08-28
Publication date: 2021-01-22

Abstract

The invention provides a power failure monitoring method, a power failure monitoring device, electronic equipment and a computer readable storage medium, belongs to the technical field of power failure monitoring, and solves the problem that logs are not recorded even if a serious failure of power loss occurs in the existing control strategy. When the power supply unit is powered down, storing power down information into a flash memory; after the power supply unit is powered up again, reading power failure information in the flash memory; synchronizing the power failure information to the RAM, so that the BMC can read the power failure information in the RAM; and clearing the power failure information in the flash memory. The invention is used for adding the switch PSU power-down information recording and displaying function in the existing CPLD/FPGA and BMC design, optimizes the switch fault recording and displaying system design, is convenient for problem location when a fault occurs in the PSU power-down information recording and displaying system, and needs to record the power-down log besides clearing action after the BMC acquires the power-down information, thereby prompting a user and bringing more humanized interactive design to the user.

Description

Power failure monitoring method and device, electronic equipment and computer readable storage medium

Technical Field

The present invention relates to the field of power failure monitoring technologies, and in particular, to a power failure monitoring method and apparatus, an electronic device, and a computer-readable storage medium.

Background

The CPLD/FPGA is a semi-customized special integrated circuit, has the series advantages of flexible programming, quick response, high integration level and the like, and is more and more widely applied to the field of development, verification and control application in the prior period. In the switch system, the CPLD/FPGA chip is used for controlling the power-on and power-off sequence control, communication control, key detection, fan rotating speed control, SFP lighting control, serial port switching and the like of the whole switch, and the BMC is used for indicating the state, state detection, firmware upgrading, remote control, log collection and the like of the switch.

When the AC power line is lost to cause the power loss of the switch system, at the moment, the whole switch system loses power supply within millisecond time, the system needs to quickly acquire the power loss of the system and quickly store the information into the nonvolatile memory, so that the power failure information is ensured not to be lost, and when the switch system recovers the power supply, the power failure information needs to be recovered.

In existing control strategies, logs are not recorded even when a power loss catastrophic failure occurs.

Disclosure of Invention

The invention aims to provide a power failure monitoring method, a power failure monitoring device, electronic equipment and a computer readable storage medium, and aims to solve the technical problem that logs cannot be recorded when a power source is lost or a serious fault occurs in the prior art.

In a first aspect, the present invention provides a power failure monitoring method applied to a programmable device, where the method includes:

when the power supply unit is powered down, storing the power down information into the flash memory;

after the power supply unit is powered up again, reading power failure information in the flash memory;

synchronizing the power failure information to the RAM, so that the BMC can read the power failure information in the RAM;

and clearing the power failure information in the flash memory.

Further, the programmable device is a CPLD, and the flash memory is an internal flash memory of the CPLD.

Furthermore, the programmable device is an FPGA, and the flash memory is an FPGA plug-in flash memory.

Further, the step of clearing the power failure information in the flash memory includes:

receiving a command for clearing power failure information in the RAM from the BMC;

and clearing the power failure information in the flash memory according to the instruction.

In a second aspect, the present invention further provides a power failure monitoring apparatus, which is applied to a programmable device, and the apparatus includes:

the write-in module is used for storing the power failure information to the flash memory when the power supply unit is powered down;

the reading module is used for reading the power failure information in the flash memory after the power supply unit is powered up;

the synchronization module is used for synchronizing the power failure information to the RAM so that the BMC can read the power failure information in the RAM;

and the clearing module is used for clearing the power failure information in the flash memory.

Further, the clearing module is specifically configured to receive an instruction from the BMC to clear the power failure information in the RAM; and clearing the power failure information in the flash memory according to the instruction.

In a third aspect, the present invention further provides an electronic device comprising a BMC, a power supply unit and the power down monitoring apparatus of claim 5 or 6.

Further, the electronic device is a switch or a server.

In a fourth aspect the present invention also provides a computer readable storage medium having stored thereon machine executable instructions which, when invoked and executed by a processor, cause the processor to carry out the method of any of claims 1 to 4

The invention provides a switch system PSU power failure monitoring method and a detection device, which add a switch PSU power failure information recording and displaying function in the existing CPLD/FPGA and BMC design, thereby optimizing the switch fault recording and displaying system design. The PSU power failure information recording and displaying method comprises the following steps: when the CPLD/FPGA detects that the PSU PWROK information of the switch system fails, the FLASH read-write logic is triggered, the PSU power-down information is recorded into a FLASH which is not lost when power is down, when the switch system is powered on, the FLASH read-write logic is triggered again, the PSU power-down information is synchronized into the RAM, when the BMC acquires the PSU power-down information, the recording and displaying can be carried out, the BMC simultaneously carries out clearing operation on the PSU power-down information in the RAM, when the CPLD/FPGA acquires the instruction, the PSU power-down information in the FLASH can be erased, the PSU power-down information recording and displaying system is convenient for problem location when a failure occurs, and meanwhile, more humanized interactive design is brought to a user.

Accordingly, the electronic device and the computer-readable storage medium provided by the embodiments of the present invention also have the above technical effects.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a functional schematic diagram of a method for implementing a PSU power failure monitoring recording system of a switch system according to an embodiment of the present invention;

FIG. 2 is a functional schematic diagram of a PSU PWROK power indication detection module provided by an embodiment of the invention;

fig. 3 is a schematic diagram of the operation of the CPLD/FPGA on the FLASH and RAM and the BMC read-write display logic function according to the embodiment of the present invention;

fig. 4 is a schematic block diagram of an electronic device system according to an embodiment of the present invention.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without any creative effort, shall fall within the protection scope of the present invention.

The terms "comprising" and "having" and any variations thereof as referred to in embodiments of the invention are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The embodiment of the invention provides a power failure monitoring method, which is applied to a programmable device and comprises the following steps:

and clearing the power failure information in the flash memory.

The embodiment of the invention also provides a power failure monitoring device, which is applied to a programmable device, and comprises:

The PSU state of the switch system is detected in the whole switch operation life, and when the PSU loses power and the whole switch system loses power supply, the CPLD/FPGA stores PSU power failure information into a FLASH which does not lose power failure; when the switch system recovers the power supply, the CPLD/FPGA reads FLASH information and synchronizes the information to the RAM, and the BMC directly reads PSU information in the RAM and displays records; after reading the PSU information, the BMC can clear the PSU power-down information in the RAM, and after receiving the PSU power-down information, the CPLD/FPGA can synchronously clear the PSU power-down information in the FLASH. The PSU is monitored by combining the CPLD/FPGA and the BMC, and PSU information recording is increased; on the other hand, the scheme does not increase BMC logic and does not bring CPLD/FPGA IO change, and CPLD/FPGA logic resources are increased because FLASH and synchronous RAM and FLASH information are read. The scheme that this patent is related to can show to improve switch system fault location foundation and data display hommization, simultaneously based on CPLD/FPGA's programmable property, can fully verify before the volume production, make control more nimble. The patent is characterized mainly in the following aspects:

1. the PSU information is detected in the running process of the switch, and when the PSU is powered off, the PSU power-off information is recorded into a non-volatile memory FLASH, so that the PSU power-off information loss caused by the fact that a PSU power-off switch system loses power supply is prevented.

2. When the system is powered on and power supply is recovered, FLASH information is synchronized to the RAM, and the upper-layer controller can conveniently acquire power failure information. The upper controller is prevented from directly accessing the FLASH memory.

3. The upper layer controller such as BMC will display when obtaining PSU power down information, which is beneficial to providing visual interface.

4. When the upper layer controller acquires the PSU power failure information, a PSU power failure clearing instruction is written into the RAM, and when the CPLD/FPGA receives the information, the PSU power failure information in the FLASH is controlled to be cleared, so that the next recording is facilitated.

5. The switch system does not increase logic or IO of an upper controller or increase CPLD/FPGA IO through the PSU power failure monitoring record display system realization method of the CPLD/FPGA and the BMC, but increases CPLD/FPGA logic resources, thereby bringing about the change of CPLD/FPGA model selection.

The CPLD/FPGA has the advantage of high system clock frequency, can quickly acquire the information of power loss, and can complete information storage before the whole switch system loses the information. The BMC or the CPU can be used as an upper layer controller to display information.

The invention realizes PSU power failure information recording and displaying function in the existing CPLD/FPGA and BMC design, the key points are PSU PWROK detection, FLASH read-write logic and drive design and RAM and FLASH information synchronous design, the specific embodiment of the invention includes the following two kinds:

example one

1) PSU information detection design

And (3) monitoring the descending edge of the PWROK signal indicating normal working state information of each PSU in real time through a CPLD/FPGA high-speed system clock, and obtaining a PSU power-down indicating signal when detecting that all the PWROK signals of the PSU are abnormal. The functional schematic diagram of the PSU PWROK power indication detection module is shown in fig. 2.

2) FLASH read design

When the PSU PWROK signal is abnormal, the FLASH is written, and specially, the FLASH is written by a state machine according to the FLASH time sequence. And when the PSU PWROK signal is recovered to be normal, executing read operation on the FLASH. And when the upper-layer controller carries out clearing operation on the FLASH PSU indicating bit, writing operation is carried out on the FLASH PSU indicating bit, and the current PSU PWROK normal information is written. Particularly, for the CPLD, the PSU information can be stored in the own user FLASH, and for the FPGA, the PSU information can be stored in the external FLASH. The schematic diagram of the logic function of the operation of the CPLD/FPGA on the FLASH and RAM and the reading and writing display of the BMC is shown in FIG. 3.

3) Synchronous design of FLASH and RAM information

In order to facilitate the upper controller to obtain PSU information and read and write FLASH, and synchronize FLASH and RAM information, the upper controller directly performs read and write operations on the CPLD/FPGA, and the CPLD/FPGA performs read and write operations on the FLASH. Specifically, the CPLD/FPGA RAM communicates with the upper controller through I2C. The schematic diagram of the logic function of the operation of the CPLD/FPGA on the FLASH and RAM and the reading and writing display of the BMC is shown in FIG. 3.

4) BMC to RAM read-write and display design

The BMC reads and writes the CPLD/FPGA register according to a general I2C protocol, and when reading that the specific PSU power failure register information is effective, the BMC records the information into a log and prompts a user; in order to record PSU power failure information next time, the BMC can write the RAM, and the CPLD/FPGA can synchronize the information into the FLASH. The schematic diagram of the logic function of the operation of the CPLD/FPGA on the FLASH and RAM and the reading and writing display of the BMC is shown in FIG. 3.

Example two

1) Designing a switch PSU power failure fault information recording and displaying system based on a CPLD/FPGA and a BMC on the basis of the first principle of the embodiment;

2) compiling a CPLD/FPGA and BMC program, and updating a CPLD/FPGA and BMC burning mirror image;

3) and plugging and unplugging the PSU, verifying the effectiveness of the strategy and optimizing the power failure information recording and protecting system of the switch PSU.

The PSU power failure information recording and displaying system provided by the invention can be applied to a switch system and a server system, and simultaneously, FLASH can record PSU power failure information and record any information lost or expected to be stored when power failure occurs

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention usually place when in use, and are only used for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have specific orientations, be constructed in specific orientations, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

An electronic device according to an embodiment of the present invention includes a BMC, a power supply unit, and a power failure monitoring apparatus according to the foregoing embodiments, where the electronic device is a switch or a server, as shown in fig. 4, an electronic device 800 includes a memory 801 and a processor 802, where the memory stores a computer program that can be executed on the processor, and the processor implements the steps of the method according to the foregoing embodiments when executing the computer program.

As shown in fig. 4, the electronic device further includes: a bus 803 and a communication interface 804, the processor 802, the communication interface 804, and the memory 801 being connected by the bus 803; the processor 802 is used to execute executable modules, such as computer programs, stored in the memory 801.

The Memory 801 may include a high-speed Random Access Memory (RAM), and may also include a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. The communication connection between the network element of the system and at least one other network element is implemented through at least one communication interface 804 (which may be wired or wireless), and an internet, a wide area network, a local network, a metropolitan area network, and the like may be used.

The bus 803 may be an ISA bus, PCI bus, EISA bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one double-headed arrow is shown in FIG. 4, but that does not indicate only one bus or one type of bus.

The memory 801 is used for storing a program, the processor 802 executes the program after receiving an execution instruction, and the method performed by the apparatus defined by the process disclosed in any of the foregoing embodiments of the present invention may be applied to the processor 802, or implemented by the processor 802.

The processor 802 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 802. The Processor 802 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the device can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in ram, flash memory, rom, prom, or eprom, registers, among other storage media as is well known in the art. The storage medium is located in the memory 801, and the processor 802 reads the information in the memory 801 and completes the steps of the method in combination with the hardware thereof.

In accordance with the above method, embodiments of the present invention also provide a computer readable storage medium storing machine executable instructions, which when invoked and executed by a processor, cause the processor to perform the steps of the above method.

The apparatus provided by the embodiment of the present invention may be specific hardware on the device, or software or firmware installed on the device, etc. The device provided by the embodiment of the present invention has the same implementation principle and technical effect as the method embodiments, and for the sake of brief description, no mention is made in the device embodiments, and reference may be made to the corresponding contents in the method embodiments. It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the foregoing systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

As another example, the division of the elements into only one logical division may be implemented in a different manner, as multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may also be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in the embodiments provided by the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in a figure, it need not be further defined or explained in subsequent figures, and moreover, the terms "first," "second," "third," etc. are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.

Finally, it should be noted that: the above-mentioned embodiments are merely specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: those skilled in the art can still make modifications or changes to the technical solutions described in the foregoing embodiments or make equivalent substitutions for some technical features within the technical scope of the present disclosure; and the modifications, changes or substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention. Are intended to be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A power failure monitoring method is applied to a programmable device, and comprises the following steps:

and clearing the power failure information in the flash memory.

2. The power failure monitoring method according to claim 1, wherein the programmable device is a CPLD, and the flash memory is a CPLD internal flash memory.

3. The power failure monitoring method according to claim 1, wherein the programmable device is an FPGA, and the flash memory is an FPGA plug-in flash memory.

4. The power failure monitoring method according to claim 3, wherein the step of clearing the power failure information in the flash memory comprises:

5. A power failure monitoring device is applied to a programmable device, and comprises:

6. The power-down monitoring device according to claim 5, wherein the purge module is specifically configured to receive an instruction from the BMC to purge the RAM of power-down information; and clearing the power failure information in the flash memory according to the instruction.

7. An electronic device comprising a BMC, a power supply unit and a power down monitoring apparatus as claimed in claim 5 or 6.

8. The electronic device of claim 7, wherein the electronic device is a switch or a server.

9. A computer readable storage medium having stored thereon machine executable instructions which, when invoked and executed by a processor, cause the processor to execute the method of any of claims 1 to 4.