CN103631739A - Positioning analysis method for embedded system and embedded system - Google Patents
Positioning analysis method for embedded system and embedded system Download PDFInfo
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Abstract
The embodiment of the invention relates to a positioning analysis method for an embedded system and the embedded system. The embedded system comprises a processor, a processor ETM, a bus and a bus ETM, wherein the bus is electrically connected with the bus ETM, and the processor ETM is electrically connected with the bus ETM. The method includes the steps that a processor trigger condition is configured for the processor ETM; the processor ETM is triggered to complete processor collection operation when the processor ETM detects an event meeting the corresponding processor trigger condition, and the triggered processor ETM sends a message to the bus ETM which is not triggered, and the message is used for triggering the bus ETM to complete bus collection operation; the collected processor operation and the collected bus operation are stored so as to carry out system positioning analysis. Through combined tracking on the processor and the bus, the positioning analysis method for the embedded system and the embedded system can increase the information amount capable of being used for analyzing abnormity reasons and improve fault analyzing and solving efficiency beneficially aiming at abnormities in the system.
Description
Technical field
The embodiment of the present invention relates to embedded system, particularly the method for positioning analyzing of embedded system and embedded system.
Background technology
In order to guarantee the normal operation of programs in embedded system and other technical purpose, conventionally need to position analysis to embedded system, specifically, conventionally need to follow the tracks of processor of embedded system etc.Embedded system comprises flush bonding processor, ARM(Advanced RISC(Reduced Instruction Set Computing for example) Machines, advanced RISC(Reduced Instruction Set Computer) CPU(Central Processing Unit machines corporation), central processing unit).In flush bonding processor, generally comprise ETM(Embedded Trace Macrocell, Embedded Trace unit), be used for monitoring the kernel of flush bonding processor, and by the information after compression real-time be delivered to ETB(Embedded Trace Buffer, Embedded Trace buffer memory).User can be by JTAG(Joint Test Action Group for example, combined testing action group) data in interface accessing ETB, to the fault in embedded system, extremely carry out analyzing and positioning.
In complicated embedded system, can by bus, connect the equipment such as processor, storer, particularly, in the embedded system of multiprocessor, the structure of bus is very complicated.Adopt the similar method that processor is followed the tracks of, also can position analysis to the operation in bus.In this case, in bus, also comprise ETM and corresponding ETB with it.
When embedded system being positioned to analysis, corresponding trigger condition can be set for the ETM of flush bonding processor and bus.In program operation process in embedded system, the Acquisition Processor that ETM is real-time and the instruction in bus, and be written in corresponding ETB.When meeting trigger condition, for example occur when abnormal, trigger ETM, for example by interruptions, trigger ETM, make ETM stop collection.Before triggering ETM by analysis, the information recording in ETB, can analyze and cause meeting trigger condition, for example abnormal, reason and position.
The operation (instruction) that ETM can carry out in each cycle of recording processor, also can selectively only record redirect or abnormal behavior (instruction).By instruction is compressed, for example, to recording redirect, exceptional instructions, or the mode such as the type of recording instruction and jump address only, can save the record space in ETB.
Summary of the invention
The embodiment of the present invention has proposed a kind of method for positioning analyzing of embedded system, by the tracking of combining to processor and bus, abnormal for what occur in embedded system, increase the quantity of information that can be used for analyzing abnormal generation reason, be conducive to improve the efficiency of fault analysis and solution.
First aspect, the embodiment of the present invention has proposed a kind of method for positioning analyzing of embedded system, the processor Embedded Trace Module ETM that described embedded system comprises processor and is electrically connected to described processor, and bus and the bus ETM that is electrically connected to described bus, described processor ETM is electrically connected to described bus ETM, and described method comprises: be described processor ETM configuration processor trigger condition;
When described processor ETM detects the event that meets its corresponding processor trigger condition, described processor ETM has been triggered Acquisition Processor operation, the described processor ETM being triggered sends message to the described bus ETM not being triggered, and described message is used for triggering described bus ETM and completes data acquisition bus operation;
Storage of collected to described processor operations and the described bus operation that collects, for system positioning analysis.
In conjunction with first aspect, in the possible implementation of the first, be described bus ETM configuration bus trigger condition; When described bus ETM detects the event that meets its corresponding bus trigger condition, described bus ETM has been triggered data acquisition bus operation, the described bus ETM being triggered sends message to the described processor ETM not being triggered, and described message is used for triggering described processor ETM and completes Acquisition Processor operation.
In conjunction with the possible implementation of the first of first aspect or first aspect, in the possible implementation of the second, described processor operations and described bus operation comprise respectively timestamp, described timestamp is used for making described processor operations and described bus according to time unifying, for co-located analysis.
In conjunction with first, second kind of first aspect or first aspect possible implementation, in the third possible implementation, described processor ETM and described bus ETM comprise respectively timer, and described method comprises:
The timer of the timer of described processor ETM and described bus ETM is synchronous;
Described processor ETM reads the timing value of the timer of described processor ETM while gathering described processor operations, timestamp as described processor operations, while gathering described bus operation with described bus ETM, read the timing value of the timer of described bus ETM, as the timestamp of described bus operation.
In conjunction with first aspect or first aspect first to the third possible implementation, in the 4th kind of possible implementation, described storage of collected to described processor operations and the described bus operation collecting, specifically comprise:
According to described timestamp by described processor operations and described bus operation time unifying, and be joint operation record by described processor operations and described bus operation unloading, wherein each joint operation record comprises timestamp, the processor operations corresponding with this timestamp and the bus operation corresponding with this timestamp.
In conjunction with first to fourth kind of first aspect or first aspect possible implementation, in the 5th kind of possible implementation, described embedded system comprises a plurality of processors and a plurality of described processor ETM corresponding with described a plurality of processors, wherein described in each processor ETM respectively with being electrically connected to processor ETM described in other of described bus ETM, so that when a described processor ETM is triggered therein, the described processor ETM being triggered sends described message to the described bus ETM not being triggered and other processors ETM, be used for triggering described bus ETM and other processors ETM and complete separately data acquisition bus operation and processor operations.
First to the 5th kind of possible implementation in conjunction with first aspect or first aspect, in the 6th kind of possible implementation, described embedded system comprises a plurality of buses and a plurality of described bus ETM corresponding with described a plurality of buses, wherein described in each, bus ETM is electrically connected to described processor ETM and bus ETM described in other respectively, so that when a described bus ETM is triggered therein, the described bus ETM being triggered sends described message to described processor ETM and bus ETM described in other, be used for triggering described processor ETM and other buses ETM and complete separately Acquisition Processor operation and bus operation.
First to the 6th kind of possible implementation in conjunction with first aspect or first aspect, in the 7th kind of possible implementation, described embedded system comprises a plurality of processors and a plurality of described processor ETM corresponding with described a plurality of processors, wherein described in each, processor ETM is electrically connected to bus ETM described in each and processor ETM described in other respectively, so that when a described processor ETM is triggered therein, the described processor ETM being triggered sends described message to described a plurality of bus ETM and other processors ETM, be used for triggering described a plurality of bus ETM and complete separately data acquisition bus operation and processor operations with processor ETM described in other.
In conjunction with first to the 7th kind of possible implementation of first aspect or first aspect, in the 8th kind of possible implementation, described method also comprises: show the described joint operation record of storing.
First to the 8th kind of possible implementation in conjunction with first aspect or first aspect, in the 9th kind of possible implementation, the described message that described described bus ETM to not being triggered or described processor ETM send, the described bus ETM not being triggered described in arrival or the relative delay of described processor ETM remain unchanged.
Second aspect, has proposed a kind of method for positioning analyzing of embedded system, and described embedded system comprises processor and bus, and the system ETM being electrically connected to described processor and bus, and described method comprises:
For described system ETM configuration processor trigger condition and bus trigger condition;
In described system ETM detects processor, meet while meeting the event of described bus trigger condition in described processor trigger condition or described bus, described system ETM is triggered and completes and gathers described processor operations and described bus operation;
Store described processor operations and described bus operation that described system ETM gathers, for system positioning analysis.
In conjunction with second aspect, in the possible implementation of the first, described processor operations and described bus operation comprise timestamp, and described timestamp is used for making described processor operations and described bus according to time unifying, for co-located analysis.
In conjunction with the possible implementation of the first of second aspect or second aspect, in the possible implementation of the second, described system ETM comprises timer, and described method comprises:
Start the described timer of described system ETM,
Described system ETM gathers described processor operations and described bus operation and reads the timing value of described timer, as the described timestamp of described processor operations and described bus operation.
The third aspect, has proposed a kind of embedded system, and described embedded system comprises:
Processor, for executable operations instruction;
The processor Embedded Trace Module ETM being electrically connected to described processor, for gathering the operation of described processor, described processor ETM comprises processor Embedded Trace buffer ETB;
Bus, for being electrically connected to described processor and storer;
The bus ETM being electrically connected to described bus, for gathering the operation of described bus, described bus ETM comprises bus ETB;
Wherein said processor ETM is electrically connected to described bus ETM, and described embedded system also comprises:
Controller, described controller is used to described processor ETM configuration processor trigger condition;
When described processor ETM detects the event that meets its corresponding processor trigger condition, described processor ETM has been triggered Acquisition Processor operation, the described processor ETM being triggered sends message to the described bus ETM not being triggered, and described message is used for triggering described bus ETM and completes data acquisition bus operation;
Described processor ETB is for storing gathered described processor operations and described bus ETB for storing gathered described bus operation, for system positioning analysis.
In conjunction with the third aspect, in the possible implementation of the first, described controller is used to described bus ETM configuration bus trigger condition, when described bus ETM detects the event that meets its corresponding trigger condition, described bus ETM has been triggered data acquisition bus operation, the described bus ETM being triggered sends message to the described processor ETM not being triggered, and described message is used for triggering described processor ETM and completes Acquisition Processor operation.
In conjunction with the possible implementation of the first of the third aspect or the third aspect, in the possible implementation of the second, described processor ETM and described bus ETM comprise respectively timer,
Described controller is used for the timer of the timer of described processor ETM and described bus ETM is synchronous,
When described processor ETM Acquisition Processor operation, described processor ETM is also for reading the timing value of the timer of described processor ETM, as the timestamp of described processor operations;
When described bus ETM data acquisition bus operation, described bus ETM is also for reading the timing value of the timer of described bus ETM, as the timestamp of described bus operation.
In conjunction with first and second kinds of the third aspect or the third aspect possible implementations, in the third possible implementation, described controller is used for according to described timestamp described processor operations and described bus operation time unifying, and described processor operations and described bus operation are saved as to joint operation record in described storer transfer, wherein each joint operation record comprises timestamp, the processor operations corresponding with this timestamp and the bus operation corresponding with this timestamp.
In conjunction with the third aspect or the third aspect first to the third possible implementation, in the 4th kind of possible implementation, described embedded system also comprises:
Display, for showing the described joint operation record of described memory stores.
In conjunction with first to fourth kind of the third aspect or the third aspect possible implementation, in the 5th kind of possible implementation, the described message that described described bus ETM to not being triggered or described processor ETM send, the described bus ETM not being triggered described in arrival or the relative delay of described processor ETM remain unchanged.
Fourth aspect, has proposed a kind of embedded system, and described embedded system comprises:
Processor, for executable operations instruction;
Bus, for being electrically connected to described processor and storer;
The system ETM being electrically connected to described processor and described bus, for gathering the operation of described processor and the operation of described bus, described system ETM comprises system ETB;
Controller, described controller is used to described system ETM configuration processor trigger condition and bus trigger condition;
In described system ETM detects processor, meet while meeting the event of described bus trigger condition in described processor trigger condition or described bus, described system ETM is triggered and completes and gathers described processor operations and described bus operation;
Described processor operations and described bus operation that described system ETB gathers for storing described system ETM, for system positioning analysis.
In conjunction with fourth aspect, in the possible implementation of the first, described system ETM comprises timer,
Described controller is used for starting described timer,
When described system ETM Acquisition Processor operation and bus operation, described system ETM reads the timing value of described timer, as the described timestamp of described processor operations and described bus operation.
According to the embodiment of the present invention, by the processor in embedded system and bus, combine tracking, abnormal for what occur in embedded system, increase the quantity of information that can be used for analyzing abnormal generation reason, be conducive to improve the efficiency of fault analysis and solution.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural drawing of embedded system of the technical scheme of the application embodiment of the present invention;
Fig. 2 is according to the schematic flow diagram of the method for positioning analyzing of the embedded system of the embodiment of the present invention;
Fig. 3 is the structural drawing of another kind of embedded system of the technical scheme of the application embodiment of the present invention;
Fig. 4 is according to the schematic flow diagram of the embedded system method for positioning analyzing of the embodiment of the present invention;
Fig. 5 is according to the schematic configuration diagram of the embedded system of the embodiment of the present invention;
Fig. 6 is according to the schematic configuration diagram of the embedded system of the embodiment of the present invention;
Fig. 7 is according to the schematic configuration diagram of the another kind of embedded system of the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Fig. 1 is the structural drawing of embedded system of the technical scheme of the application embodiment of the present invention.As shown in Figure 1, comprise that the embedded system 100 of positioning analysis module comprises: processor 110, for executable operations instruction; Processor ETM 120, described processor ETM is electrically connected to processor, for the instruction operation situation of monitoring processor 110 operation in Acquisition Processor 110; Processor ETB 122, described processor ETB is electrically connected to processor ETM, the processor operations gathering for cache processor ETM120; Bus 130, described bus is electrically connected to processor 110 with storer 140, for transfer instruction and data between processor 110 and storer 140; Bus ETM 150, and described bus ETM150 is electrically connected to bus 130, for monitor and data acquisition bus 150 on read-write operation; Bus ETB152, described bus ETB is electrically connected to bus ETM 150, the bus operation gathering for buffer memory bus ETM150.According to the embodiment of the present invention, processor ETM 120 is electrically connected to bus ETM 150, for mutual pass-along message.For example, the triggering port of processor ETM 120 and the triggering port of bus ETM 150 are all electrically connected on common controller, realized the co-located of processor ETM 120 and bus ETM 150 analyze by controller.
It will be understood by those skilled in the art that when embedded system 100 being positioned to analysis, can also comprise the main frame of debugging use, for example personal computer; Trace debug software; With trace debug emulator, JTAG emulator for example.The main frame of debugging use is electrically connected to processor ETM and bus ETM by trace debug emulator, and by debugging interface for example jtag interface ETM is configured, read the data in ETB, coordinate trace debug software to carry out the operations such as the fault analysis of embedded system, abnormal location.
It will be understood by those skilled in the art that in embedded system shown in Fig. 1, storer 140 is only the example of the equipment that loads in bus.The equipment loading in bus can comprise main equipment (Master) and additionally arrange standby (Slave), wherein processor 110 can be used as main equipment also can be standby as additionally arranging, and storer 140 can only be standby as additionally arranging.Additionally arranging for comprising the equipment except storer 140, Peripheral Interface, input-output device etc. in embedded system.
It should be appreciated by those skilled in the art that the scale difference according to embedded system, wherein can comprise a plurality of processors, a plurality of processor ETM, a plurality of bus, a plurality of bus ETM.They can interconnect according to the annexation shown in Fig. 1, and all ETM wherein, comprise processor ETM and bus ETM, are electrically connected to each other, and the mutual pass-along message of user, to realize the co-located analysis to embedded system.
Fig. 2 is according to the schematic flow diagram of the method for positioning analyzing 200 of the embedded system of the embodiment of the present invention.As shown in Figure 2, method 200 comprises:
210: be processor ETM configuration processor trigger condition;
Method for positioning analyzing also comprises startup processor ETM Acquisition Processor operation and starts the operation of bus ETM data acquisition bus.
220: when described processor ETM detects the event that meets its corresponding processor trigger condition, described processor ETM has been triggered Acquisition Processor operation, the described processor ETM being triggered sends message to the described bus ETM not being triggered, and described message is used for triggering described bus ETM and completes data acquisition bus operation;
230: storage of collected to processor operations and the bus operation that collects, for system positioning analysis.
In embodiments of the present invention, step 210 can also be included as bus ETM configuration bus trigger condition.In this case, step 220 may further include or when described bus ETM detects the event that meets its corresponding bus trigger condition, described bus ETM has been triggered data acquisition bus operation, the described bus ETM being triggered sends message to the described processor ETM not being triggered, and described message is used for triggering described processor ETM and completes Acquisition Processor operation;
In embedded system malfunction analysis procedure, the instruction of carrying out in processor ETM continuous acquisition processor, and instruction and data in bus ETM continuous acquisition bus, when processor ETM is triggered, processor ETM is by the instruction that stops carrying out in Acquisition Processor, and by the instruction buffer collecting in bus ETB, be provided with post analysis, the mode of operation of bus ETM is similar to processor ETM.For the processor trigger condition of processor ETM be the bus trigger condition of bus ETM configuration, can be the anomalous event of the appearance in processor, the abnormal read-write operation in bus etc.Or for other actual needs, the processor trigger condition configuring for processor ETM can be jump instruction, branch instruction etc.For example, the processor trigger condition configuring for processor ETM can be while processor execution " goto Address**** " instruction being detected, the instruction that stops carrying out on Acquisition Processor, and be that the bus trigger condition of bus ETM configuration can be, while " read access postpones to surpass 50 clock period " being detected in bus, to stop the instruction and data on data acquisition bus.In order to narrate conveniently, the various instructions of carrying out in processor are summarized with " processor operations ", and the various instruction and datas that occur in bus are summarized with " bus operation ".
When meeting the processor trigger condition configuring for processor ETM, processor ETM is triggered.Equally, for other actual needs, the bus trigger condition configuring for bus ETM can be the read write command to specific memory.When meeting the bus trigger condition configuring for bus ETM, bus ETM is triggered.
In embodiments of the present invention, because processor ETM is electrically connected to bus ETM, therefore when at processor ETM and bus ETM, one of them detects the event that meets its alignment processing device trigger condition or bus trigger condition, the processor ETM being triggered or bus ETM are when completing Acquisition Processor operation or bus operation, to the bus ETM not being triggered or processor ETM, send message, message completes data acquisition bus operation or processor operations for triggering the bus ETM or the processor ETM that are not triggered.
Specifically, if processor ETM detects the processor trigger condition arranging into processor ETM, processor ETM completes the collection to processor operations, meanwhile, processor ETM sends message to bus ETM, and this message completes the collection to bus operation for Trigger Bus ETM.After completing collection, the processor operations that processor ETM is collected is buffered in processor ETB, and the bus operation that bus ETM is collected is cached in bus ETB, used for later positioning analysis.In like manner, if bus ETM detects the bus trigger condition arranging into bus ETM, bus ETM completes the collection to bus operation, meanwhile, bus ETM sends message to processor ETM, and this message completes the collection to processor operations for triggering processor ETM.After completing collection, the processor operations that processor ETM is collected is buffered in processor ETB, and the bus operation that bus ETM is collected is cached in bus ETB, used for later positioning analysis.
In a kind of possible implementation, described processor operations and described bus operation comprise respectively timestamp, and described timestamp is used for making described processor operations and described bus according to time unifying, for co-located analysis.In obtaining a kind of implementation of timestamp, the processor ETM120 shown in Fig. 1 and bus ETM150 can comprise respectively timer.Method 200 shown in Fig. 2 can comprise: the timer of the timer of described processor ETM and described bus ETM is synchronous.In addition, step 220 in method 200 can comprise: described processor ETM reads the timing value of the timer of described processor ETM, as the timestamp of described processor operations, and described bus ETM reads the timing value of the timer of described bus ETM, as the timestamp of described bus operation.
In order to realize the co-located analysis of processor and bus, can processor operations and bus operation be alignd according to time sequencing according to the timestamp in processor operations and bus operation, can observe at synchronization thus event in processor and bus.For this reason, the step 230 of method 200 can comprise: according to described timestamp by described processor operations and described bus operation time unifying, and be joint operation record by described processor operations and described bus operation unloading, wherein each joint operation record comprises timestamp, the processor operations corresponding with this timestamp and the bus operation corresponding with this timestamp.Alternatively, joint operation record can be stored in storer 140, to use during follow-up system positioning analysis.
As previously mentioned, embedded system, according to scale and concrete application scenario, can comprise a plurality of processors and/or a plurality of bus apparatus such as a plurality of storeies etc.In this case, embedded system correspondingly comprises a plurality of processor ETM and/or a plurality of bus ETM.Certainly, each ETM is correspondingly equipped with ETB separately.
In a kind of possible implementation, embedded system comprises a plurality of processor ETM and bus ETM.According to the embodiment of the present invention, each processor ETM is electrically connected to bus ETM and other processors ETM respectively, so that one of them processor ETM is when being triggered, the processor ETM being triggered sends message to bus ETM and other processors ETM, for Trigger Bus ETM and other processors ETM, complete separately data acquisition bus operation and processor operations, or when bus ETM is triggered, this bus ETM sends message to each processor ETM, for triggering each processor ETM, completes separately Acquisition Processor operation.
In the possible implementation of another kind, embedded system comprises processor ETM and a plurality of bus ETM.According to the embodiment of the present invention, each bus ETM is electrically connected to processor ETM and other buses ETM respectively, so that one of them bus ETM is when being triggered, the bus ETM being triggered sends message to processor ETM and other buses ETM, be used for triggering processor ETM and other buses ETM and complete separately Acquisition Processor operation and bus operation, or when processor ETM is triggered, this processor ETM sends message to each bus ETM, for triggering each bus ETM, completes separately data acquisition bus operation.
In the possible implementation of another kind, under complicated situation, embedded system comprises a plurality of processor ETM and a plurality of bus ETM.According to the embodiment of the present invention, each processor ETM is electrically connected to each bus ETM respectively, so that one of them processor ETM is when being triggered, the processor ETM being triggered sends message to all bus ETM and other processors ETM, be used for triggering all bus ETM and other processors ETM and complete separately data acquisition bus operation and processor operations, or when one of them bus ETM is triggered, the bus ETM being triggered sends message to whole processor ETM and other buses ETM, be used for triggering whole processor ETM and other buses ETM and complete separately data acquisition bus operation and processor operations.
According to the embodiment of the present invention, in the situation that embedded system comprises a plurality of processor ETM and/or a plurality of bus ETM, can utilize the timer in each processor ETM and/or each bus ETM, processor operations and/or bus operation increase timestamp for each processor ETM and/or each bus ETM collection, be used for by processor operations and bus operation time unifying, to realize co-located analysis.
According to the embodiment of the present invention, can show processor operations and/or the bus operation of storage, for co-located analysis.Preferably, method 200 can comprise: show the described joint operation record of storing, to facilitate, carry out system positioning analysis.
According to the embodiment of the present invention, the message that the processor ETM being triggered or bus ETM send to the bus ETM not being triggered or processor ETM, the bus ETM not being triggered described in arrival or the relative delay of bus ETM remain unchanged.After embedded system development completes, a plurality of processor ETM each other, a plurality of bus ETM each other, processor ETM and bus ETM electrical connection are each other fixed, and therefore the message delay from an ETM to another ETM does not change with regard to being fixed up.For example, although may be different from the message of ETM to the two ETM and the message delay from ETM to the three ETM, for example differ 3 clock period, but can when processor operations and bus operation being carried out to time unifying according to timestamp, adjust accordingly, so that bus operation and processor operations in joint operation record are the operation that occurs in synchronization, be conducive to like this carry out co-located analysis.
Illustrate the concrete application of the embodiment of the present invention below.
For example the bus trigger condition for bus ETM configuration is that monitoring is abnormal for specific memory X " write command ", for example, in " write command " arrival detecting storer X, but in the given time, " writing data " does not have in the situation of arrival, bus ETM is triggered and completes the collection of bus operation, and simultaneous processor ETM is also triggered and completes the collection of processor operations.By the processor operations of buffer memory in analysis processor ETB, for example, find that processor A has sent " write command " to storer X, and another processor B has also been sent " write command " to storer X simultaneously.Next, by analyzing the bus operation of buffer memory in bus ETB, find that " write command " to storer X that processor B is sent do not reach, but reside in bus.Next, return to the processor operations in check processing device ETB, find also while reference-to storage Y of processor A and B.And by the bus operation in bus ETB, find that same problem has occurred for storer Y and storer X.This shows, " write command " that processor A and B send is that order arrives, there is reversed order in " the writing data " but of sending in bus, and storer X requires first to receive " write command " that " writing data " that processor A sends could receiving processor B sends, can draw thus, so-called " butterfly deadlock " occurred between processor A and B and storer X and Y.In this case, utilize the technical scheme of the embodiment of the present invention, can go out abnormal reason by express analysis, and abnormal position occurs.
In another example, for example the processor trigger condition for processor ETM configuration is that processor " is hung dead ".Here it is out of service and no longer respond the request of other processors that said " hang dead " shows as processor, in the performance of software view, is exactly " hanging extremely (hang on) ".While there is " hanging dead " at processor, processor ETM is triggered and completes the collection of processor operations, and bus ETM is also triggered and completes the collection of bus operation simultaneously.By analysis processor ETB, can see that it is to access certain to additionally arrange standby that processor " is hung extremely " front last access.Next, by checking the bus operation in bus ETB, find that this auxiliary device has received this access instruction, and normally fed back to processor.As can be seen here, bus does not break down.And then check other bus operations in bus ETB, and for example find that termination (halt) signal of processor is set to by software maloperation effectively, cause thus processor " to hang dead ".This scene is typical " software error " but not " hard error " accelerated software location according to the method for the embodiment of the present invention.
Fig. 3 is the structural drawing of another kind of embedded system of the technical scheme of the application embodiment of the present invention.As shown in Figure 3, comprise that the embedded system 300 of positioning analysis module comprises: processor 310, for executable operations instruction; Bus 330, described bus is electrically connected to processor 310 with storer 340, for transfer instruction and data between processor 310 and storer 340; System ETM 320, and described system ETM is electrically connected to processor 310 and bus 330, for the instruction operation situation of monitoring processor 310 operation in Acquisition Processor 310, and the read-write operation on monitoring data acquisition bus 330; System ETB 322, and described system ETB is electrically connected to system ETM 320, the processor operations and the bus operation that for caching system ETM320, gather.
In this case, while meeting the event of processor trigger condition or bus trigger condition in processor or bus, system ETM is triggered, simultaneously the operation in Acquisition Processor and bus, and be buffered in system ETB, to carry out the co-located analysis of processor and bus.
Fig. 4 is according to the schematic flow diagram of the embedded system method for positioning analyzing 400 of the embodiment of the present invention.Method 400 is applied to the embedded system described in Fig. 3.As shown in Figure 4, method 400 comprises:
410: be system ETM configuration processor trigger condition and bus trigger condition;
Method for positioning analyzing also comprises that starting described system ETM Acquisition Processor operates and bus operation.
420: when system ETM detects the event that meets described processor trigger condition or described bus trigger condition, described system ETM is triggered and completes Acquisition Processor operation and bus operation;
430: store processor operations and bus operation that described system ETM gathers, for system positioning analysis.
Therefore the in the situation that of system ETM unified monitoring processor and bus, the processor operations of storing in ETB is corresponding with bus operation, can not use timer to provide timestamp for processor operations and bus operation.But, alternatively, also can be in step 420 or before step 420, start the timer of system ETM, described timer provides shared timestamp for the operation in processor and bus.In this case, system ETM is in Acquisition Processor operation and bus operation, also can read the timing value of timer, described timestamp as described processor operations and described bus operation, and the timing value of processor operations and bus operation generation is together buffered in bus ETB, to facilitate localization of fault and analysis.
According to the embodiment of the present invention, by the co-located of processor and bus is analyzed, abnormal for what occur in embedded system, increase the quantity of information that can be used for analyzing abnormal generation reason, be conducive to improve the efficiency of fault analysis and solution.
According to the embodiment of the present invention, a kind of embedded system has been proposed, this embedded system adopts the method for positioning analyzing of the aforementioned embodiment of the present invention to carry out co-located analysis to processor and bus.
Fig. 5 is according to the schematic configuration diagram of the embedded system of the embodiment of the present invention.As shown in Figure 5, embedded system 500 comprises:
Processor 510, for executable operations instruction;
The processor Embedded Trace Module ETM 520 being electrically connected to described processor, for gathering the operation of described processor, described processor ETM 520 comprises processor Embedded Trace buffer ETB522;
The bus ETM 550 being electrically connected to described bus, for gathering the operation of described bus, described bus ETM 550 comprises bus ETB 552;
Wherein said processor ETM 520 is electrically connected to described bus ETM 550, and described embedded system also comprises:
Controller 560, described controller 560 is used to described processor ETM 520 configuration processor trigger conditions, and for starting described processor ETM 520 Acquisition Processor operations and starting described bus ETM 550 data acquisition bus operations;
When described processor ETM520 detects the event that meets its corresponding processor trigger condition, described processor ETM520 has been triggered Acquisition Processor operation, the described processor ETM520 being triggered sends message to the described bus ETM550 not being triggered, and described message is used for triggering described bus ETM550 and completes data acquisition bus operation;
Described processor ETB 522 is for storing gathered described processor operations and described bus ETB 552 for storing gathered described bus operation, for system positioning analysis.
According to the embodiment of the present invention, described controller 560 is also used to described bus ETM 550 configuration bus trigger conditions, and
When described bus ETM550 detects the event that meets its corresponding bus trigger condition, described bus ETM550 has been triggered data acquisition bus operation, the described bus ETM550 being triggered sends message to the described processor ETM520 not being triggered, and described message is used for triggering described processor ETM520 and completes Acquisition Processor operation.
It will be understood by those skilled in the art that controller can comprise according in the embedded system of the embodiment of the present invention: input-output device, keyboard for example, for inputting instruction; Interfacing equipment, jtag interface for example, for access processor ETM and/or bus ETM.Controller 560 can comprise independent storer, ROM (read-only memory) (Read Only Memory for example, be called for short ROM) or read-write memory (Random Access Memory is called for short RAM) for storing command information, these command informations are for realizing the method for the embodiment of the present invention.
Alternatively, in embodiments of the present invention, for realizing the command information of the method for the embodiment of the present invention, can be stored in the storer 540 of embedded system 500.
According to a kind of concrete example, controller 560 consists of trace debug main frame, JTAG emulator, for realizing the command information of the method for the embodiment of the present invention, is stored in the storer in trace debug main frame.Trace debug main frame possesses the input-output device such as keyboard, mouse, for inputting instruction and data to embedded system.JTAG emulator, as excuse equipment, is electrically connected to trace debug main frame with embedded system, with configuration processor ETM and/or bus ETM, and for processor operations and the bus operation of the collection of read memory 540.
Alternatively, as shown in Figure 6, described processor ETM 520 and described bus ETM 550 comprise respectively timer 524 and timer 554,
Described controller 560 is for synchronous by the timer 554 of the timer of described processor ETM 520 524 and described bus ETM 550,
When described processor ETM 520 Acquisition Processor operation, described processor ETM 520 is also for reading the timing value of the timer 524 of described processor ETM 520, as the timestamp of described processor operations;
When described bus ETM 550 data acquisition bus operation, described bus ETM 550 is also for reading the timing value of the timer 554 of described bus ETM 550, as the timestamp of described bus operation.
According to the embodiment of the present invention, described controller 560 for according to described timestamp by described processor operations and described bus operation time unifying, and be joint operation record by described processor operations and described bus operation unloading, wherein each joint operation record comprises timestamp, the processor operations corresponding with this timestamp and the bus operation corresponding with this timestamp.Alternatively, according to the embodiment of the present invention, described embedded system 500 comprises a plurality of processors 510 and a plurality of processor ETMs 520 corresponding with a plurality of processors 510, wherein each processor ETM 520 is electrically connected to bus ETM 550 and other processors ETM 520 respectively, so that when a processor ETM 520 is triggered therein, other processors ETM 520 and bus ETM 550 are triggered simultaneously.
Alternatively, according to the embodiment of the present invention, described embedded system 500 comprises a plurality of buses 530 and a plurality of bus ETMs 550 corresponding with a plurality of buses 530, wherein each bus ETM 550 is electrically connected to processor ETM 520 and other buses ETM 550 respectively, so that when a bus ETM is triggered therein, other buses ETM and processor ETM are triggered simultaneously.
Alternatively, in embedded system 500, comprise a plurality of buses 530 and a plurality of bus ETMs 550 corresponding with a plurality of buses 530, and in the situation of a plurality of processors 510 and a plurality of described processor ETM 520 corresponding with a plurality of processors, each processor ETM is electrically connected to bus ETM and other processors ETM respectively, so that when a processor ETM is triggered therein, other processors ETM and bus ETM are triggered simultaneously, and each bus ETM is electrically connected to processor ETM and other buses ETM respectively, so that when a bus ETM is triggered therein, other buses ETM and processor ETM are triggered simultaneously.
Alternatively, according to the embodiment of the present invention, both are all triggered processor ETM 520 and bus ETM 550 and after continuing to gather the described processor operations and described bus operation of predetermined number, stop gathering described processor operations and described bus operation.
According to the embodiment of the present invention, as previously mentioned, to the message of the bus ETM 550 not being triggered or processor ETM 520 transmissions, the bus ETM 550 that arrival is not triggered or the relative delay of processor ETM 520 remain unchanged.
Fig. 7 is according to the schematic configuration diagram of the another kind of embedded system of the embodiment of the present invention.As shown in Figure 7, embedded system 700 comprises:
The system ETM 730 being electrically connected to processor 710 and bus 720, for gathering the operation of described processor 710 and the operation of described bus 720, described system ETM 730 comprises system ETB 732;
In described system ETM 730 detects processor, meet while meeting the event of described bus trigger condition in described processor trigger condition or described bus 720, described system ETM 730 is triggered and completes and gathers described processor operations and described bus operation;
Described processor operations and described bus operation that described system ETB 732 gathers for storing described system ETM, for system keeps track.
It will be understood by those skilled in the art that controller can comprise according in the embedded system of the embodiment of the present invention: input-output device, keyboard for example, for inputting instruction; Interfacing equipment, jtag interface for example, for access processor ETM and/or bus ETM.Controller 750 can comprise independent storer, ROM (read-only memory) (Read Only Memory for example, be called for short ROM) or read-write memory (Random Access Memory is called for short RAM) for storing command information, these command informations are for realizing the method for the embodiment of the present invention.
Alternatively, in embodiments of the present invention, for realizing the command information of the method for the embodiment of the present invention, can be stored in the storer 740 of embedded system 700.
According to a kind of concrete example, controller consists of trace debug main frame, JTAG emulator, for realizing the command information of the method for the embodiment of the present invention, is stored in the storer in trace debug main frame.Trace debug main frame possesses the input-output device such as keyboard, mouse, for inputting instruction and data to embedded system.JTAG emulator, as excuse equipment, is electrically connected to trace debug main frame with embedded system, with configuration-system ETM, and for processor operations and the bus operation of the collection of read memory 740.
Alternatively, in embodiments of the present invention, storer 740 may further include external memory storage, for example hard disk drive, the a large amount of processor operations gathering for long preservation system ETM and a large amount of bus operations, for post analysis or other specific purposes.
Alternatively, described system ETM 730 comprises timer 734,
Described controller 750 is for starting described timer 734,
When described system ETM 730 Acquisition Processor operations and bus operation, described system ETM 730 reads the timing value of described timer 734, as the described timestamp of described processor operations and described bus operation.
Those of ordinary skills can recognize, unit and the algorithm steps of each example of describing in conjunction with embodiment disclosed herein, can realize with the combination of electronic hardware or computer software and electronic hardware.These functions are carried out with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can specifically should be used for realizing described function with distinct methods to each, but this realization should not thought and exceeds scope of the present invention.
Those skilled in the art can be well understood to, and for convenience and simplicity of description, the specific works process of the system of foregoing description, device and unit, can, with reference to the corresponding process in preceding method embodiment, not repeat them here.
In the several embodiment that provide in the application, should be understood that disclosed system, apparatus and method can realize by another way.For example, device embodiment described above is only schematic, for example, the division of described unit, be only that a kind of logic function is divided, during actual realization, can have other dividing mode, for example a plurality of unit or assembly can in conjunction with or can be integrated into another system, or some features can ignore, or do not carry out.Another point, shown or discussed coupling each other or direct-coupling or communication connection can be by some interfaces, indirect coupling or the communication connection of device or unit can be electrically, machinery or other form.
The described unit as separating component explanation can or can not be also physically to separate, and the parts that show as unit can be or can not be also physical locations, can be positioned at a place, or also can be distributed in a plurality of network element.Can select according to the actual needs some or all of unit wherein to realize the object of the present embodiment scheme.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, can be also that the independent physics of unit exists, and also can be integrated in a unit two or more unit.
If described function usings that the form of SFU software functional unit realizes and during as production marketing independently or use, can be stored in a computer read/write memory medium.Understanding based on such, the part that technical scheme of the present invention contributes to prior art in essence in other words or the part of this technical scheme can embody with the form of software product, this computer software product is stored in a storage medium, comprise that some instructions are with so that a computer equipment (can be personal computer, server, or the network equipment etc.) carry out all or part of step of method described in each embodiment of the present invention.And aforesaid storage medium comprises: various media that can be program code stored such as USB flash disk, portable hard drive, ROM (read-only memory) (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disc or CDs.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion by the described protection domain with claim.
Claims (21)
1. the method for positioning analyzing of an embedded system, it is characterized in that, the processor Embedded Trace Module ETM that described embedded system comprises processor and is electrically connected to described processor, and bus and the bus ETM that is electrically connected to described bus, described processor ETM is electrically connected to described bus ETM, and described method comprises:
For described processor ETM configuration processor trigger condition;
When described processor ETM detects the event of the described processor trigger condition that meets its correspondence, described processor ETM has been triggered Acquisition Processor operation, the described processor ETM being triggered sends message to the described bus ETM not being triggered, and described message is used for triggering described bus ETM and completes data acquisition bus operation;
Storage of collected to described processor operations and the described bus operation that collects, for system positioning analysis.
2. the method for claim 1, is characterized in that, described method also comprises:
For described bus ETM configuration bus trigger condition;
When described bus ETM detects the event that meets its corresponding bus trigger condition, described bus ETM has been triggered data acquisition bus operation, the described bus ETM being triggered sends message to the described processor ETM not being triggered, and described message is used for triggering described processor ETM and completes Acquisition Processor operation.
3. method as claimed in claim 1 or 2, is characterized in that, described processor operations and described bus operation comprise respectively timestamp, and described timestamp is used for making described processor operations and described bus according to time unifying, for co-located analysis.
4. method as claimed in claim 3, is characterized in that, described processor ETM and described bus ETM comprise respectively timer, and described method comprises:
The timer of the timer of described processor ETM and described bus ETM is synchronous;
Described processor ETM reads the timing value of the timer of described processor ETM while gathering described processor operations, timestamp as described processor operations, while gathering described bus operation with described bus ETM, read the timing value of the timer of described bus ETM, as the timestamp of described bus operation.
5. the method as described in claim 3 or 4, is characterized in that,
Described storage of collected to described processor operations and the described bus operation that collects, specifically comprise:
According to described timestamp by described processor operations and described bus operation time unifying, and be joint operation record by described processor operations and described bus operation unloading, wherein each joint operation record comprises timestamp, the processor operations corresponding with this timestamp and the bus operation corresponding with this timestamp.
6. the method as described in claim 1 to 5 any one, is characterized in that,
Described embedded system comprises a plurality of processors and a plurality of described processor ETM corresponding with described a plurality of processors, wherein described in each processor ETM respectively with being electrically connected to processor ETM described in other of described bus ETM, so that when a described processor ETM is triggered therein, the described processor ETM being triggered sends described message to the described bus ETM not being triggered and other processors ETM, for triggering described bus ETM and other processors ETM, completes separately data acquisition bus operation and processor operations.
7. the method as described in claim 1 to 5 any one, is characterized in that,
Described embedded system comprises a plurality of buses and a plurality of described bus ETM corresponding with described a plurality of buses, wherein described in each, bus ETM is electrically connected to described processor ETM and bus ETM described in other respectively, so that when a described bus ETM is triggered therein, the described bus ETM being triggered sends described message to described processor ETM and bus ETM described in other, for triggering described processor ETM and other buses ETM, completes separately Acquisition Processor operation and bus operation.
8. method as claimed in claim 7, is characterized in that,
Described embedded system comprises a plurality of processors and a plurality of described processor ETM corresponding with described a plurality of processors, wherein described in each, processor ETM is electrically connected to bus ETM described in each and processor ETM described in other respectively, so that when a described processor ETM is triggered therein, the described processor ETM being triggered sends described message to described a plurality of bus ETM and other processors ETM, for triggering described a plurality of bus ETM, completes separately data acquisition bus operation and processor operations with processor ETM described in other.
9. method as claimed in claim 5, is characterized in that, described method also comprises:
Show the described joint operation record of storing.
10. the method as described in claim 1 to 9 any one, is characterized in that,
The described message that described described bus ETM to not being triggered or described processor ETM send, the described bus ETM not being triggered described in arrival or the relative delay of described processor ETM remain unchanged.
The method for positioning analyzing of 11. 1 kinds of embedded systems, is characterized in that, described embedded system comprises processor and bus, and the system ETM being electrically connected to described processor and bus, and described method comprises:
For described system ETM configuration processor trigger condition and bus trigger condition;
In described system ETM detects processor, meet while meeting the event of described bus trigger condition in described processor trigger condition or described bus, described system ETM is triggered and completes and gathers described processor operations and described bus operation;
Store described processor operations and described bus operation that described system ETM gathers, for system positioning analysis.
12. methods as claimed in claim 11, is characterized in that, described processor operations and described bus operation comprise timestamp, and described timestamp is used for making described processor operations and described bus according to time unifying, for co-located analysis.
13. methods as claimed in claim 12, is characterized in that, described system ETM comprises timer, and described method comprises:
Start the described timer of described system ETM,
Described system ETM gathers described processor operations and described bus operation and reads the timing value of described timer, as the described timestamp of described processor operations and described bus operation.
14. 1 kinds of embedded systems, is characterized in that, described embedded system comprises:
Processor, for executable operations instruction;
The processor Embedded Trace Module ETM being electrically connected to described processor, for gathering the operation of described processor, described processor ETM comprises processor Embedded Trace buffer ETB;
Bus, for being electrically connected to described processor and storer;
The bus ETM being electrically connected to described bus, for gathering the operation of described bus, described bus ETM comprises bus ETB;
Wherein said processor ETM is electrically connected to described bus ETM, and described embedded system also comprises:
Controller, described controller is used to described processor ETM configuration processor trigger condition;
When described processor ETM detects the event that meets its corresponding processor trigger condition, described processor ETM has been triggered Acquisition Processor operation, the described processor ETM being triggered sends message to the described bus ETM not being triggered, and described message is used for triggering described bus ETM and completes data acquisition bus operation;
Described processor ETB is for storing gathered described processor operations and described bus ETB for storing gathered described bus operation, for system positioning analysis.
15. embedded systems as claimed in claim 14, is characterized in that,
Described controller is also used to described bus ETM configuration bus trigger condition;
When described bus ETM detects the event that meets its corresponding bus trigger condition, described bus ETM has been triggered data acquisition bus operation, the described bus ETM being triggered sends message to the described processor ETM not being triggered, and described message is used for triggering described processor ETM and completes Acquisition Processor operation.
16. embedded systems as claimed in claim 14, is characterized in that,
Described processor ETM and described bus ETM comprise respectively timer,
Described controller is used for the timer of the timer of described processor ETM and described bus ETM is synchronous,
When described processor ETM Acquisition Processor operation, described processor ETM is also for reading the timing value of the timer of described processor ETM, as the timestamp of described processor operations;
When described bus ETM data acquisition bus operation, described bus ETM is also for reading the timing value of the timer of described bus ETM, as the timestamp of described bus operation.
17. embedded systems as claimed in claim 15, is characterized in that,
Described controller is used for according to described timestamp described processor operations and described bus operation time unifying, and described processor operations and described bus operation are saved as to joint operation record in described storer transfer, wherein each joint operation record comprises timestamp, the processor operations corresponding with this timestamp and the bus operation corresponding with this timestamp.
18. embedded systems as described in claims 14 or 15, is characterized in that,
Described embedded system also comprises:
Display, for showing the described joint operation record of described memory stores.
19. embedded systems as described in claim 14 to 18 any one, is characterized in that,
The described message that described described bus ETM to not being triggered or described processor ETM send, the described bus ETM not being triggered described in arrival or the relative delay of described processor ETM remain unchanged.
20. 1 kinds of embedded systems, is characterized in that, described embedded system comprises:
Processor, for executable operations instruction;
Bus, for being electrically connected to described processor and storer;
The system ETM being electrically connected to described processor and described bus, for gathering the operation of described processor and the operation of described bus, described system ETM comprises system ETB;
Controller, described controller is used to described system ETM configuration processor trigger condition and bus trigger condition;
In described system ETM detects processor, meet while meeting the event of described bus trigger condition in described processor trigger condition or described bus, described system ETM is triggered and completes and gathers described processor operations and described bus operation;
Described processor operations and described bus operation that described system ETB gathers for storing described system ETM, for system positioning analysis.
21. embedded systems as claimed in claim 20, is characterized in that,
Described system ETM comprises timer,
Described controller is used for starting described timer,
When described system ETM Acquisition Processor operation and bus operation, described system ETM reads the timing value of described timer, as the described timestamp of described processor operations and described bus operation.
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