CN112255455A

CN112255455A - Signal processing method, signal processor, device and storage medium

Info

Publication number: CN112255455A
Application number: CN202011232971.0A
Authority: CN
Inventors: 刘君
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2020-11-06
Filing date: 2020-11-06
Publication date: 2021-01-22
Anticipated expiration: 2040-11-06

Abstract

The embodiment of the application discloses a signal processing method, a signal processor, equipment and a storage medium, and belongs to the field of signal processing. The method comprises the following steps: acquiring an initial sampling signal; processing the initial sampling signal with the maximum signal-to-noise ratio to obtain an input signal, wherein the data bit width corresponding to the input signal after the processing with the maximum signal-to-noise ratio is lower than the data bit width threshold; and performing fast Fourier transform operation on the input signal, performing maximum signal-to-noise ratio processing in the fast Fourier transform operation process to obtain an output signal, wherein the data bit width of the output signal subjected to the maximum signal-to-noise ratio processing is smaller than the data bit width threshold. The overflow of the data bit width caused by the continuous increase of the data bit width along with each stage of calculation can be avoided, so that the occupation of the processing resource of the signal processor caused by the continuous increase of the data bit width in the FFT implementation process is avoided, and the implementation cost of the FFT is reduced.

Description

Signal processing method, signal processor, device and storage medium

Technical Field

Embodiments of the present disclosure relate to the field of signal processing, and in particular, to a signal processing method, a signal processor, a device, and a storage medium.

Background

Fast Fourier Transform (FFT) is a Fast algorithm of discrete Fourier transform, and applying FFT to the field of signal processing can simplify the calculation process in the signal processing process, such as less multiplication.

In the related art, in the process of implementing the FFT, a fixed bit width is adopted for processing each intermediate stage, a fixed scaling factor is preset for each stage, and since no processing is performed in the calculation process of each intermediate stage, the bit width of data is correspondingly increased, and in order to avoid overflow, a larger data bit width needs to be set to accommodate the processed data, which obviously increases the implementation cost of the FFT.

Disclosure of Invention

The embodiment of the application provides a signal processing method, a signal processor, equipment and a storage medium. The technical scheme is as follows:

in one aspect, an embodiment of the present application provides a signal processing method, where the method includes:

acquiring an initial sampling signal;

performing maximum signal-to-noise ratio processing on the initial sampling signal to obtain an input signal, wherein the data bit width corresponding to the input signal after the maximum signal-to-noise ratio processing is lower than a data bit width threshold;

and performing fast Fourier transform operation on the input signal, and performing maximum signal-to-noise ratio processing in the fast Fourier transform operation process to obtain an output signal, wherein the data bit width of the output signal subjected to the maximum signal-to-noise ratio processing is smaller than a data bit width threshold value.

On the other hand, an embodiment of the present application provides a signal processor, where the signal processor includes a sampling unit, a fast fourier transform operation unit, a first maximum signal-to-noise ratio processing unit, and a second maximum signal-to-noise ratio processing unit;

the sampling unit is used for acquiring an initial sampling signal;

the first maximum signal-to-noise ratio processing unit is used for carrying out maximum signal-to-noise ratio processing on the initial sampling signal to obtain an input signal;

the fast Fourier transform operation unit and the second maximum signal-to-noise ratio processing unit are used for processing the input signal to obtain an output signal.

In another aspect, embodiments of the present application provide a computer device, which includes a signal processor and a memory, where at least one instruction, at least one program, a set of codes, or a set of instructions is stored in the memory, and the at least one instruction, the at least one program, the set of codes, or the set of instructions is loaded and executed by the signal processor to implement the signal processing method according to the above aspect.

In another aspect, embodiments of the present application provide a computer-readable storage medium, in which at least one instruction, at least one program, a set of codes, or a set of instructions is stored, and the at least one instruction, the at least one program, the set of codes, or the set of instructions is loaded and executed by a signal processor to implement the signal processing method according to the above aspect.

In another aspect, according to an aspect of the present application, there is provided a computer program product or a computer program comprising computer instructions stored in a computer readable storage medium. A signal processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the signal processing method provided in the various alternative implementations of the above aspects.

The beneficial effects brought by the technical scheme provided by the embodiment of the application at least comprise:

in the FFT implementation process, the maximum signal-to-noise ratio processing is carried out on the initial sampling signal, the fixed-point loss in the FFT process is reduced, the data bit width is reduced through the maximum signal-to-noise ratio processing in the FFT process, the overflow of the data bit width caused by the fact that the data bit width is continuously increased along with each stage of calculation can be avoided, the occupation of the processing resources of a signal processor due to the fact that the data bit width is continuously increased in the FFT implementation process is avoided, and the implementation cost of the FFT is reduced.

Drawings

Fig. 1 is an expanded view showing a 16-point IFFT transform;

FIG. 2 illustrates a block diagram of a signal processor, according to an exemplary embodiment of the present application;

FIG. 3 illustrates a flow chart of a signal processing method provided by an exemplary embodiment of the present application;

FIG. 4 shows a flow chart of a signal processing method shown in another exemplary embodiment of the present application;

FIG. 5 shows a flow chart of a signal processing method shown in another exemplary embodiment of the present application;

FIG. 6 is a flow diagram illustrating a method for maximum SNR processing during a butterfly operation in accordance with an exemplary embodiment of the present application;

FIG. 7 illustrates a schematic diagram of radix operations shown in an exemplary embodiment of the present application;

FIG. 8 illustrates a schematic diagram of a phase rotation operation shown in an exemplary embodiment of the present application;

fig. 9 shows a block diagram of a signal processor provided in an exemplary embodiment of the present application;

fig. 10 shows a schematic structural diagram of a computer device provided in an exemplary embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Reference herein to "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

The FFT is a fast algorithm of discrete Fourier transform, and is obtained by improving the algorithm of the discrete Fourier transform according to the characteristics of odd, even, virtual, real and the like of the discrete Fourier transform. In the field of signal processing, when a signal is processed using FFT, the signal may be transformed from the time domain to the frequency domain for further analysis of the characteristics of the signal in the frequency domain. Optionally, the FFT algorithm includes a time-based decimation FFT algorithm and a frequency-domain decimation-based FFT algorithm. As shown in FIG. 1, which shows an expanded view of a 16-point IFFT transform, in which the time is measuredDecimation, radix-2 for example, X (0) -X (15) for 16 sampling signals,

representing twiddle factors, obtaining output signals by performing four-stage butterfly operation on 16 sampling signals, wherein each stage of butterfly operation consists of radix-2 operation and phase rotation operation.

Because each stage of butterfly operation needs to be subjected to two complex additions and one complex multiplication, if the operation data is not processed, the data bit width can be increased step by step.

In view of the problem that the data bit width in the related art increases gradually, an embodiment of the present application provides a new signal processing method, which is applied to the signal processor shown in fig. 2, as shown in fig. 2, which shows a block diagram of a structure of the signal processor shown in an exemplary embodiment of the present application, where the signal processor 200 includes: a sampling unit 201, a first maximum signal-to-noise ratio processing unit 202, an FFT operation unit 203, and a second maximum signal-to-noise ratio processing unit 204.

The sampling unit 201 is configured to perform analog-to-digital conversion on an analog signal and sample the analog signal to obtain a plurality of discrete digital signals. In the embodiment of the present application, the sampling unit 201 is configured to acquire an initial sampling signal. Alternatively, the sampling unit 201 may be an Analog-to-Digital Converter (ADC).

The first maximum snr processing unit 202 is configured to perform maximum snr processing on the input signal. In this embodiment, the first maximum snr processing unit 202 may receive the initial sampling signal transmitted by the sampling unit 201, and perform maximum snr processing on the initial sampling signal to obtain an input signal for performing an FFT process.

The FFT operation unit 203 performs a fast fourier transform operation on a plurality of discrete input signals. The FFT operation unit 203 may include a plurality of radix operators and a phase rotation unit.

The second maximum snr processing unit 204 is configured to perform maximum snr processing on the data during the FFT operation. In the embodiment of the application, in the FFT operation process, the maximum signal-to-noise ratio processing is carried out on each stage of operation, so that the gradual increase of the data bit width caused by the complex addition operation and the complex multiplication operation in the FFT process is avoided, and the control of the data bit width within the data bit width threshold is realized.

Optionally, a buffer (buffer) is further included in the signal processor 200 for storing the scaling factor of each stage.

Compared with the prior art in which only FFT operation processing is performed on an input signal, the first maximum snr processing unit 202 and the second maximum snr processing unit 204 are newly added to the signal processor 200 in the embodiment of the present application, which can avoid overflow of the data bit width due to the continuous increase of the data bit width along with each stage of calculation, thereby avoiding occupation of the processing resources of the signal processor due to the continuous increase of the data bit width in the FFT implementation process, and further reducing the implementation cost of the FFT.

It should be noted that the Signal processing method shown in the embodiment of the present Application may be applied to a Signal Processor (in a Processor chip), where the Signal Processor may be a Digital Signal Processor (DSP) or an Application Specific Integrated Circuit (ASIC), and the embodiment of the present Application is not limited thereto.

Referring to fig. 3, a flow chart of a signal processing method according to an exemplary embodiment of the present application is shown. The embodiment of the present application takes the application of the method to a signal processor as an example for explanation, and the method includes:

step 301, an initial sampling signal is obtained.

In the field of signal processing, when processing an analog signal, it is necessary to convert the analog signal into a digital signal and then perform signal processing on the digital signal, and therefore, in a possible implementation, the signal processor performs ADC sampling on the received analog signal to obtain a digital signal, i.e., an initial sampling signal.

The analog signal may be a radio frequency signal or an electromagnetic wave signal, and the type of the analog signal is not limited in the embodiment of the present application.

In the FFT processing process, in order to facilitate FFT operation, when ADC sampling is carried out on an analog signal, the number of sampled points is generally an integer power of 2, for example, the number of sampled points is 16 points and is 2^4, and then 16 initial sampled signals can be obtained.

Step 302, performing maximum signal-to-noise ratio processing on the initial sampling signal to obtain an input signal, wherein a data bit width corresponding to the input signal after the maximum signal-to-noise ratio processing is lower than a data bit width threshold.

Defining an initial data bit width as W, wherein the initial data bit width is a sampling bit width corresponding to an initial sampling signal, for example, the initial data bit width (sampling bit width) is 16 bits, which means that each sampling point acquires 2 bytes of data; the data bit width threshold is determined by the initial data bit width, and the data bit width of each level of operation data in the FFT implementation process needs to be smaller than the data bit width threshold, so that the overflow phenomenon caused by the fact that the data bit width exceeds the data bit width threshold is avoided.

In an illustrative example, the relationship between the data bit width threshold and the initial data bit may be expressed as:

max_W＝2^W-1-1

wherein max _ W represents a data bit width threshold value, and W represents an initial data bit width.

In order to avoid the loss of FFT localization, in a possible embodiment, the initial sampling signal is first processed with the maximum snr to obtain the input signal for FFT.

Of course, due to the limitation of the data bit width threshold, the data bit width corresponding to the input signal after the maximum signal-to-noise ratio processing is performed on the initial sampling signal also needs to be guaranteed to be lower than the maximum data bit width, so as to avoid overflow.

Step 303, performing fast fourier transform operation on the input signal, and performing maximum signal-to-noise ratio processing in the fast fourier transform operation process to obtain an output signal, where the data bit width of the output signal after the maximum signal-to-noise ratio processing is smaller than the data bit width threshold.

The maximum signal-to-noise ratio processing is used for reducing the data bit width of the signal in the fast Fourier transform operation process.

In the FFT implementation process, each stage of processing may cause an increase in data bit width, for example, complex multiplication or complex addition is performed on two signal values, which may cause an increase in data bit width.

In one possible embodiment, the increase of the bit width of the data after the complex multiplication is avoided by performing fast fourier transform on the input signal and performing maximum snr processing on the operation data during the FFT operation, for example, performing maximum snr processing after the complex multiplication.

In the embodiment of the application, the maximum signal-to-noise ratio processing is carried out on the initial sampling signal, the fixed-point loss in the FFT process is reduced, the data bit width is reduced through the maximum signal-to-noise ratio processing in the FFT process, the overflow of the data bit width caused by the continuous increase of the data bit width along with the calculation of each stage can be avoided, the occupation of the processing resource of the signal processor caused by the continuous increase of the data bit width in the FFT implementation process is avoided, and the implementation cost of the FFT is reduced.

In the process of implementing the FFT, there are multiple levels of butterfly operations, so as to further avoid an increase in the bit width of the operation data of each level in the middle, in a possible implementation manner, the increase in the bit width of the data in the FFT process is further controlled by performing the maximum snr processing in each level of butterfly operations.

Referring to fig. 4, a flow chart of a signal processing method according to another exemplary embodiment of the present application is shown. The embodiment of the present application takes the application of the method to a signal processor as an example for explanation, and the method includes:

step 401, an initial sampling signal is obtained.

The implementation manner of this step may refer to step 301, which is not described herein again.

Step 402, calculating an initial scaling factor corresponding to the input signal according to the initial real part signal value, the initial imaginary part signal value and an initial data bit width, wherein the initial data bit width is a sampling bit width corresponding to the initial sampling signal.

When representing the initial sampling signal, the initial sampling signal is represented in a complex form to participate in signal processing operation, for example, the initial signal may be represented as: r_si(n)＝X_si(n)+j·Y_si(n) wherein R_si(n) is an initial sampling signal, X_si(n) is the real signal value corresponding to the initial sampling signal, Y_siAnd (n) is an imaginary signal value corresponding to the initial sampling signal, and j is an imaginary unit.

Optionally, the initial sampling signals (I/Q) may share the same index, for example, if the sharing index is e, the initial sampling signals may be expressed as: r_si(n)＝I*2^e+Q*2^e。

In one possible embodiment, for each data R_si(n) when maximum signal-to-noise ratio processing is performed, the principle is as follows: each data R_siAnd (n) performing left shift to ensure that one of the I/Q most significant bits of the input data (signals) is not 0, correspondingly, in the processing process, firstly calculating to obtain an initial scaling factor corresponding to the input signals according to an initial real part signal value, an initial imaginary part signal value and an initial data bit width (sampling bit width) corresponding to the initial sampling signals, and then calculating to obtain the input signals processed by the maximum signal-to-noise ratio according to the initial scaling factor and the initial sampling signal value.

In one illustrative example, the relationship of the scaling factor to the initial sampled signal may be expressed as:

S(n)＝W-2-floor(log2(max(|X_si(n)|，|Y_si(n)|))) (1)

wherein S (n) is the initial sampling signal R_si(n) corresponding initial scaling factor, W is the initial data bit width, X_si(n) is the initial real signal value, Y_si(n) is the initial imaginary signal value, floor (x) represents a floor function, i.e., the maximum integer no greater than x, max (x) represents the maximum value, and | x | represents the absolute value.

In one possible embodiment, the initial sampling signal represented in complex form is calculated as shown in formula (1), i.e. the initial scaling factor corresponding to the input signal can be obtained.

Because a fixed scaling factor is not adopted in the embodiment of the application, a buffer for storing the scaling factor is provided, and the size of the buffer is the maximum number of FFT points supported by the signal processor.

The number of FFT points is the number corresponding to the initial sampling signal, and for the convenience of FFT operation, the initial sampling signal usually takes an integer power of 2, for example, 16 points.

In a possible application scenario, after the initial sampling signal is processed with the maximum snr, the initial scaling factor needs to be stored in the buffer, and the input signal is sent to the FFT operation unit for FFT operation.

And step 403, calculating to obtain an input signal according to the initial sampling signal and the initial scaling factor.

In a possible implementation, after the initial scaling factor is determined, the input signal after the maximum snr processing may be calculated according to the initial sampling signal and the initial scaling factor.

In an illustrative example, the relationship of the input signal, the initial scaling factor, and the initial sampling signal may be expressed as:

R_si′(n)＝R_si(n)·2^-s(n)

wherein R is_si' (n) denotes the input signal (i.e., the sampled signal after maximum signal-to-noise ratio processing), R_si(n) denotes the initial sampled signal, and s (n) denotes the initial scaling factor.

And step 404, performing k-level butterfly operation on the input signal, and performing maximum signal-to-noise ratio processing in the butterfly operation process of each level to obtain an output signal, wherein k is a positive integer and is related to the number of initial sampling signals.

The FFT operation is superposition of butterfly operations of all levels, according to the characteristics of the FFT, the FFT operation comprises several levels of butterfly operations which are related to the number of initial sampling signals and the algorithm adopted by the FFT, taking a radix-2 algorithm extracted by time as an example, if the number of the initial sampling signals is 16(2^4), the FFT operation comprises 4 levels of butterfly operations, and if the radix-4 extracted by time is taken as an example, the FFT operation comprises two levels of butterfly operations (4^ 2).

Because each stage of butterfly operation needs to be subjected to two complex additions and one complex multiplication, and in the process of performing the complex multiplication and the complex addition, the data bit width corresponding to the signal value after the operation may be increased, and the situation that the data bit width overflows or is large may occur, therefore, in order to avoid the phenomenon that the data bit width is increased due to each stage of butterfly operation, the purpose of reducing the data bit width is achieved by performing the maximum signal-to-noise ratio processing on each stage of butterfly operation result, and on the basis of considering that the data bit width is smaller than the data bit width threshold value (the overflow phenomenon does not occur), the processing resources allocated when the signal processor processes the signal can be saved.

In the embodiment, the initial sampling signal is subjected to the maximum signal-to-noise ratio processing, so that the loss of the FFT fixed-point processing can be avoided, and in addition, the maximum signal-to-noise ratio processing is performed in each stage of butterfly operation process in the FFT, so that the phenomenon of data overflow in the butterfly operation process is avoided, and the increase of the data bit width after each stage of butterfly operation processing is avoided, thereby avoiding the need of allocating more processing resources due to the increase of the data bit width, and further reducing the implementation cost of the FFT.

As can be seen from fig. 1, in the process of each stage of butterfly operation, two operation steps, namely radix (radix) operation and phase rotation operation, are required, and therefore, when the maximum snr is processed in the butterfly operation process, the maximum snr processing under the two operation conditions needs to be considered, that is, the maximum snr processing needs to be performed after each operation.

On the basis of fig. 4, as shown in fig. 5, step 404 may include steps 404A to 404D.

Step 404A, radix operation is performed on the nth stage input signal to obtain an nth stage radix operation result, wherein n is a positive integer, and the nth stage input signal is an input signal of nth stage butterfly operation.

In the process of performing maximum signal-to-noise ratio processing on butterfly operation, considering that the butterfly operation comprises radix operation and phase rotation operation, and each operation may possibly bring about an increase in data bit width, therefore, after radix operation is performed on an input signal, maximum signal-to-noise ratio processing needs to be performed on a radix operation result, and then phase rotation operation is performed on an output signal after the maximum signal-to-noise ratio processing; similarly, after the phase rotation operation is performed on the output signal, the phase rotation operation result may need to be processed with the maximum signal-to-noise ratio, and then may be used as the input signal of the next stage of butterfly operation.

Since the FFT process includes k levels of butterfly operations, i.e., an iterative process of k butterfly operations, in a possible embodiment, after the signal processor obtains the nth level of input signal, it performs radix operation on the nth level of input signal, first obtains the nth level of radix operation result, and then performs maximum snr processing on the nth level of radix operation result.

In an exemplary example, taking radix-2, 8-point FFT as an example, the FFT includes 3 levels of butterfly operations, and when n is 1, performing radix operation on a first level input signal (the first level input signal is a signal obtained by performing maximum signal-to-noise ratio processing on an initial sampling signal or an input signal of the first level of butterfly operations) to obtain a first level radix operation result, and then performing maximum signal-to-noise ratio processing on the first level radix operation result. When n is 2, the second-stage input signal is the signal obtained by the first-stage input signal after radix operation, maximum signal-to-noise ratio processing, phase rotation operation and maximum signal-to-noise ratio processing, and so on.

And step 404B, performing maximum signal-to-noise ratio processing on the nth stage radix operation result to obtain an nth stage output signal.

Different from the related art in which the radix operation result is directly subjected to the phase rotation operation, in the embodiment of the present application, in order to weaken or offset the phenomenon of data bit width increase during the radix operation on the signal value, after the radix operation result is obtained after the radix operation, the maximum signal-to-noise ratio processing needs to be performed on the radix operation result at first, the data bit width of the radix operation result is reduced, the increase of the data bit width is avoided, and the data bit width is also guaranteed not to exceed the data bit width threshold.

Corresponding to step 404A, in the implementation process, after the signal processor obtains the nth stage radix operation result, the maximum signal-to-noise ratio processing is first performed on the nth stage radix operation result, so as to obtain an output signal for performing the phase rotation operation, that is, the nth stage output signal.

In an exemplary example, when n is 1, after a radix operation is performed on the first-stage input signal to obtain a first-stage radix operation result, a maximum signal-to-noise ratio processing is performed on the first-stage radix operation result, and an output signal obtained after the maximum signal-to-noise ratio processing is used as a first-stage output signal.

And step 404C, performing phase rotation operation on the nth-level output signal to obtain an nth-level phase rotation operation result.

In each stage of butterfly operation, radix operation is performed first, and then phase rotation operation is performed, so in one possible implementation manner, the signal processor inputs the nth stage output signal after butterfly operation and maximum signal-to-noise ratio processing into the phase rotation operation unit, performs phase rotation operation, first obtains the nth stage phase rotation operation result, and then performs maximum signal-to-noise ratio processing on the nth stage phase rotation operation result.

And step 404D, performing maximum signal-to-noise ratio processing on the nth-stage phase rotation operation result to obtain an n +1 th-stage input signal, wherein the input signal obtained after performing maximum signal-to-noise ratio processing on the kth-stage phase rotation operation result is determined as an output signal.

Similar to the radix operation process, after radix operation and maximum snr processing are performed on an input signal, the obtained output signal is input to a phase rotation operation unit, and since complex multiplication exists in the phase rotation operation, the bit width of the processed signal value data may also increase, in one possible implementation, the maximum snr processing needs to be performed on the phase rotation operation result, and after the bit width of the data is reduced, the subsequent stage of butterfly operation can be performed.

In the FFT process, after the signal processor obtains the nth phase rotation operation result, it first needs to perform maximum snr processing to avoid the increase of data bit width, and then performs next stage butterfly operation after maximum snr processing.

In an exemplary example, the operation process of the nth stage butterfly operation includes: performing radix operation on the nth-stage input signal to obtain a radix operation result, performing maximum signal-to-noise ratio processing on the radix operation result to obtain an nth-stage output signal, performing phase rotation operation on the nth-stage output signal to obtain an nth-stage phase rotation operation result, and performing maximum signal-to-noise ratio processing on the nth-stage phase rotation operation result to obtain an n + 1-stage input signal, where the n + 1-stage input signal is used for performing an n + 1-stage butterfly operation, and the n + 1-stage butterfly operation process is similar to the n-stage butterfly operation process, and this embodiment is not described herein again.

It should be noted that, when the nth is equal to k, that is, when the FFT performs the last stage (k stages) of butterfly operation, the input signal obtained after radix operation-maximum signal-to-noise ratio processing-phase rotation operation-maximum signal-to-noise ratio processing is determined as the output signal of the FFT.

In this embodiment, because it is considered that each stage of butterfly operation includes radix operation and phase rotation operation, and both of the radix operation and the phase rotation operation may cause an increase in data bit width, and a situation that the data bit width exceeds a data bit width threshold may also occur, in the process of each stage of butterfly operation, a maximum signal-to-noise ratio processing step is added after radix operation and phase rotation operation, so that an increase in data bit width is more accurately prevented, and overflow of the data bit width is avoided.

In the above embodiment, the action position of the maximum snr processing in the FFT implementation process is described, that is, the maximum snr processing is required to be performed in each stage of butterfly operation, and the maximum snr processing is also required to be performed for radix operation and phase rotation operation included in each stage of butterfly operation.

Referring to fig. 6, a flowchart of a method for performing maximum snr processing in a butterfly operation process according to an exemplary embodiment of the present application is shown, where the method is applied to a signal processor as an example, and the method includes:

step 601, performing radix operation on the first input signal and the second input signal to obtain a first radix operation result and a second radix operation result.

As can be seen from fig. 1, in each butterfly operation process, the input of the butterfly operation includes two signals, i.e., the first input signal and the second input signal, and the output is also two signals, i.e., the first output signal and the second output signal, therefore, in one possible embodiment, when performing radix operation on the nth stage input signal, radix operation is performed on the first input signal and the second input signal corresponding to the nth stage input signal, and correspondingly, after radix operation, two radix operation results, i.e., the first radix operation result and the second radix operation result, are also obtained.

The process of radix operation on the first output signal and the second output signal may include the following steps:

firstly, a first scaling factor corresponding to a first input signal and a second scaling factor corresponding to a second input signal are obtained.

In a possible embodiment, in the course of performing radix operation, it is necessary to consider the scaling factor corresponding to each stage of input signal, since the scaling factor is dynamically changed and stored in the buffer, when radix operation is performed on the nth stage of input signal, it is necessary to obtain the first scaling factor and the second scaling factor corresponding to the first input signal and the second input signal (nth stage of input signal), respectively, from the buffer for performing radix operation.

Because the update calculation of the scaling factor is involved in the maximum signal-to-noise ratio processing process, the scaling factor corresponding to the nth-level input signal is the updated scaling factor obtained after the maximum signal-to-noise ratio processing is performed after the nth-1-level butterfly operation is performed, and is stored in the buffer.

And secondly, calculating to obtain a first radix operation result and a second radix operation result according to the first input signal, the second input signal, the first scaling factor and the second scaling factor.

Compared with the related art, each stage of butterfly operation adopts a fixed scaling factor, and the scaling factor is not involved in the radix operation process correspondingly.

In an exemplary example, taking the first radix operation result as an example, the radix calculation formula can be expressed as:

r′_sj+1(m)＝r_sj(m)·2^s(m)+r_sj(n)·2^s(n)

wherein r'_sj+1(m) denotes the result of the first radix operation, r_sj(m) denotes a first input signal, r_sj(n) represents the second input signal, s (m) represents the first scaling factor corresponding to the first input signal, and s (n) represents the second scaling factor corresponding to the second input signal.

Due to the feature of the butterfly operation of adding the subtraction, the second radix operation result can be expressed as:

r′_sj+1(n)＝r_sj(m)·2^s(m)-r_sj(n)·2^s(n)

wherein r'_sj+1(n) represents the result of the second radix operation.

Step 602, the maximum signal-to-noise ratio processing is performed on the first radix operation result to obtain a first output signal.

Because two operation results, namely the first radix operation result and the second radix operation result, can be obtained after radix operation, it is also necessary to perform maximum snr processing on the two radix operation results respectively in the process of performing maximum snr processing on the radix operation results.

The process of performing maximum snr processing on the first radix operation result may include the following steps:

first, a first real part signal value and a first imaginary part signal value corresponding to a first radix operation result and a data bit width corresponding to the first radix operation result are obtained.

Since the data bit width corresponding to the radix operation result needs to be paid attention in real time during the maximum snr processing, and the updated scaling factor is related to the radix operation result, in a possible implementation, when the maximum snr processing is performed on the first radix operation result, first a first real part signal value and a first imaginary part signal value corresponding to the first radix operation result need to be obtained first, so as to be used for calculating the updated scaling factor.

Since the updated scaling factor is related to the current data bit width of the first radix operation result, for example, if the data bit width of the first radix operation result is larger, the corresponding scaling factor is larger, and therefore, when the scaling factor is calculated, the data bit width corresponding to the first radix operation result also needs to be obtained.

In a possible implementation manner, after the signal processor obtains the first radix operation result, it needs to obtain a first real part signal value, a second imaginary part signal value and a data bit width corresponding to the first radix operation result.

And secondly, calculating to obtain a scaling factor corresponding to the first output signal according to the first real part signal value, the first imaginary part signal value and the data bit width corresponding to the first radix operation result.

In a possible implementation manner, after the first real part signal value, the first imaginary part signal value, and the data bit width (the first radix operation result) corresponding to the first radix operation result are obtained, the scaling factor corresponding to the first output signal may be calculated according to the scaling factor formula, so as to achieve the purpose of updating the scaling factor.

In an exemplary example, taking the first output signal as an example, the calculation formula of the scaling factor can be expressed as:

s′(m)＝W-2-floor(log2(max(|X_sj(m)|,|Y_sj(m)|))) (2)

wherein s' (m) is a scaling factor (i.e. the scaling factor updated in the maximum snr processing) corresponding to the first output signal, W is a data bit width corresponding to the first radix operation result, and X_sj(m) represents a first real signal value, Y, corresponding to the first radix operation result_sj(m) represents a first imaginary signal value corresponding to the first radix operation result.

And thirdly, calculating to obtain a first output signal according to the scaling factor corresponding to the first output signal and the first radix operation result.

In a possible embodiment, the updated scaling factor is used as an index for calculating the first output signal based on the first radix operation result and the updated scaling factor.

In an exemplary example, the relationship between the first output signal and the first radix operation result may be expressed as:

r_sj+1(m)＝r′_sj+1(m)·2^-s′(m) (3)

wherein r is_sj+1(m) denotes a first output signal, r'_sj+1(m) denotes the result of the first radix operation, and s' (m) denotes the updated scaling factor (i.e. the scaling factor corresponding to the first output signal).

Step 603, the maximum signal-to-noise ratio processing is performed on the second radix operation result to obtain a second output signal.

Similar to the maximum snr processing performed on the radix operation result in the foregoing, after the signal processor obtains the second radix operation result, the phase rotation operation is not directly performed on the second radix operation result, but the maximum snr processing is performed on the second radix operation result at first, so that the data bit width increased in the radix operation process is reduced, the second output signal processed by the maximum snr is obtained, and thus the data bit width of the second output signal is ensured to be lower than the data bit width threshold.

The method for performing maximum snr processing on the second radix operation result may include the following steps:

and firstly, acquiring a second real part signal value and a second imaginary part signal value corresponding to a second radix operation result and a data bit width corresponding to the second radix operation result.

Similar to the maximum snr processing performed on the first radix operation result in the foregoing, in the maximum snr processing performed on the second radix operation result, the second real part signal value, the second imaginary part signal value and the data bit width corresponding to the second real part signal value and the second imaginary part signal value, which are corresponding to the second radix operation result, also need to be obtained for updating the scaling factor.

And secondly, calculating to obtain a scaling factor corresponding to the second output signal according to the second real part signal value, the second imaginary part signal value and the data bit width corresponding to the second radix operation result.

In a possible implementation manner, after the second real part signal value, the second imaginary part signal value and the data bit width corresponding to the second radix operation result are obtained, the scaling factor corresponding to the second output signal can be obtained through calculation according to the scaling factor formula, so as to achieve the purpose of updating the scaling factor.

In an exemplary example, the scaling factor corresponding to the second output signal may be calculated as:

s′(n)＝W-2-floor(log2(max(|X_sj(n)|，|Y_sj(n)|)))

wherein s' (n) represents a scaling factor (i.e. an updated scaling factor in the maximum snr processing) corresponding to the second output signal, W represents a data bit width corresponding to the second radix operation result, and X represents a data bit width corresponding to the second radix operation result_sj(n) represents a second real signal value, Y, corresponding to a second radix operation result_sjAnd (n) represents a second imaginary signal value corresponding to the second radix operation result.

And thirdly, calculating to obtain a second output signal according to the scaling factor corresponding to the second output signal and the second radix operation result.

In a possible implementation manner, the updated scaling factor is used as an index for calculating the second output signal processed by the maximum signal-to-noise ratio according to the second radix operation result and the updated scaling factor.

In an exemplary example, the relationship between the second output signal and the second radix operation result may be expressed as:

r_sj+1(n)＝r′_sj+1(n)·2^-s′(n)

wherein r is_sj+1(n) denotes a second output signal, r'_sj+1(n) denotes the second radix operation result, and s' (n) denotes the updated scale factor (i.e. the scale factor corresponding to the second output signal).

In an exemplary example, as shown in FIG. 7, a schematic diagram of radix operation shown in an exemplary embodiment of the present application is shown. J denotes the jth stage butterfly, where r_sj(m) denotes a first input signal corresponding to the j-th input signal, r_sj(n) represents a second input signal corresponding to the j-th input signal, s (m) represents a first scaling factor corresponding to the first output signal, s (n) represents a second scaling factor corresponding to the second output signal, r_sj+1(m) denotes a first output signal corresponding to the j-th stage output signal, r_sj+1(n) represents the second output signal corresponding to the j-th output signal, s '(m) represents the scaling factor (the scaling factor updated during the maximum signal-to-noise ratio processing) corresponding to the first output signal, and s' (n) represents the scaling factor (the scaling factor updated during the maximum signal-to-noise ratio processing) corresponding to the second output signal. Wherein, r is_sj(m)、r_sj(n) to r_sj+1(m)、r_sj+1The process of (n) may be referred to the above examples.

Step 604, perform a phase rotation operation on the first output signal to obtain a first phase rotation operation result.

The first output signal is a signal of the first radix operation result after maximum signal-to-noise ratio processing.

In addition, in the case of not needing to perform the complex multiplication, the maximum signal-to-noise ratio processing may not be required, and the maximum signal-to-noise ratio processing may also be performed, so that the data bit width may be further reduced.

In an exemplary example, for a phase rotation unit that needs to perform a complex multiplication operation, the calculation formula of the phase rotation operation result can be expressed as:

wherein r'_sj+1(m) represents the result of the first phase rotation operation, r_sj(m) is the first output signal (i.e. the result of the first radix operation processed by the maximum snr),

for the twiddle factor in the FFT,

step 605, perform a phase rotation operation on the second output signal to obtain a second phase rotation operation result.

The second output signal is a signal obtained by performing maximum signal-to-noise ratio processing on the second radix operation result.

The calculation method for the second phase rotation calculation result may refer to the first phase rotation calculation result, which is not described herein again.

Step 606, performing maximum signal-to-noise ratio processing on the first phase rotation operation result to obtain a first input signal corresponding to the n +1 th-level input signal.

Similar to radix operation, different from the related art in which the phase rotation operation result is directly used as the input signal of the next stage butterfly operation, in the embodiment of the present application, in order to avoid an increase in data bit width, the maximum snr processing needs to be performed on the phase rotation operation result.

In a possible implementation manner, after the signal processor obtains the first phase rotation operation result, the signal processor performs maximum signal-to-noise ratio processing on the first phase rotation operation result to obtain a first input signal of a next stage butterfly operation, that is, a first input signal in the n +1 th stage input signal.

In a possible implementation, the process of performing maximum snr processing on the first phase rotation operation result may include the following steps:

and firstly, acquiring a third real part signal value and a third imaginary part signal value corresponding to the first phase rotation operation result and a data bit width corresponding to the first phase rotation operation result.

Similar to the maximum snr processing performed on the radix operation result, when the maximum snr processing is performed on the phase rotation operation result, the real part signal value and the imaginary part signal value and the data bit width corresponding to the first phase rotation operation result also need to be obtained for updating the scaling factor, that is, the third real part signal value and the third imaginary part signal value and the data bit width corresponding to the third real part signal value and the third imaginary part signal value corresponding to the first phase rotation operation result are obtained.

And secondly, calculating to obtain a first scaling factor corresponding to the first input signal in the n + 1-th-level input signal according to the data bit width corresponding to the third real part signal value, the third imaginary part signal value and the first phase rotation operation result.

In the butterfly operation process, the bit width of each level of data is dynamically changed, and the bit widths of different levels of data may have differences, but it is required to ensure that the bit width of each level of data is lower than the threshold value of the bit width of the data.

In a possible implementation manner, the data bit width corresponding to the third real part signal value, the third imaginary part signal value and the first phase rotation calculation result is input into a preset scaling factor calculation formula, and a scaling factor corresponding to the first input signal in the n +1 th-level input signal, that is, an updated scaling factor after the maximum signal-to-noise ratio processing is performed on the first phase rotation calculation result, can be obtained through calculation.

The scaling factor calculation formula may refer to formula (2) in the above embodiments, which is not described herein again.

And thirdly, calculating to obtain a first input signal corresponding to the (n + 1) th-level input signal according to a first scaling factor corresponding to the first input signal in the (n + 1) th-level input signal and the first phase rotation operation result.

In a possible embodiment, when the maximum snr is performed on the first phase rotation operation result, the updated scaling factor is used as an index to perform operation with the first phase rotation operation result, so as to obtain a signal after the maximum snr processing, that is, a first input signal corresponding to the n +1 th-stage input signal.

The formula for calculating the first output signal according to the first phase rotation operation result may refer to formula (3) in the above embodiments, which is not described herein again in this embodiment of the present application.

And 607, performing maximum signal-to-noise ratio processing on the second phase rotation operation result to obtain a second input signal corresponding to the n +1 th-level input signal.

Similar to the maximum snr processing performed on the first phase rotation operation result in the foregoing embodiment, after the signal processor obtains the second phase rotation operation result, the maximum snr processing is also performed on the second phase rotation operation result, and the second phase rotation operation result is used for input of the subsequent (n + 1) -th level butterfly operation.

The method for performing maximum snr processing on the second phase rotation operation result may include the following steps:

and firstly, acquiring a fourth real part signal value and a fourth imaginary part signal value corresponding to the second phase rotation operation result and a data bit width corresponding to the second phase rotation operation result.

Since the update of the scaling factor is involved in the process of performing the maximum snr processing on the second phase rotation operation result, and the update process of the scaling factor requires participation of a signal value and a data bit width, in a possible implementation, in the process of performing the maximum snr processing on the second phase rotation operation result, a fourth real part signal value, a fourth imaginary part signal value and a data bit width corresponding to the fourth real part signal value and the fourth imaginary part signal value, which correspond to the second phase rotation operation result, need to be obtained for calculating the updated scaling factor.

And secondly, calculating to obtain a second scaling factor corresponding to the second input signal in the n + 1-th-level input signal according to the data bit width corresponding to the fourth real part signal value, the fourth imaginary part signal value and the second phase rotation operation result.

In a possible implementation manner, after the signal processor obtains the data bit width corresponding to the fourth real part signal value, the fourth imaginary part signal value, and the second phase rotation operation result, the three data may be substituted into a preset scaling factor formula, so as to calculate an updated scaling factor, that is, a second scaling factor corresponding to a second input signal in the n +1 th-level input signal.

The above embodiments may be referred to in the formula for calculating the scaling factor according to the real signal value, the imaginary signal value, and the data bit width, which is not described herein again in this embodiment.

And thirdly, calculating to obtain a second input signal corresponding to the (n + 1) th-level input signal according to a second scaling factor corresponding to the second input signal in the (n + 1) th-level input signal and a second phase rotation operation result.

In a possible implementation manner, after the updated scaling factor is obtained, the second input signal corresponding to the n +1 th-level input signal may be obtained through calculation according to the scaling factor and the second phase rotation operation result.

The above embodiments may be referred to in terms of a formula for calculating a signal value according to a phase rotation operation result and a scaling factor, which is not described herein in detail.

In an exemplary example, as shown in fig. 8, a schematic diagram of a phase rotation operation shown in an exemplary embodiment of the present application is shown. Wherein r is_sj(m) represents a first output signal (i.e. a signal input to the phase rotation operation unit) in the jth stage of butterfly operation, s (m) represents a scaling factor corresponding to the first output signal, r_sj+1(m) represents r_sj(m) the first output signal after the phase rotation operation and the maximum signal-to-noise ratio processing, s' (m) represents a scaling factor corresponding to the first output signal,

the rotation factor is expressed, and the maximum signal-to-noise ratio processing is carried out after the phase rotation operation, and the updating of the scaling factor is involved, namely the scaling factor is updated from s (m) to s' (m).

In this embodiment, a process of performing maximum snr processing during radix operation and phase rotation operation is described, and compared with the related art, by performing maximum snr processing on radix operation results, increase of data bit width during radix operation can be avoided, and meanwhile, maximum snr processing is performed on phase rotation operation results, increase of data bit width during phase rotation operation can be avoided, so that occupation of processing resources of a signal processor due to increase of data bit width during FFT implementation is avoided, and further, implementation cost of FFT is reduced.

It should be noted that, in the embodiment of the present application, the FFT is taken as an example for illustration, and in other possible implementations, various signal processing methods provided in the embodiment of the present application are also applied in the IFFT process.

Referring to fig. 9, a block diagram of a signal processor according to an exemplary embodiment of the present application is shown. The signal processor 900 includes a sampling unit 901, a first maximum signal-to-noise ratio processing unit 902, a fast fourier transform operation unit 903, and a second maximum signal-to-noise ratio processing unit 904.

The sampling unit 901 is configured to obtain an initial sampling signal;

the first maximum snr processing unit 902 is configured to perform maximum snr processing on the initial sampling signal to obtain an input signal;

the fast fourier transform operation unit 903 and the second maximum snr processing unit 904 are configured to process the input signal to obtain an output signal.

Optionally, the fast fourier transform operation includes k-level butterfly operation, where k is a positive integer and is related to the number of the initial sampling signals;

the fft operation unit 903 and the second maximum snr processing unit 904 are further configured to:

and performing k-level butterfly operation on the input signal, and performing maximum signal-to-noise ratio processing in the butterfly operation process of each level to obtain the output signal.

Optionally, the butterfly operation includes radix operation and phase rotation operation;

performing radix operation on the nth-stage input signal to obtain an nth-stage radix operation result, wherein n is a positive integer, and the nth-stage input signal is an input signal of the nth-stage butterfly operation;

carrying out maximum signal-to-noise ratio processing on the nth stage radix operation result to obtain an nth stage output signal;

performing phase rotation operation on the nth-stage output signal to obtain an nth-stage phase rotation operation result;

and performing maximum signal-to-noise ratio processing on the nth-stage phase rotation operation result to obtain an n +1 th-stage input signal, wherein the input signal obtained after performing maximum signal-to-noise ratio processing on the kth-stage phase rotation operation result is determined as the output signal.

performing radix operation on the first input signal and the second input signal to obtain a first radix operation result and a second radix operation result;

performing maximum signal-to-noise ratio processing on the first radix operation result to obtain the first output signal;

performing maximum signal-to-noise ratio processing on the second radix operation result to obtain a second output signal;

performing phase rotation operation on the first output signal to obtain a first phase rotation operation result;

performing phase rotation operation on the second output signal to obtain a second phase rotation operation result;

performing maximum signal-to-noise ratio processing on the first phase rotation operation result to obtain a first input signal corresponding to the (n + 1) th-level input signal;

and performing maximum signal-to-noise ratio processing on the second phase rotation operation result to obtain a second input signal corresponding to the (n + 1) th-level input signal.

Optionally, the fast fourier transform operation unit 903 is further configured to:

acquiring a first scaling factor corresponding to the first input signal and a second scaling factor corresponding to the second input signal;

and calculating to obtain the first radix operation result and the second radix operation result according to the first input signal, the second input signal, the first scaling factor and the second scaling factor.

Optionally, the second maximum snr processing unit 904 is further configured to:

acquiring a first real part signal value and a first imaginary part signal value corresponding to the first radix operation result and a data bit width corresponding to the first radix operation result;

calculating to obtain a scaling factor corresponding to the first output signal according to the correspondence between the first real part signal value, the first imaginary part signal value and the first radix operation result;

calculating to obtain the first output signal according to the scaling factor corresponding to the first output signal and the first radix operation result;

acquiring a second real part signal value and a second imaginary part signal value corresponding to the second radix operation result and a data bit width corresponding to the second radix operation result;

calculating to obtain a scaling factor corresponding to the second output signal according to the second real part signal value, the second imaginary part signal value and the data bit width corresponding to the second radix operation result;

and calculating to obtain the second output signal according to the scaling factor corresponding to the second output signal and the second radix operation result.

acquiring a third real part signal value and a third imaginary part signal value corresponding to the first phase rotation operation result and a data bit width corresponding to the first phase rotation operation result;

calculating to obtain a first scaling factor corresponding to a first input signal in the n +1 th-level input signal according to the third real part signal value, the third imaginary part signal value and the data bit width corresponding to the first phase rotation operation result;

and calculating to obtain a first input signal corresponding to the n +1 th-level input signal according to a first scaling factor corresponding to the first input signal in the n +1 th-level input signal and the first phase rotation operation result.

acquiring a fourth real part signal value and a fourth imaginary part signal value corresponding to the second phase rotation operation result and a data bit width corresponding to the second phase rotation operation result;

calculating to obtain a second scaling factor corresponding to a second input signal in the n +1 th-level input signal according to the fourth real part signal value, the fourth imaginary part signal value and the data bit width corresponding to the second phase rotation operation result;

and calculating to obtain a second input signal corresponding to the n +1 th-level input signal according to a second scaling factor corresponding to the second input signal in the n +1 th-level input signal and the second phase rotation operation result.

Optionally, the first maximum snr processing unit 902 is further configured to:

calculating an initial scaling factor corresponding to the input signal according to the initial real part signal value, the initial imaginary part signal value and an initial data bit width, wherein the initial data bit width is a sampling bit width corresponding to the initial sampling signal;

and calculating to obtain the input signal according to the initial sampling signal and the initial scaling factor.

In the embodiment of the application, in the FFT implementation process, the maximum signal-to-noise ratio processing is carried out on the initial sampling signal, the fixed-point loss in the FFT process is reduced, the data bit width is reduced through the maximum signal-to-noise ratio processing in the FFT process, the overflow of the data bit width caused by the continuous increase of the data bit width along with the calculation of each stage can be avoided, the occupation of the processing resource of the signal processor caused by the continuous increase of the data bit width in the FFT implementation process is avoided, and the implementation cost of the FFT is reduced.

Referring to fig. 10, a schematic structural diagram of a computer device according to an exemplary embodiment of the present application is shown.

The computer device 1000 comprises a signal processor 1001 and a memory 1002. The signal processor 1001 may be a DSP or an ASIC, which is not limited in this embodiment of the present application, and when the signal processor 1001 operates, the signal processor 1001 may be configured to implement the signal processing method as shown in the above embodiments.

The embodiment of the present application further provides a computer-readable storage medium, which stores at least one instruction, where the at least one instruction is loaded and executed by the processor to implement the signal processing method according to the above embodiments.

Embodiments of the present application also provide a computer program product or computer program comprising computer instructions stored in a computer-readable storage medium. A signal processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the signal processing method provided in the various alternative implementations of the above aspects.

Those skilled in the art will recognize that, in one or more of the examples described above, the functions described in the embodiments of the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable storage medium. Computer-readable storage media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method of signal processing, the method comprising:

acquiring an initial sampling signal;

and performing fast Fourier transform operation on the input signal, and performing maximum signal-to-noise ratio processing in the fast Fourier transform operation process to obtain an output signal, wherein the data bit width of the output signal subjected to the maximum signal-to-noise ratio processing is smaller than the data bit width threshold.

2. The method of claim 1, wherein the fast fourier transform operation comprises a k-stage butterfly operation, k being a positive integer and related to the number of the initial sampled signals;

the fast fourier transform operation is performed on the input signal, and the maximum signal-to-noise ratio is processed in the fast fourier transform operation process to obtain an output signal, including:

3. The method of claim 2, wherein the butterfly operations comprise a radix operation and a phase rotation operation;

the performing k-level butterfly operations on the input signal and performing maximum signal-to-noise ratio processing in the butterfly operations at each level to obtain the output signal includes:

4. The method of claim 3, wherein the nth stage input signal comprises a first input signal and a second input signal, and the nth stage output signal comprises a first output signal and a second output signal;

the step of performing radix operation on the nth-stage input signal to obtain an nth-stage radix operation result includes:

the maximum signal-to-noise ratio processing is performed on the nth stage radix operation result to obtain an nth stage output signal, and the processing comprises:

the performing phase rotation operation on the nth-stage output signal to obtain an nth-stage phase rotation operation result includes:

the performing maximum signal-to-noise ratio processing on the nth-stage phase rotation operation result to obtain an n +1 th-stage input signal includes:

5. The method of claim 4, wherein performing radix operation on the first input signal and the second input signal to obtain a first radix operation result and a second radix operation result comprises:

6. The method of claim 5, wherein said performing maximum signal-to-noise ratio processing on said first radix operation result to obtain said first output signal comprises:

calculating to obtain a scaling factor corresponding to the first output signal according to the first real part signal value, the first imaginary part signal value and the data bit width corresponding to the first radix operation result;

the performing maximum signal-to-noise ratio processing on the second radix operation result to obtain the second output signal includes:

7. The method according to claim 4, wherein the performing the maximum snr processing on the first phase rotation operation result to obtain a first input signal corresponding to the n +1 th-stage input signal comprises:

calculating to obtain a first input signal corresponding to the (n + 1) th-level input signal according to a first scaling factor corresponding to the first input signal in the (n + 1) th-level input signal and the first phase rotation operation result;

the performing maximum signal-to-noise ratio processing on the second phase rotation operation result to obtain a second input signal corresponding to the (n + 1) th-level input signal includes:

8. The method according to any one of claims 1 to 7, characterized in that the initial sampled signal consists of initial real signal values and initial imaginary signal values;

the processing of the maximum signal-to-noise ratio of the initial sampling signal to obtain an input signal includes:

9. A signal processor is characterized by comprising a sampling unit, a fast Fourier transform arithmetic unit, a first maximum signal-to-noise ratio processing unit and a second maximum signal-to-noise ratio processing unit;

the sampling unit is used for acquiring an initial sampling signal;

10. A computer device comprising a signal processor and a memory, the memory having stored therein at least one instruction, at least one program, a set of codes, or a set of instructions, the at least one instruction, the at least one program, the set of codes, or the set of instructions being loaded and executed by the signal processor to implement a signal processing method according to any one of claims 1 to 8.

11. A computer-readable storage medium having stored therein at least one instruction, at least one program, a set of codes, or a set of instructions, which is loaded and executed by a signal processor to implement the signal processing method according to any one of claims 1 to 8.