CN112347413A

CN112347413A - Signal processing method, signal processor, device and storage medium

Info

Publication number: CN112347413A
Application number: CN202011231127.6A
Authority: CN
Inventors: 刘君
Original assignee: Zeku Technology Beijing Corp Ltd
Current assignee: Zeku Technology Beijing Corp Ltd
Priority date: 2020-11-06
Filing date: 2020-11-06
Publication date: 2021-02-09

Abstract

The embodiment of the application discloses a signal processing method, a signal processor, equipment and a storage medium, and belongs to the field of signal processing. The method comprises the following steps: acquiring an initial sampling signal; processing the initial sampling signal with the maximum signal-to-noise ratio to obtain an input signal, wherein the data bit width corresponding to the input signal after the processing with the maximum signal-to-noise ratio is lower than the data bit width threshold; and performing fast Fourier transform operation on the input signal, performing overflow processing in the fast Fourier transform operation process to obtain an output signal, wherein the data bit width of the output signal subjected to the overflow processing is smaller than the data bit width threshold value. The overflow of the data bit width caused by the continuous increase of the data bit width along with each stage of calculation can be avoided, so that the occupation of the processing resource of the signal processor caused by the continuous increase of the data bit width in the FFT implementation process is avoided, and the implementation cost of the FFT is reduced.

Description

Signal processing method, signal processor, device and storage medium

Technical Field

Embodiments of the present disclosure relate to the field of signal processing, and in particular, to a signal processing method, a signal processor, a device, and a storage medium.

Background

Fast Fourier Transform (FFT) is a Fast algorithm of discrete Fourier transform, and applying FFT to the field of signal processing can simplify the calculation process in the signal processing process, such as less multiplication.

In the related art, in the process of implementing the FFT, a fixed bit width is adopted for processing each intermediate stage, a fixed scaling factor is preset for each stage, and since no processing is performed in the calculation process of each intermediate stage, the bit width of data is correspondingly increased, and in order to avoid overflow, a larger data bit width needs to be set to accommodate the processed data, which obviously increases the implementation cost of the FFT.

Disclosure of Invention

The embodiment of the application provides a signal processing method, a signal processor, equipment and a storage medium. The technical scheme is as follows:

in one aspect, an embodiment of the present application provides a signal processing method, where the method includes:

acquiring an initial sampling signal;

performing maximum signal-to-noise ratio processing on the initial sampling signal to obtain an input signal, wherein the data bit width corresponding to the input signal after the maximum signal-to-noise ratio processing is lower than a data bit width threshold;

and performing fast Fourier transform operation on the input signal, performing overflow processing in the fast Fourier transform operation process to obtain an output signal, wherein the data bit width of the output signal subjected to the overflow processing is smaller than the data bit width threshold value.

On the other hand, an embodiment of the present application provides a signal processor, where the signal processor includes a sampling unit, a fast fourier transform operation unit, a maximum signal-to-noise ratio processing unit, and an overflow processing unit;

the sampling unit is used for acquiring an initial sampling signal;

the maximum signal-to-noise ratio processing unit is used for carrying out maximum signal-to-noise ratio processing on the initial sampling signal to obtain an input signal;

the fast Fourier transform operation unit and the overflow processing unit are used for processing the input signal to obtain an output signal.

In another aspect, embodiments of the present application provide a computer device, which includes a signal processor and a memory, where at least one instruction, at least one program, a set of codes, or a set of instructions is stored in the memory, and the at least one instruction, the at least one program, the set of codes, or the set of instructions is loaded and executed by the signal processor to implement the signal processing method according to the above aspect.

In another aspect, embodiments of the present application provide a computer-readable storage medium, in which at least one instruction, at least one program, a set of codes, or a set of instructions is stored, and the at least one instruction, the at least one program, the set of codes, or the set of instructions is loaded and executed by a signal processor to implement the signal processing method according to the above aspect.

In another aspect, according to an aspect of the present application, there is provided a computer program product or a computer program comprising computer instructions stored in a computer readable storage medium. A signal processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the signal processing method provided in the various alternative implementations of the above aspects.

The beneficial effects brought by the technical scheme provided by the embodiment of the application at least comprise:

in the FFT implementation process, the maximum signal-to-noise ratio processing is carried out on the initial sampling signal, the fixed point loss in the FFT process is reduced, the overflow processing is carried out in the FFT process, the overflow of the data bit width caused by the continuous increase of the data bit width along with each stage of calculation can be avoided, the occupation of the processing resource of the signal processor caused by the continuous increase of the data bit width in the FFT implementation process is avoided, and the implementation cost of the FFT is reduced.

Drawings

Fig. 1 shows an expanded view of a 16-point IFFT transform;

FIG. 2 illustrates a block diagram of a signal processor, according to an exemplary embodiment of the present application;

FIG. 3 illustrates a flow chart of a signal processing method provided by an exemplary embodiment of the present application;

FIG. 4 shows a flow chart of a signal processing method shown in another exemplary embodiment of the present application;

FIG. 5 shows a flow chart of a signal processing method shown in another exemplary embodiment of the present application;

FIG. 6 is a flow diagram illustrating a method for overflow handling during a butterfly operation in accordance with an illustrative embodiment of the present application;

FIG. 7 illustrates a schematic diagram of radix operations shown in an exemplary embodiment of the present application;

FIG. 8 illustrates a schematic diagram of a phase rotation operation shown in an exemplary embodiment of the present application;

fig. 9 shows a block diagram of a signal processor provided in an exemplary embodiment of the present application;

fig. 10 shows a schematic structural diagram of a computer device provided in an exemplary embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Reference herein to "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

The FFT is a fast algorithm of discrete Fourier transform, and is obtained by improving the algorithm of the discrete Fourier transform according to the characteristics of odd, even, virtual, real and the like of the discrete Fourier transform. In the field of signal processing, when a signal is processed using FFT, the signal may be transformed from the time domain to the frequency domain for further analysis of the characteristics of the signal in the frequency domain. Optionally, the FFT algorithm includes a time-based decimation FFT algorithm and a frequency-domain decimation-based FFT algorithm. As shown in fig. 1, which shows a development of 16-point IFFT, wherein, taking time decimation, radix-2 as an example, X (0) -X (15) are 16 sampling signals,

representing twiddle factors, obtaining output signals by performing four-stage butterfly operation on 16 sampling signals, wherein each stage of butterfly operation consists of radix-2 operation and phase rotation operation.

Because each stage of butterfly operation needs to be subjected to two complex additions and one complex multiplication, if the operation data is not processed, the data bit width can be increased step by step.

In view of the problem that the data bit width in the related art increases gradually, an embodiment of the present application provides a new signal processing method, which is applied to the signal processor shown in fig. 2, as shown in fig. 2, which shows a block diagram of a structure of the signal processor shown in an exemplary embodiment of the present application, where the signal processor 200 includes: a sampling unit 201, a maximum signal-to-noise ratio processing unit 202, an FFT operation unit 203, and an overflow processing unit 204.

The sampling unit 201 is configured to perform analog-to-digital conversion on an analog signal and sample the analog signal to obtain a plurality of discrete digital signals. In the embodiment of the present application, the sampling unit 201 is configured to acquire an initial sampling signal. Alternatively, the sampling unit 201 may be an Analog-to-Digital Converter (ADC).

The maximum snr processing unit 202 is used for performing maximum snr processing on the input signal. In this embodiment, the maximum snr processing unit 202 may receive the initial sampling signal transmitted by the sampling unit 201, and perform maximum snr processing on the initial sampling signal to obtain an input signal for performing an FFT process.

The FFT operation unit 203 performs a fast fourier transform operation on a plurality of discrete input signals. Among them, the FFT operation unit 203 may include a plurality of radix operators (basis operators) and a phase rotation unit.

The overflow processing unit 204 is used for performing overflow processing on the data. In the embodiment of the present application, in the FFT operation process, if the data bit width corresponding to the signal value exceeds the data bit width threshold in the signal processing process, an overflow process is performed on the signal value, for example, a scaling factor is increased, and the signal value is reduced.

Optionally, a buffer (buffer) is further included in the signal processor 200 for storing the scaling factor of each stage.

Compared with the prior art in which only FFT operation processing is performed on an input signal, the maximum snr processing unit 202 and the overflow processing unit 204 are newly added to the signal processor 200 in the embodiment of the present application, which can avoid overflow of the data bit width caused by the continuous increase of the data bit width along with each stage of calculation, thereby avoiding occupation of processing resources of the signal processor by the continuous increase of the data bit width in the FFT implementation process, and further reducing the implementation cost of the FFT.

It should be noted that the Signal processing method shown in the embodiment of the present Application may be applied to a Signal Processor (in a Processor chip), where the Signal Processor may be a Digital Signal Processor (DSP) or an Application Specific Integrated Circuit (ASIC), and the embodiment of the present Application is not limited thereto.

Referring to fig. 3, a flow chart of a signal processing method according to an exemplary embodiment of the present application is shown. The embodiment of the present application takes the application of the method to a signal processor as an example for explanation, and the method includes:

step 301, an initial sampling signal is obtained.

In the field of signal processing, when processing an analog signal, it is necessary to convert the analog signal into a digital signal and then perform signal processing on the digital signal, and therefore, in a possible implementation, the signal processor performs ADC sampling on the received analog signal to obtain a digital signal, i.e., an initial sampling signal.

The analog signal may be a radio frequency signal or an electromagnetic wave signal, and the type of the analog signal is not limited in the embodiment of the present application.

In the FFT processing process, in order to facilitate FFT operation, when ADC sampling is carried out on an analog signal, the number of sampled points is generally an integer power of 2, for example, the number of sampled points is 16 points and is 2^4, and then 16 initial sampled signals can be obtained.

Step 302, performing maximum signal-to-noise ratio processing on the initial sampling signal to obtain an input signal, wherein a data bit width corresponding to the input signal after the maximum signal-to-noise ratio processing is lower than a data bit width threshold.

Defining an initial data bit width as W, wherein the initial data bit width is a sampling bit width corresponding to an initial sampling signal, for example, the initial data bit width (sampling bit width) is 16 bits, which means that each sampling point acquires 2 bytes of data; the data bit width threshold is determined by the initial data bit width, and is used for determining whether the data bit width is greater than the data bit width threshold, that is, whether an overflow condition occurs in the FFT implementation process.

In one illustrative example, the data bit width threshold may be expressed as:

max_W＝2^W-1-1

wherein max _ W represents a data bit width threshold value, and W represents an initial data bit width.

In order to avoid the loss of FFT localization, in a possible embodiment, the initial sampling signal is first processed with the maximum snr to obtain the input signal for FFT.

Certainly, due to the limitation of the data bit width threshold, the data bit width corresponding to the input signal after the maximum signal-to-noise ratio processing is performed on the initial sampling signal needs to be guaranteed to be lower than the data bit width threshold, so as to avoid overflow.

And 303, performing fast Fourier transform operation on the input signal, performing overflow processing in the fast Fourier transform operation process to obtain an output signal, wherein the data bit width of the output signal subjected to the overflow processing is smaller than the data bit width threshold value.

The overflow processing is used for processing the signals with the data bit width larger than the data bit width threshold value in the fast Fourier transform operation process.

In the process of implementing the FFT, each stage of processing may cause an increase in data bit width, for example, complex multiplication is performed on two signal values, which obviously causes an increase in data bit width.

In the embodiment of the application, the maximum signal-to-noise ratio processing is carried out on the initial sampling signal, the fixed point loss in the FFT process is reduced, the overflow processing is carried out in the FFT process, the overflow of the data bit width caused by the continuous increase of the data bit width along with each stage of calculation can be avoided, the occupation of the processing resource of the signal processor caused by the continuous increase of the data bit width in the FFT implementation process is avoided, and the implementation cost of the FFT is reduced.

In the process of implementing the FFT, there are multiple levels of butterfly operations, and in order to further ensure that no overflow occurs in each level of operation in the middle, in a possible implementation manner, the overflow can be further avoided by performing overflow processing in each level of butterfly operations.

Referring to fig. 4, a flow chart of a signal processing method according to another exemplary embodiment of the present application is shown. The embodiment of the present application takes the application of the method to a signal processor as an example for explanation, and the method includes:

step 401, an initial sampling signal is obtained.

The implementation manner of this step may refer to step 301, which is not described herein again.

Step 402, calculating an initial scaling factor corresponding to the input signal according to the initial real part signal value, the initial imaginary part signal value and an initial data bit width, wherein the initial data bit width is a sampling bit width corresponding to the initial sampling signal.

When representing the initial sampling signal, the initial sampling signal is represented in a complex form to participate in signal processing operation, for example, the initial signal may be represented as: r_si(n)＝X_si(n)+j·Y_si(n) wherein R_si(n) is an initial sampling signal, X_si(n) is the real signal value corresponding to the initial sampling signal, Y_siAnd (n) is an imaginary signal value corresponding to the initial sampling signal, and j is an imaginary unit.

Alternatively, the initial sampling signals (I/Q) may share the same index,for example, if the sharing index is e, the initial sampling signal can be represented as: r_si(n)＝I*2^e+Q*2^e。

In one possible embodiment, for each data R_si(n) when maximum signal-to-noise ratio processing is performed, the principle is as follows: each data R_siAnd (n) performing left shift to ensure that one of the I/Q most significant bits of the input data (signals) is not 0, correspondingly, in the processing process, firstly calculating to obtain an initial scaling factor corresponding to the input signals according to an initial real part signal value, an initial imaginary part signal value and an initial data bit width corresponding to the initial sampling signals, and then calculating to obtain the input signals processed by the maximum signal-to-noise ratio according to the initial scaling factor and the initial sampling signal value.

In one illustrative example, the relationship of the scaling factor to the initial sampled signal may be expressed as:

S(n)＝W-2-floor(log2(max(|X_si(n)|，|Y_si(n)|))) (1)

wherein S (n) is the initial sampling signal R_si(n) corresponding initial scaling factor, W is the initial data bit width, X_si(n) is the initial real signal value, Y_si(n) is the initial imaginary signal value, floor (x) represents a floor function, i.e., the maximum integer no greater than x, max (x) represents the maximum value, and | x | represents the absolute value.

In one possible embodiment, the initial sampling signal represented in complex form is calculated as shown in formula (1), i.e. the initial scaling factor corresponding to the input signal can be obtained.

Because a fixed scaling factor is not adopted in the embodiment of the application, a buffer for storing the scaling factor is provided, and the size of the buffer is the maximum number of FFT points supported by the signal processor.

The number of FFT points is the number corresponding to the initial sampling signal, and for the convenience of FFT operation, the initial sampling signal usually takes an integer power of 2, for example, 16 points.

And step 403, calculating to obtain an input signal according to the initial sampling signal and the initial scaling factor.

In a possible implementation, after the initial scaling factor is determined, the input signal after the maximum snr processing may be calculated according to the initial sampling signal and the initial scaling factor.

In an illustrative example, the relationship of the input signal, the initial scaling factor, and the initial sampling signal may be expressed as:

R_si′(n)＝R_si(n)·2^-s(n)

wherein R is_si' (n) denotes the input signal (i.e., the signal after maximum signal-to-noise ratio processing), R_si(n) denotes the initial sampled signal, and s (n) denotes the initial scaling factor.

And step 404, performing k-level butterfly operation on the input signal, and performing overflow processing in the butterfly operation process of each level to obtain an output signal, wherein k is a positive integer and is related to the number of initial sampling signals.

The FFT operation is superposition of butterfly operations of all levels, according to the characteristics of the FFT operation, the FFT operation comprises several levels of butterfly operations which are related to the number of initial sampling signals and the algorithm adopted by the FFT operation, taking a radix-2 algorithm extracted by time as an example, if the number of the initial sampling signals is 16(2^4), the FFT operation comprises 4 levels of butterfly operations, and if the radix-4 extracted by time is taken as an example, the FFT operation comprises two levels of butterfly operations (4^ 2).

In order to avoid the overflow phenomenon in the butterfly operation process of each stage, in a possible implementation manner, by performing overflow processing in the butterfly operation process of each stage, the continuous increase of the data bit width in the butterfly operation process of each stage can be avoided.

In the embodiment, the initial sampling signal is processed with the maximum signal-to-noise ratio, so that the loss of FFT fixed-point processing can be avoided, in addition, the overflow processing is performed in each stage of butterfly operation process in the FFT, the data overflow phenomenon in the butterfly operation process is avoided, the continuous increase of the data bit width is reduced, the corresponding hardware structure is avoided being required to be set due to the increase of the data bit width, and the implementation cost of the FFT is reduced.

As can be seen from fig. 1, in the process of each stage of butterfly operation, two operation steps, namely radix (radix) operation and phase rotation operation, are required, and therefore, when performing overflow processing in the butterfly operation process, the overflow processing process under the two operation conditions needs to be considered separately, that is, the overflow processing needs to be performed after each operation.

On the basis of fig. 4, as shown in fig. 5, step 404 may include steps 404A to 404D.

Step 404A, radix operation is performed on the nth stage input signal to obtain an nth stage radix operation result, wherein n is a positive integer, and the nth stage input signal is an input signal of nth stage butterfly operation.

In the process of performing overflow processing on the butterfly operation, considering that the butterfly operation comprises radix operation and phase rotation operation, and each operation may possibly bring about an increase in data bit width, therefore, after radix operation is performed on an input signal, overflow processing needs to be performed on a radix operation result, and then phase rotation operation needs to be performed on an output signal after the overflow processing; similarly, after the phase rotation operation is performed on the output signal, the overflow processing may be performed on the phase rotation operation result, and the overflow processing may be used as the input signal of the next stage of butterfly operation.

Since the FFT process includes k levels of butterfly operations, i.e., an iterative process of k butterfly operations, in a possible embodiment, after acquiring the nth level of input signal, the signal processor performs radix operation on the nth level of input signal, first obtains the nth level of radix operation result, and then performs overflow processing on the nth level of radix operation result, where the nth level of input signal is the input signal of the nth level of butterfly operations.

In an exemplary example, taking radix-2, 16-point FFT as an example, the FFT includes 4 stages of butterfly operations, and when n is 1, radix operation is performed on a first stage input signal (the first stage input signal is an input signal after maximum snr processing is performed on an initial sampling signal or an input signal of the first stage butterfly operation) to obtain a first stage radix operation result, and then overflow processing is performed on the first stage radix operation result. When n is 2, the second-stage input signal is the signal obtained by the first-stage input signal after radix operation, overflow processing, phase rotation operation and overflow processing, and so on.

And step 404B, performing overflow processing on the n-th radix operation result to obtain an n-th output signal.

Different from the related art in which phase rotation operation is directly performed on a radix operation result, in the embodiment of the present application, in order to avoid an overflow phenomenon caused by an increase in data bit width during a radix operation performed on a signal value, after the radix operation result is obtained, overflow processing needs to be performed on the radix operation result first, so that the data bit width is prevented from exceeding a maximum data bit width, and then subsequent phase rotation operation is performed on the overflow-processed radix operation result.

Corresponding to step 404A, in the implementation process, after the signal processor obtains the nth stage radix operation result, the nth stage radix operation result is first subjected to overflow processing, so as to obtain an output signal for performing phase rotation operation, that is, an nth stage output signal.

In an exemplary example, when n is 1, after a radix operation is performed on the first-stage input signal to obtain a first-stage radix operation result, an overflow processing is performed on the first-stage radix operation result, and an output signal obtained after the overflow processing is used as a first-stage output signal.

And step 404C, performing phase rotation operation on the nth-level output signal to obtain an nth-level phase rotation operation result.

In each stage of butterfly operation, radix operation is performed first, and then phase rotation operation is performed, so in one possible implementation manner, the signal processor inputs the nth stage output signal after butterfly operation and overflow processing into the phase rotation operation unit, performs phase rotation operation, first obtains the nth stage phase rotation operation result, and then performs overflow processing.

And step 404D, performing overflow processing on the nth-stage phase rotation operation result to obtain an n +1 th-stage input signal, wherein the input signal obtained after performing overflow processing on the kth-stage phase rotation operation result is determined as an output signal.

Similar to the radix operation process described above, after radix operation and overflow processing are performed on the input signal, the obtained output signal is input to phase rotation operation, which may also result in an increase in bit width of signal data due to complex multiplication of the phase rotation operation.

In the FFT process, after the signal processor acquires the nth phase rotation operation result, it first needs to perform overflow processing to avoid that the data bit width is greater than the data bit width threshold, and then performs subsequent butterfly operation on the data after the overflow processing.

In an exemplary example, the operation process of the nth stage butterfly operation includes: performing radix operation on the nth-stage input signal to obtain a radix operation result, performing overflow processing on the radix operation result to obtain an nth-stage output signal, performing phase rotation operation on the nth-stage output signal to obtain an nth-stage phase rotation operation result, and performing overflow processing on the nth-stage phase rotation operation result to obtain an n + 1-stage input signal, where the n + 1-stage input signal is used for performing an n + 1-stage butterfly operation, and the n + 1-stage butterfly operation process is similar to the n-stage butterfly operation process, and this embodiment is not described herein again.

It should be noted that, when the nth is equal to k, that is, the FFT proceeds to the last stage (k stages) of butterfly operation, the input signal obtained after radix operation-overflow processing-phase rotation operation-overflow processing is determined as the output signal of the FFT.

In this embodiment, because it is considered that each stage of butterfly operation includes radix operation and phase rotation operation, and both of the radix operation and the phase rotation operation may cause an increase in data bit width, that is, a situation that the data bit width exceeds a data bit width threshold may occur, in the process of each stage of butterfly operation, an overflow processing step is added after radix operation and phase rotation operation, so that an overflow phenomenon of the data bit width is more accurately prevented.

In the above embodiment, the action position of the overflow processing in the FFT implementation process is described, that is, the overflow processing is required to be performed in each stage of butterfly operation, and the overflow processing is also required to be performed for the radix operation and the phase rotation operation included in each stage of butterfly operation.

Referring to fig. 6, a flowchart of a method for performing overflow processing during a butterfly operation process according to an exemplary embodiment of the present application is shown, where the method is applied to a signal processor as an example, and the method includes:

step 601, performing radix operation on the first input signal and the second input signal to obtain a first radix operation result and a second radix operation result.

As can be seen from fig. 1, in each butterfly operation process, the input of the butterfly operation includes two signals, i.e., the first input signal and the second input signal, and the output is also two signals, i.e., the first output signal and the second output signal, therefore, in one possible embodiment, when performing radix operation on the nth stage input signal, radix operation is performed on the first input signal and the second input signal corresponding to the nth stage input signal, and correspondingly, after radix operation, two radix operation results, i.e., the first radix operation result and the second radix operation result, are also obtained.

The process of radix operation on the first output signal and the second output signal may include the following steps:

firstly, a first scaling factor corresponding to a first input signal and a second scaling factor corresponding to a second input signal are obtained.

In a possible embodiment, in the course of performing radix operation, it is necessary to consider the scaling factor corresponding to each stage of input signal, since the scaling factor is dynamically changed and stored in the buffer, when radix operation is performed on the nth stage of input signal, it is necessary to obtain the first scaling factor and the second scaling factor corresponding to the first input signal and the second input signal (nth stage of input signal), respectively, from the buffer for performing radix operation.

And secondly, determining the maximum value of the first scaling factor and the second scaling factor as the nth-level scaling factor corresponding to radix operation.

In the process of radix operation, taking the maximum value of the first scaling factor and the second scaling factor as the nth-stage scaling factor corresponding to radix operation, and performing radix operation on the first input signal and the second input signal. The maximum value of the scaling factor max _ s ═ max (s (m), s (n)), where s (m) denotes the first scaling factor, s (n) denotes the second scaling factor, and max (x) denotes the maximum value.

And thirdly, calculating to obtain a first radix operation result and a second radix operation result according to the first input signal, the second input signal and the nth-level scaling factor.

In a possible embodiment, after the maximum scaling factor is obtained by calculation, the first radix operation result and the second radix operation result may be calculated according to the first output signal, the second output signal, and the nth scaling factor (the maximum value of the first scaling factor and the second scaling factor corresponding to the nth input signal).

In an exemplary example, taking the first radix operation result as an example, the radix calculation formula can be expressed as:

r′_sj+1(m)＝r_sj(m)·2^s(m)-max_s+r_sj(n)·2^s(n)-max_s

wherein r'_sj+1(m) denotes the result of the first radix operation, r_sj(m) denotes a first input signal, r_sj(n) represents the second input signal, s (m) represents the first scaling factor corresponding to the first input signal, s (n) represents the second scaling factor corresponding to the second input signal, and max _ s represents the maximum of the first scaling factor and the second scaling factor.

Due to the feature of the butterfly operation of adding the subtraction, the second radix operation result can be expressed as:

r′_sj+1(n)＝r_sj(m)·2^s(m)-max_s-r_sj(n)·2^s(n)-max_s

wherein r'_sj+1(n) represents the result of the second radix operation.

Step 602, performing overflow processing on the first radix operation result to obtain a first output signal.

Since two operation results, namely the first radix operation result and the second radix operation result, can be obtained after radix operation, in the process of performing overflow processing on radix operation results, it is also necessary to perform overflow processing on the two radix operation results respectively.

The process of performing overflow processing on the first radix operation result may include the following steps:

first, a first real part signal value and a first imaginary part signal value corresponding to a first radix operation result are obtained.

In the overflow processing process, it is necessary to determine whether the data bit width corresponding to the radix operation result exceeds the data bit width threshold, and since the signal is represented by a complex number in the signal processing process, in a possible implementation manner, the real part signal value and the imaginary part signal value in the radix operation result are obtained to subsequently determine whether the data bit width overflows, that is, to obtain the first real part signal value and the first imaginary part signal value corresponding to the first radix operation result.

And secondly, in response to the fact that the absolute value of the first real part signal value is larger than or equal to the data bit width threshold value or the absolute value of the first imaginary part signal value is larger than or equal to the data bit width threshold value, calculating to obtain a first output signal according to the nth-stage scaling factor and the first radix operation result, wherein the scaling factor corresponding to the first output signal is larger than the nth-stage scaling factor, and the first output signal is one half of the first radix operation result.

In a possible implementation manner, after a first real part signal value and a first imaginary part signal value corresponding to a first radix operation result are obtained, a relationship between a data bit width of the first real part signal value and a data bit width threshold of the first imaginary part signal value is respectively judged, so as to determine a processing manner of the first radix operation result.

In an illustrative example, the formula for determining whether to perform overflow processing can be expressed as:

abs(real(r′_sj+1(m))) is not less than max _ W or abs (ima)g(r′_sj+1(m)))≥max_W

Wherein r'_sj+1(m) represents the result of the first radix operation, max _ W represents the data bit width threshold, real (x) represents taking the real part value of the complex number, imag (x) represents taking the imaginary part value of the complex number, and abs (x) represents calculating the absolute value.

In order to avoid the situation of data overflow caused by data overflow or subsequent continuous operation, the situation of data overflow is avoided by increasing the scaling factor and reducing the signal value and the like.

In one possible embodiment, if the radix operation result has a data overflow phenomenon, the nth scaling factor (i.e. the maximum value of the first scaling factor and the second scaling factor) is added by 1 to obtain the scaling factor corresponding to the first output signal (i.e. the scaling factor is increased), and the first radix operation result is reduced to one half of the original scaling factor (i.e. the signal value is reduced) to be used as the first output signal.

In an exemplary example, when there is a data overflow condition, the processing manner of the first radix operation result and the nth level scaling factor can be expressed as:

s′(m)＝max_s+1，r_sj+1(m)＝r′_sj+1(m)/2

where s' (m) represents a scaling factor corresponding to the first output signal, max _ s represents an nth-order scaling factor, and r_sj+1(m) is a first output signal (i.e., the signal after the overflow process), r'_sj+1(m) represents the result of the first radix operation.

And thirdly, determining the scaling factor of the nth stage as the scaling factor corresponding to the first output signal and determining the first radix operation result as the first output signal in response to the absolute value of the first real part signal value being smaller than the maximum data bit width threshold and the absolute value of the first imaginary part signal value being smaller than the maximum data bit width threshold.

For the case that the first radix operation result does not have an overflow phenomenon, that is, the data bit width of the real part signal value and the imaginary part signal value is smaller than the data bit width threshold, it is not necessary to increase the scaling factor and decrease the radix operation result, therefore, in a possible implementation manner, if the absolute value of the first real part signal value is smaller than the data bit width threshold and the absolute value of the first imaginary part signal value is smaller than the data bit width threshold, the nth stage scaling factor may be directly determined as the scaling factor corresponding to the first output signal, and the first radix operation result is determined as the first output signal.

In an exemplary example, when the overflow phenomenon does not exist in the first radix operation result, the relationship between the first output signal and the first radix operation result can be expressed as:

s′(m)＝max_s，r_sj+1(m)＝r′_sj+1(m)

where s' (m) represents a scaling factor corresponding to the first output signal, max _ s represents an nth-order scaling factor (i.e., a maximum value of the first scaling factor and the second scaling factor), and r_sj+1(m) denotes a first output signal, r'_sj+1(m) represents the result of the first radix operation.

Step 603, performing overflow processing on the second radix operation result to obtain a second output signal.

Similar to the above embodiment, after the second radix operation result is obtained, the second radix operation result also needs to be subjected to overflow processing, and then the second radix operation result after overflow processing is subjected to phase rotation operation.

The overflow processing method for the second radix operation result may include the following steps:

and firstly, acquiring a second real part signal value and a second imaginary part signal value corresponding to a second radix operation result.

Similar to the process of performing the overflow processing on the first radix operation result in the foregoing embodiment, after performing the overflow processing on the second radix operation result, the relationship between the real part signal value and the imaginary part signal value corresponding to the second radix operation result and the data bit width threshold needs to be respectively determined, and then the corresponding signal processor obtains the second real part signal value and the second imaginary part signal value corresponding to the second radix operation result.

And secondly, in response to the fact that the absolute value of the second real part signal value is larger than or equal to the data bit width threshold value, or the absolute value of the second imaginary part signal value is larger than or equal to the data bit width threshold value, calculating to obtain a second output signal according to the nth-level scaling factor and a second radix operation result, wherein the scaling factor corresponding to the second output signal is larger than the nth-level scaling factor, and the second output signal is one half of the second radix operation result.

In a possible embodiment, the overflow handling manner for the operation result is determined by comparing the relationship between the operation result and the data bit width threshold after each operation, that is, the overflow handling manner for the second radix operation result is determined by correspondingly comparing the relationship between the second real part signal value and the second imaginary part signal value corresponding to the second radix operation result and the data bit width threshold.

In an exemplary example, the formula for determining whether the second radix operation result is subjected to overflow processing can be expressed as:

abs(real(r′_sj+1(n))) is not less than max _ W or abs (imag (r'_sj+1(n)))≥max_W

Wherein r'_sj+1(n) denotes a second radix operation result, max _ W denotes a data bit width threshold, real (x) denotes a real part value of a complex number, and real (r'_sj+1(n)) represents a second real signal value corresponding to the second radix operation result, imag (x) represents an imaginary value obtained by taking a complex number, and imag (r'_sj+1(n)) represents a second imaginary signal value corresponding to the second radix calculation result, abs (x) represents the absolute value, abs (real (r'_sj+1(n))) represents the absolute value of the second real signal value, abs (imag (r'_sj+1(n))) represents the absolute value of the second imaginary signal value.

If the absolute value of the second real part signal value corresponding to the second radix operation result is determined to be greater than or equal to the data bit width threshold, or the absolute value of the second imaginary part signal value is determined to be greater than or equal to the data bit width threshold, it indicates that the second radix operation result has data bit width overflow or the data bit width overflow is caused by subsequent continuous operation, and therefore, the overflow can be avoided by increasing the scaling factor and reducing the signal value.

In one possible embodiment, if the second radix operation result has a data overflow phenomenon, the nth scaling factor (i.e. the maximum value of the first scaling factor and the second scaling factor) is added by one to obtain the scaling factor corresponding to the second output signal (i.e. increase the scaling factor), and the second radix operation result is reduced to one-half of the original value (i.e. decrease the signal value) to be used as the second output signal.

In an exemplary example, when the bit width of the memory data overflows, the processing manner of the second radix operation result and the nth stage scaling factor can be expressed as:

s′(n)＝max_s+1，r_sj+1(m)＝r′_sj+1(n)/2

where s' (n) represents a scaling factor corresponding to the second output signal, max _ s represents an nth-order scaling factor, and r_sj+1(m) is a second output signal (i.e., a signal obtained by performing overflow processing on the second radix calculation result), r'_sj+1(n) represents the result of the second radix operation.

And thirdly, determining the scaling factor of the nth stage as the scaling factor corresponding to the second output signal and determining the second radix operation result as the second output signal in response to the absolute value of the second real part signal value being smaller than the data bit width threshold and the absolute value of the second imaginary part signal value being smaller than the data bit width threshold.

In another possible implementation manner, if the absolute value of the second real part signal value corresponding to the second radix operation result is smaller than the data bit width threshold and the absolute value of the second imaginary part signal value corresponding to the second radix operation result is also smaller than the data bit width threshold, it indicates that the second radix operation result does not have a phenomenon of data bit width overflow, and therefore, the second radix operation result may be directly determined as the second output signal and the nth-level scaling factor may be determined as the scaling factor of the second output signal without performing overflow processing on the second radix operation result.

In an exemplary example, when the second radix operation result does not have the data bit width overflow phenomenon, the relationship between the second output signal and the second radix operation result can be expressed as:

s′(n)＝max_s，r_sj+1(n)＝r′_sj+1(n)

where s' (n) represents a scaling factor corresponding to the second output signal, max _ s represents an nth-order scaling factor, and r_sj+1(n) denotes a second output signal, r'_sj+1(n) represents the result of the second radix operation.

In an exemplary example, as shown in FIG. 7, a schematic diagram of radix operation shown in an exemplary embodiment of the present application is shown. J denotes the jth stage butterfly, where r_sj(m) denotes a first input signal corresponding to the j-th input signal, r_sj(n) represents a second input signal corresponding to the j-th input signal, s (m) represents a first scaling factor corresponding to the first input signal, s (n) represents a second scaling factor corresponding to the second input signal, r_sj+1(m) denotes a first output signal corresponding to the j-th stage output signal, r_sj+1(n) represents a second output signal corresponding to the j-th stage output signal, s '(m) represents a scaling factor corresponding to the first output signal, and s' (n) represents a scaling factor corresponding to the second output signal. Wherein, r is_sj(m)、r_sj(n) to r_sj+1(m)、r_sj+1The process of (n) may be referred to the above examples.

Step 604, perform a phase rotation operation on the first output signal to obtain a first phase rotation operation result.

The first output signal is a signal of the first radix operation result after overflow processing.

In the phase rotation operation process, there are two cases, one is that no complex multiplication is required, and the other is that the complex multiplication is required, in which the increase of the data bit width may be brought about after the multiplication, and therefore, the overflow processing is required after the phase rotation operation unit, and in the case that the complex multiplication is not required, the overflow processing may not be required, and the overflow processing may be performed, but the input signal after the overflow processing is identical to the input signal before the overflow processing.

In an exemplary example, for a phase rotation unit that needs to perform a complex multiplication operation, the calculation formula of the phase rotation operation result can be expressed as:

wherein r'_sj+1(m) represents the result of the first phase rotation operation, r_sj(m) is the first output signal (i.e. the result of the first radix operation that has been overflow processed),

for the twiddle factor in the FFT,

step 605, perform a phase rotation operation on the second output signal to obtain a second phase rotation operation result.

The second output signal is a signal obtained by performing overflow processing on the second radix operation result.

The calculation method for the second phase rotation calculation result may refer to the first phase rotation calculation result, which is not described herein again.

Step 606, performing overflow processing on the first phase rotation operation result to obtain a first input signal corresponding to the n +1 th-level input signal.

Similar to radix operation, unlike the related art in which the phase rotation operation result is directly used as the input signal of the next stage butterfly operation, in the embodiment of the present application, in order to avoid the situation of data bit width overflow, the overflow processing needs to be performed on the phase rotation operation result.

In a possible implementation manner, after the signal processor obtains the first phase rotation operation result, the signal processor performs overflow processing on the first phase rotation operation result to obtain the first input signal of the next stage of butterfly operation, that is, the first input signal in the n +1 th stage of input signals.

In a possible implementation, the process of performing overflow processing on the first phase rotation operation result may include the following steps:

firstly, a third real part signal value and a third imaginary part signal value corresponding to the first phase rotation operation result are obtained.

Similar to the overflow processing of the radix operation result, when the overflow processing of the phase rotation operation result is performed, the relationship between the data bit width corresponding to the real part signal value and the imaginary part signal value in the phase rotation operation result and the data bit width threshold also needs to be compared, so in one possible implementation manner, after the signal processor obtains the first phase rotation operation result, a third real part signal value and a third imaginary part signal value corresponding to the first phase rotation operation result are obtained, and are used for judging whether the overflow processing is performed subsequently.

And secondly, in response to the fact that the absolute value of the third real part signal value is greater than or equal to the data bit width threshold value or the absolute value of the third imaginary part signal value is greater than or equal to the data bit width threshold value, determining a first input signal corresponding to the (n + 1) th-stage input signal and a first scaling factor corresponding to the first input signal according to a scaling factor corresponding to the first output signal and the first phase rotation operation result, wherein the first input signal is one half of the first phase rotation operation result, and the first scaling factor is greater than the scaling factor corresponding to the first output signal.

The formula for determining whether overflow occurs may refer to the above embodiments, which are not described herein again.

For the case of data bit width overflow, that is, the absolute value of the third real part signal value is greater than or equal to the data bit width threshold, or the absolute value of the third imaginary part signal value is greater than or equal to the data bit width threshold, a scaling factor needs to be increased and the signal value needs to be reduced (that is, the overflow processing is performed on the phase rotation operation result).

In an exemplary example, the processing manner of the first phase rotation operation result and the scaling factor may be expressed as:

s′(m)＝s(m)+1，r_sj+1(m)＝r′_sj+1(m)/2

where s' (m) represents the scale factor after the overflow process (the scale factor of the first input signal), s (m) represents the scale factor corresponding to the first output signal, and r_sj+1(m) representsThe overflow processed first phase rotation operation result (i.e., first input signal) r'_sj+1(m) represents a result of the first phase rotation operation.

And thirdly, in response to that the absolute value of the third real part signal value is smaller than the data bit width threshold and the absolute value of the third imaginary part signal value is smaller than the data bit width threshold, determining the first phase rotation operation result as a first input signal corresponding to the n + 1-th-level input signal, and determining a scaling factor corresponding to the first output signal as a first scaling factor corresponding to the first input signal.

In a possible implementation, the scaling factor corresponding to the first output signal may be directly determined as the scaling factor of the first input signal, and the first phase rotation operation result may be determined as the first input signal corresponding to the n +1 th-stage input signal, for a case that the data bit width of the first phase rotation operation result does not overflow, that is, the data bit width of the third real part signal value and the third imaginary part signal value corresponding to the first phase rotation operation result is smaller than the data bit width threshold.

In an illustrative example, in the case where there is no data overflow as a result of the first phase rotation operation, the first input signal and its corresponding scaling factor may be expressed as:

s′(m)＝s(m)，r_sj+1(m)＝r′_sj+1(m)

where s' (m) represents a scaling factor corresponding to the first input signal (i.e., a scaling factor after the overflow process), s (m) represents a scaling factor corresponding to the first output signal (i.e., a scaling factor before the phase rotation operation), and r_sj+1(m) denotes a first input signal (i.e., an input signal after overflow processing), r'_sj+1(m) represents the first output signal (i.e., the signal prior to the phase rotation operation).

And step 607, performing overflow processing on the second phase rotation operation result to obtain a second input signal corresponding to the n +1 th-level input signal.

The overflow processing method for the second phase rotation operation result may include the following steps:

and firstly, acquiring a fourth real part signal value and a fourth imaginary part signal value corresponding to the second phase rotation operation result.

Similar to the above overflow processing on the first phase rotation operation result, after the second phase rotation operation result is obtained, a fourth real part signal value and a fourth imaginary part signal value corresponding to the second phase rotation operation result need to be obtained, and the fourth real part signal value and the fourth imaginary part signal value are judged to determine whether the overflow processing on the second phase rotation operation result needs to be performed.

And secondly, in response to the fact that the absolute value of the fourth real part signal value is greater than or equal to the data bit width threshold value or the absolute value of the fourth imaginary part signal value is greater than or equal to the data bit width threshold value, determining a second input signal corresponding to the (n + 1) th-stage input signal and a second scaling factor corresponding to the second input signal according to the scaling factor corresponding to the second output signal and the second phase rotation operation result, wherein the second input signal is one half of the second phase rotation operation result, and the second scaling factor is greater than the scaling factor corresponding to the second output signal.

In a possible implementation manner, if the absolute value of the fourth real part signal value corresponding to the second phase rotation operation result is greater than or equal to the data bit width threshold, or the absolute value of the fourth imaginary part signal value corresponding to the second phase rotation operation result is greater than or equal to the data bit width threshold, it is determined that there is a possibility of data bit width overflow in the second phase rotation operation result, and the second input signal for inputting the next-stage butterfly operation is obtained by performing overflow processing on the second phase rotation operation result.

The overflow processing method for the second phase rotation operation result comprises the following steps: and halving the signal value of the second phase rotation operation result, that is, the second input signal corresponding to the n +1 th-level input signal is half of the second phase rotation operation result, and increasing the scaling factor, that is, the scaling factor of the second input signal is greater than that of the second output signal, for example, adding one to the scaling factor of the second output signal (the n +1 th-level output signal) to obtain the scaling factor of the second input signal (the n +1 th-level input signal).

And thirdly, in response to that the absolute value of the fourth real part signal value is smaller than the data bit width threshold and the absolute value of the fourth imaginary part signal value is smaller than the data bit width threshold, determining the second phase rotation operation result as a second input signal corresponding to the n + 1-th-level input signal, and determining a scaling factor corresponding to the second output signal as a second scaling factor corresponding to the second input signal.

In another possible implementation, if it is determined that the absolute value of the fourth real signal value corresponding to the second phase rotation operation result is smaller than the data bit width threshold and the absolute value of the fourth imaginary signal value is also smaller than the data bit width threshold, which indicates that there is no data bit width overflow phenomenon in the second phase rotation operation result and no overflow processing is required on the second phase rotation operation result, the second phase rotation operation result is correspondingly determined as the second input signal corresponding to the n + 1-th stage input signal (i.e., the signal value is unchanged), and the scaling factor corresponding to the second output signal (the nth stage output signal) is determined as the second scaling factor corresponding to the second input signal (the n + 1-th stage input signal) (the scaling factor is unchanged).

In an exemplary example, as shown in fig. 8, a schematic diagram of a phase rotation operation shown in an exemplary embodiment of the present application is shown. Wherein r is_sj(m) represents a first output signal (i.e. a signal input to the phase rotation operation unit) in the jth stage of butterfly operation, s (m) represents a scaling factor corresponding to the first output signal, r_sj+1(m) represents r_sj(m) the first output signal after the phase rotation operation and the overflow process, s' (m) represents a scaling factor corresponding to the first output signal,

representing the twiddle factor.

In this embodiment, a process of performing overflow processing in the process of radix operation and phase rotation operation is described, and compared with the related art, by performing overflow processing on a radix operation result, increase of a data bit width in the process of radix operation can be avoided, and meanwhile, overflow processing is performed on a phase rotation operation result, increase of a data bit width in the process of phase rotation operation can be avoided, so that occupation of processing resources of a signal processor by increase of the data bit width in the process of implementing FFT is avoided, and further, implementation cost of FFT is reduced.

It should be noted that, in the embodiment of the present application, the FFT is taken as an example for illustration, and in other possible implementations, various signal processing methods provided in the embodiment of the present application are also applied in the IFFT process.

Referring to fig. 9, a block diagram of a signal processor according to an exemplary embodiment of the present application is shown. The signal processor includes a sampling unit 901, a maximum signal-to-noise ratio processing unit 902, a fast fourier transform operation unit 903, and an overflow processing unit 904.

The sampling unit 901 is configured to obtain an initial sampling signal;

the maximum signal-to-noise ratio processing unit 902 is configured to perform maximum signal-to-noise ratio processing on the initial sampling signal to obtain an input signal;

the fast fourier transform operation unit 903 and the overflow processing unit 904 are configured to process the input signal to obtain an output signal.

Optionally, the fast fourier transform operation includes k-level butterfly operation, where k is a positive integer and is related to the number of the initial sampling signals;

the fast fourier transform operation unit 903 and the overflow processing unit 904 are further configured to:

and performing k-level butterfly operation on the input signal, and performing overflow processing in the butterfly operation process of each level to obtain the output signal.

Optionally, the butterfly operation includes a radix operation and a phase rotation operation;

performing radix operation on the nth-stage input signal to obtain an nth-stage radix operation result, wherein n is a positive integer, and the nth-stage input signal is an input signal of the nth-stage butterfly operation;

carrying out overflow processing on the n-th radix operation result to obtain an n-th output signal;

performing phase rotation operation on the nth-stage output signal to obtain an nth-stage phase rotation operation result;

and performing overflow processing on the nth-stage phase rotation operation result to obtain an n +1 th-stage input signal, wherein the input signal obtained after performing overflow processing on the kth-stage phase rotation operation result is determined as the output signal.

performing radix operation on the first input signal and the second input signal to obtain a first radix operation result and a second radix operation result;

performing overflow processing on the first radix operation result to obtain the first output signal;

performing overflow processing on the second radix operation result to obtain a second output signal;

performing phase rotation operation on the first output signal to obtain a first phase rotation operation result;

performing phase rotation operation on the second output signal to obtain a second phase rotation operation result;

performing overflow processing on the first phase rotation operation result to obtain a first input signal corresponding to the (n + 1) th-level input signal;

and performing overflow processing on the second phase rotation operation result to obtain a second input signal corresponding to the (n + 1) th-level input signal.

Optionally, the fast fourier transform operation unit 903 is further configured to:

acquiring a first scaling factor corresponding to the first input signal and a second scaling factor corresponding to the second input signal;

determining the maximum value of the first scaling factor and the second scaling factor as the nth level scaling factor corresponding to radix operation;

and calculating to obtain the first radix operation result and the second radix operation result according to the first input signal, the second input signal and the nth-stage scaling factor.

Optionally, the overflow handling unit 904 is further configured to:

acquiring a first real part signal value and a first imaginary part signal value corresponding to the first radix operation result;

in response to that the absolute value of the first real part signal value is greater than or equal to the data bit width threshold, or the absolute value of the first imaginary part signal value is greater than or equal to the data bit width threshold, calculating to obtain the first output signal according to the nth-stage scaling factor and the first radix operation result, where the scaling factor corresponding to the first output signal is greater than the nth-stage scaling factor, and the first output signal is one half of the first radix operation result;

in response to the absolute value of the first real part signal value being less than the data bit width threshold and the absolute value of the first imaginary part signal value being less than the data bit width threshold, determining the nth stage scaling factor as the scaling factor corresponding to the first output signal and determining the first radix operation result as the first output signal;

the overflow handling unit 904 is further configured to:

acquiring a second real part signal value and a second imaginary part signal value corresponding to the second radix operation result;

in response to that the absolute value of the second real part signal value is greater than or equal to the data bit width threshold, or the absolute value of the second imaginary part signal value is greater than or equal to the data bit width threshold, calculating to obtain the second output signal according to the nth-level scaling factor and the second radix operation result, where the scaling factor corresponding to the second output signal is greater than the nth-level scaling factor, and the second output signal is one half of the second radix operation result;

and in response to the absolute value of the second real part signal value being smaller than the data bit width threshold and the absolute value of the second imaginary part signal value being smaller than the data bit width threshold, determining the nth stage scaling factor as the scaling factor corresponding to the second output signal and determining the second radix operation result as the second output signal.

Optionally, the overflow handling unit 904 is further configured to:

acquiring a third real part signal value and a third imaginary part signal value corresponding to the first phase rotation operation result;

in response to that the absolute value of the third real part signal value is greater than or equal to the data bit width threshold, or the absolute value of the third imaginary part signal value is greater than or equal to the data bit width threshold, determining a first input signal corresponding to the n +1 th stage input signal and a first scaling factor corresponding to the first input signal according to a scaling factor corresponding to the first output signal and the first phase rotation operation result, where the first input signal is half of the first phase rotation operation result, and the first scaling factor is greater than the scaling factor corresponding to the first output signal;

in response to the absolute value of the third real signal value being less than the data bit width threshold and the absolute value of the third imaginary signal value being less than the data bit width threshold, determining the first phase rotation operation result as the first input signal corresponding to the n +1 th stage input signal and determining the scaling factor corresponding to the first output signal as the first scaling factor corresponding to the first input signal;

the overflow handling unit 904 is further configured to:

acquiring a fourth real part signal value and a fourth imaginary part signal value corresponding to the second phase rotation operation result;

in response to that the absolute value of the fourth real part signal value is greater than or equal to the data bit width threshold or the absolute value of the fourth imaginary part signal value is greater than or equal to the data bit width threshold, determining a second input signal corresponding to the n +1 th-level input signal and a second scaling factor corresponding to the second input signal according to a scaling factor corresponding to the second output signal and the second phase rotation operation result, where the second input signal is one-half of the second phase rotation operation result, and the second scaling factor is greater than the scaling factor corresponding to the second output signal;

in response to the absolute value of the fourth real signal value being less than the data bit width threshold and the absolute value of the fourth imaginary signal value being less than the data bit width threshold, determining the second phase rotation operation result as the second input signal corresponding to the n +1 th stage input signal and determining the scaling factor corresponding to the second output signal as the second scaling factor corresponding to the second input signal.

Optionally, the maximum snr processing unit 902 is further configured to:

calculating an initial scaling factor corresponding to the input signal according to the initial real part signal value, the initial imaginary part signal value and an initial data bit width, wherein the initial data bit width is a sampling bit width corresponding to the initial sampling signal;

and calculating to obtain the input signal according to the initial sampling signal and the initial scaling factor.

Referring to fig. 10, a schematic structural diagram of a computer device according to an exemplary embodiment of the present application is shown.

The computer device 1000 comprises a signal processor 1001 and a memory 1002. The signal processor 1001 may be a DSP or an ASIC, which is not limited in this embodiment of the present application, and when the signal processor 1001 operates, the signal processor 1001 may be configured to implement the signal processing method as shown in the above embodiments.

The embodiment of the present application further provides a computer-readable storage medium, which stores at least one instruction, where the at least one instruction is loaded and executed by the processor to implement the signal processing method according to the above embodiments.

Embodiments of the present application also provide a computer program product or computer program comprising computer instructions stored in a computer-readable storage medium. A signal processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the signal processing method provided in the various alternative implementations of the above aspects.

Those skilled in the art will recognize that, in one or more of the examples described above, the functions described in the embodiments of the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable storage medium. Computer-readable storage media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method of signal processing, the method comprising:

acquiring an initial sampling signal;

2. The method of claim 1, wherein the fast fourier transform operation comprises a k-stage butterfly operation, k being a positive integer and related to the number of the initial sampled signals;

the performing fast fourier transform operation on the input signal and performing overflow processing in the fast fourier transform operation process to obtain an output signal includes:

3. The method of claim 2, wherein the butterfly operations comprise a radix operation and a phase rotation operation;

the performing k-level butterfly operations on the input signal and performing overflow processing in the course of each level of butterfly operations to obtain the output signal includes:

4. The method of claim 3, wherein the nth stage input signal comprises a first input signal and a second input signal, and the nth stage output signal comprises a first output signal and a second output signal;

the step of performing radix operation on the nth-stage input signal to obtain an nth-stage radix operation result includes:

the performing overflow processing on the n-th stage radix operation result to obtain an n-th stage output signal includes:

the performing phase rotation operation on the nth-stage output signal to obtain an nth-stage phase rotation operation result includes:

the performing overflow processing on the nth-stage phase rotation operation result to obtain an n + 1-stage input signal includes:

5. The method of claim 4, wherein performing radix operation on the first input signal and the second input signal to obtain a first radix operation result and a second radix operation result comprises:

6. The method of claim 5, wherein said performing overflow processing on the first radix operation result to obtain the first output signal comprises:

performing overflow processing on the second radix operation result to obtain the second output signal, including:

7. The method according to claim 4, wherein the performing overflow processing on the first phase rotation operation result to obtain a first input signal corresponding to the n +1 th-stage input signal comprises:

performing overflow processing on the second phase rotation operation result to obtain a second input signal corresponding to the n +1 th-level input signal, including:

8. The method according to any one of claims 1 to 7, characterized in that the initial sampled signal consists of initial real signal values and initial imaginary signal values;

the processing of the maximum signal-to-noise ratio of the initial sampling signal to obtain an input signal includes:

9. The signal processor is characterized by comprising a sampling unit, a fast Fourier transform arithmetic unit, a maximum signal-to-noise ratio processing unit and an overflow processing unit;

the sampling unit is used for acquiring an initial sampling signal;

10. A computer device comprising a signal processor and a memory, the memory having stored therein at least one instruction, at least one program, a set of codes, or a set of instructions, the at least one instruction, the at least one program, the set of codes, or the set of instructions being loaded and executed by the signal processor to implement a signal processing method according to any one of claims 1 to 8.

11. A computer-readable storage medium having stored therein at least one instruction, at least one program, a set of codes, or a set of instructions, which is loaded and executed by a signal processor to implement the signal processing method according to any one of claims 1 to 8.