CN113901389A - Signal processing method and device, electronic equipment and readable storage medium - Google Patents
Signal processing method and device, electronic equipment and readable storage medium Download PDFInfo
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Abstract
The embodiment of the invention discloses a signal processing method, a signal processing device, electronic equipment and a readable storage medium. The method comprises the following steps: acquiring an input signal sequence, extracting a butterfly operation structure of a Fast Fourier Transform (FFT) algorithm according to a frequency domain, and processing the input signal sequence through the butterfly operation structure to obtain an intermediate result signal sequence; reordering elements of the intermediate result signal sequence according to the discrete Fourier transform type; and performing numerical correction on the reordered intermediate result signal sequence according to the discrete Fourier transform type to obtain a final output signal. By the technical scheme of the embodiment of the invention, the results of different discrete Fourier transform types of the input signal can be obtained simultaneously on the basis of not changing the input signal and the FFT calculation process, the calculation rate is improved, and the extra calculation expense is reduced.
Description
Technical Field
Embodiments of the present invention relate to the field of signal processing technologies, and in particular, to a signal processing method and apparatus, an electronic device, and a readable storage medium.
Background
Currently, Fast Fourier Transform (FFT) is often used for calculating DFT to increase the calculation speed and reduce the consumption of hardware (memory) resources. When calculating Inverse Discrete Fourier Transform (IDFT), two fast calculation methods of multiplexing FFT calculation structure are often adopted, one is to change butterfly operationSpecifically, the multiplicative coefficient of (c) is: the input signal of IDFT to be solved is operated according to the FFT calculation structure, and meanwhile, the IDFT is operated in the FFT calculation structure
Is replaced by
Finally, dividing the result output by the FFT calculation structure by N; another method is to take the conjugate of the input signal and then calculate the FFT, and finally take the conjugate of the FFT result.
However, if the IDFT is calculated by changing the multiplicative coefficient of the butterfly operation, the FFT calculation process is changed; if the IDFT is calculated by conjugating the input signal, calculating the FFT, and finally inverting the FFT result to conjugate, the input signal needs to be changed in value, and both methods bring extra storage or calculation overhead. Therefore, how to obtain the DFT result and the IDFT result of the input signal simultaneously without changing the input signal and the FFT calculation process has been a difficult point to be studied.
Disclosure of Invention
Embodiments of the present invention provide a signal processing method, an apparatus, an electronic device, and a readable storage medium, which can simultaneously obtain results of different discrete fourier transform types of an input signal without changing the input signal and FFT computation process.
In a first aspect, an embodiment of the present invention provides a signal processing method, including:
acquiring an input signal sequence, extracting a butterfly operation structure of a Fast Fourier Transform (FFT) algorithm according to a frequency domain, and processing the input signal sequence through the butterfly operation structure to obtain an intermediate result signal sequence;
reordering elements of the intermediate result signal sequence according to the discrete Fourier transform type;
and performing numerical correction on the reordered intermediate result signal sequence according to the discrete Fourier transform type to obtain a final output signal.
In a second aspect, an embodiment of the present invention further provides a signal processing apparatus, where the apparatus includes:
the frequency domain extraction butterfly operation module is used for acquiring an input signal sequence, extracting a butterfly operation structure of a Fast Fourier Transform (FFT) algorithm according to a frequency domain, and processing the input signal sequence through the butterfly operation structure to obtain an intermediate result signal sequence;
the element reordering module is used for reordering the elements of the intermediate result signal sequence according to the discrete Fourier transform type;
and the numerical value correction module is used for performing numerical value correction on the reordered intermediate result signal sequence according to the discrete Fourier transform type to obtain a final output signal.
In a third aspect, an embodiment of the present invention further provides an electronic device, including:
one or more processors;
a storage device for storing one or more programs,
when executed by the one or more processors, cause the one or more processors to implement a method according to any one of the embodiments of the invention.
In a fourth aspect, the embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the method according to any embodiment of the present invention.
According to the technical scheme of the embodiment of the invention, the butterfly operation structure of the FFT algorithm is extracted according to the frequency domain, the input signal is processed to obtain the intermediate result signal sequence, and the intermediate result signal sequence is subjected to element reordering and numerical correction according to the discrete Fourier transform type to obtain the final output signal.
Drawings
Fig. 1a is a flowchart of a signal processing method according to an embodiment of the present invention;
FIG. 1b is a diagram illustrating a DFT butterfly structure according to an embodiment of the present invention;
FIG. 1c is a schematic diagram of a butterfly operation structure of a radix-2 FFT algorithm according to frequency domain decimation according to an embodiment of the present invention;
fig. 2a is a flow chart of a preferred signal processing method according to an embodiment of the present invention;
FIG. 2b is a schematic diagram of a signal processing flow according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a signal processing apparatus according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1a is a flowchart of a signal processing method according to an embodiment of the present invention, fig. 1b is a schematic diagram of a DFT butterfly operation structure according to an embodiment of the present invention, and fig. 1c is a schematic diagram of a butterfly operation structure of a radix-2 FFT algorithm according to frequency domain decimation according to an embodiment of the present invention. The present embodiment is applicable to the case of obtaining the results of different discrete fourier transform types of the input signal simultaneously without changing the input signal and the FFT calculation process, and the method may be performed by a signal processing apparatus, which may be implemented in hardware and/or software and may be generally integrated in an electronic device.
As shown in fig. 1a, a signal processing method provided in an embodiment of the present invention includes the following specific steps:
s110: the method comprises the steps of obtaining an input signal sequence, extracting a butterfly operation structure of a Fast Fourier Transform (FFT) algorithm according to a frequency domain, and processing the input signal sequence through the butterfly operation structure to obtain an intermediate result signal sequence.
The input signal may refer to a discrete signal obtained by sampling an analog signal at a certain sampling rate; the input signal sequence may refer to a sequence obtained by arranging input signals according to their serial numbers; the fast Fourier transform FFT algorithm extracted according to the frequency domain can be a frequency domain extraction basis-2 FFT algorithm, and can also be a conventional algorithm such as a frequency domain extraction basis-4 FFT algorithm; the intermediate result signal sequence may refer to a signal sequence obtained after butterfly structure processing.
It can be understood that, in the embodiment of the present invention, the butterfly operation structure of the FFT algorithm according to the frequency domain decimation is determined by the type of the transform performed on the input signal. For example, in the embodiment of the present invention, taking the DFT of the input signal as an example, the basic principle of DFT may be as follows:
wherein X (k) is the DFT conversion result of the input signal, N is the number of sampling points of the input signal, N is the serial number of the input signal, k is the frequency of the frequency, i.e. the k-th frequency, W is the rotation factor,
and the number of the first and second electrodes,
has the following properties:
1) conjugate symmetry:
2) the periodicity is as follows:
3) reducibility:
the DFT rationale can be modified by the above properties as follows:
further, x (k) may be divided into two parts according to the parity of k, for example, k is 2r and k is 2r +1, where r is 0, 1.
In summary, the calculation of N points X (k) can be converted into x1(n)、x2N/2-point DFT calculation of (N). x is the number of1(n)、x2The butterfly structure itself is shown in fig. 1b, where a ═ x (N), b ═ x (N + N/2), and a ═ x1(n)，B＝x2(n) is the same as the butterfly operation structure of the frequency-domain-based extracted radix-2 FFT algorithm shown in fig. 1c, wherein fig. 1c illustrates an 8-point FFT calculation as an example. Therefore, the input signal sequence can be processed by extracting the butterfly operation structure of the Fast Fourier Transform (FFT) algorithm according to the frequency domain, and a DFT result is obtained.
Therefore, the butterfly operation structure of the Fast Fourier Transform (FFT) algorithm is extracted according to the frequency domain, the input signal sequence is processed, the calculation speed can be improved by utilizing the characteristics of the FFT algorithm, and the consumption of hardware memory resources is reduced.
Specifically, taking the input signal sequence as { x (N) }, where N is 0, 1,.. and N-1 as an example, the intermediate result signal sequence obtained by calculation according to the butterfly operation structure of the FFT algorithm of frequency domain extraction may be { x (i) }, i is 0, 1,. and N-1, where N is the number of sampling points of the input signal.
S120: and reordering elements of the intermediate result signal sequence according to the discrete Fourier transform type.
Optionally, the discrete fourier transform type includes: a discrete fourier forward transform DFT and an inverse discrete fourier transform IDFT.
Wherein, reordering elements may refer to reordering elements in the intermediate result signal sequence according to a sequence order required by the discrete fourier transform type. Exemplarily, taking the number of sampling points of the input signal as 8 points as an example, as can be seen from the schematic diagram of the butterfly operation structure of the radix-2 FFT algorithm extracted according to the frequency domain shown in fig. 1c, the arrangement order of elements in the intermediate result signal sequence obtained after the butterfly operation structure processing of the FFT algorithm is 0, 4, 2, 6, 1, 5, 3, and 7, which does not conform to the arrangement order of elements of the DFT type or the IDFT type, and therefore, the intermediate result signal sequence needs to be subjected to element reordering to meet the requirement of the discrete fourier transform type.
Optionally, reordering the elements of the intermediate result signal sequence according to the discrete fourier transform type includes: determining a numerical value bit reversal sequence number according to the sequence number sequence of the elements in the intermediate result signal sequence; determining a reordered sequence number sequence according to the numerical bit reversal sequence number sequence and the discrete Fourier transform type; and reordering the elements of the intermediate result signal sequence according to the reordered sequence number sequence. The numerical value bit reversal sequence number may refer to a sequence number obtained by performing bit reversal on element sequence numbers in the intermediate result signal sequence according to the sequence number sequence.
In an optional implementation manner of the embodiment of the present invention, determining the numerical bit flipping sequence number sequence according to the sequence number sequence of the element in the intermediate result signal sequence includes: binary conversion is carried out on the serial number of each element in the intermediate result signal sequence to obtain a binary value; the bit of the binary numerical value is inverted in high and low positions to obtain an inverted binary numerical value; and converting the inverted binary value into a binary system with the same element serial number as the element serial number in the intermediate result signal sequence to obtain a numerical value bit inversion serial number sequence.
Specifically, the sequence number sequence required for outputting the result is { idx (i) ·, i ═ 0, 1.,. N-1}, where N is the number of sampling points of the input signal, the intermediate result signal sequence is { x (i) ·, i ═ 0, 1.,. N-1}, and the sequence number sequence of elements of the intermediate result signal sequence is a decimal sequence L ═ L, L ═ 0, 1.,. N-1}, and the sequence number sequence of numerical bit flipping is { L ═ Lcvt(l) For example, l is 0, 1,., N-1} and the calculation process may be as follows: first, each element L of L is converted into log2N bit binary number L ', turning the bit of L' to obtain L ', and converting the binary number L' back to decimal system to obtain sequence number Lcvt(l) In that respect For example, when L is 10 and N is 512, the calculation process is L' 000001010, L ″ -010100000, and L ═ 010100000cvt(10) When N is 512, if the serial number of an element in the intermediate result signal sequence is 10, the corresponding serial number is 160 after the numeric bit is inverted.
Therefore, the conversion from the natural sequence of the sequence numbers to the reverse sequence of the sequence numbers can be realized by carrying out numerical value bit inversion on the sequence numbers of all elements in the intermediate result signal sequence so as to determine the numerical value bit inversion sequence number.
In another optional implementation manner of the embodiment of the present invention, determining a reordered sequence number sequence according to a numerical bit flipping sequence number sequence and a discrete fourier transform type includes: when the discrete Fourier transform type is DFT, the numerical value bit reversal sequence number is used as a reordered sequence number; when the discrete fourier transform type is IDFT, a reordered sequence number is determined based on the numerical bit flip sequence number and a conversion relationship between DFT and IDFT. Wherein the conversion relationship between DFT and IDFT can utilize properties
Analyzing DFT result Y of the same sequence Y (n)DFT(k) And IDFT result YIDFT(l) And obtaining, wherein k is the frequency, and l is the serial number of the input signal, and the specific process is as follows:
replacing the variable mod (N-l, N) with l' to obtain:
finally, it can be found that: DFT result Y of the same sequence Y (n)DFT(k) And IDFT result YIDFT(l) Has the advantages of
The important relationship of (a).
Optionally, determining a reordered sequence number based on the numerical bit flipping sequence number and the transition relationship between DFT and IDFT includes: determining a reordered sequence number sequence based on the following equation: idx (i) ═ mod (N-L)cvt(i) N), i ═ 0, 1., N-1, where idx (i) is the reordered sequence number sequence corresponding to IDFT, Lcvt(i) And turning the serial number sequence for the numerical value bit corresponding to the DFT, wherein N is the number of sampling points of the input signal, and i is the serial number of the input signal sequence.
Specifically, the numerical bit flip sequence number is { L }cvt (L), L0, 1,.., N-1, and the reordered sequence number is { idx (i), i 0, 1.., N-1, for example, when the discrete fourier transform type is DFT, idx (i) ═ Lcvt(i) I-0, 1, ·, N-1; when the discrete fourier transform type is IDFT, idx (i) ═ mod (N-L)cvt(i) N), i ═ 0, 1., N-1, where N is the number of sampling points of the input signal.
S130: and performing numerical correction on the reordered intermediate result signal sequence according to the discrete Fourier transform type to obtain a final output signal.
The numerical modification may refer to modifying the reordered intermediate result signal sequence according to a discrete fourier transform type, so that the output signal satisfies the corresponding discrete fourier transform type.
As previously mentioned, the formulas for DFT and IDFT may be as follows:
wherein X (k) is the DFT conversion result of the input signal, x (N) is the IDFT conversion result of the input signal, N is the number of sampling points of the input signal, N is the serial number of the input signal, k is the frequency number of the frequency, i.e. the k-th frequency, W is the rotation factor,
as can be seen from the above, the DFT and IDFT have different requirements on coefficients, and therefore, the reordered intermediate result signal sequence needs to be further processed according to the discrete fourier transform type to obtain an output signal conforming to the discrete fourier transform type.
In an optional implementation manner of the embodiment of the present invention, performing numerical correction on the reordered intermediate result signal sequence according to a discrete fourier transform type to obtain a final output signal includes: when the discrete Fourier transform type is DFT, transparently transmitting the reordered intermediate result signal sequence, and outputting a DFT result; and when the discrete Fourier transform type is IDFT, dividing the reordered intermediate result signal sequence by N, and outputting an IDFT result, wherein N is the number of sampling points of the input signal sequence. The transparent transmission can directly output the reordered intermediate result signal sequence without changing the reordered intermediate result signal sequence.
According to the technical scheme of the embodiment of the invention, the butterfly operation structure of the FFT algorithm is extracted according to the frequency domain, the input signal is processed to obtain the intermediate result signal sequence, and the intermediate result signal sequence is subjected to element reordering and numerical correction according to the discrete Fourier transform type to obtain the final output signal.
Fig. 2a is a flowchart of a preferred signal processing method according to an embodiment of the present invention, and fig. 2b is a schematic diagram of a signal processing flow according to an embodiment of the present invention.
As shown in fig. 2a, a preferred signal processing method provided in the embodiment of the present invention includes the following specific steps:
s210: the method comprises the steps of obtaining an input signal sequence, extracting a butterfly operation structure of a Fast Fourier Transform (FFT) algorithm according to a frequency domain, and processing the input signal sequence through the butterfly operation structure to obtain an intermediate result signal sequence.
The input signal sequence is { x (N), N ═ 0, 1,. and N-1}, and the intermediate result signal sequence is { x (i), i ═ 0, 1,. and N-1 }.
S220: the log is obtained by binary conversion of each element L of the sequence of decimal sequence numbers L ═ { L, L ═ 0, 12N bits of binary number l'.
S230: l 'is obtained by inverting the bit of l' to be high-low.
S240: obtaining a sequence L of numerical bit reversal sequences by converting the binary number L' back to decimalcvt(l)。
S250: when the discrete Fourier transform type is DFT, determining the reordered sequence number as Idx (i) Lcvt(i) I-0, 1, ·, N-1; when the discrete fourier transform type is IDFT, the reordered sequence number sequence is determined to be idx (i) -mod (N-L)cvt(i)，N)，i＝0，1，...，N-1。
S260: the value of each element X (i) of sequence number i 0, 1.., N-1 is overlaid in turn to X (idx (i)) according to the reordered sequence of sequence numbers.
S270: performing numerical correction on the reordered intermediate result signal sequence according to the discrete Fourier transform type, and when the discrete Fourier transform type is DFT, performing transparent transmission on the reordered intermediate result signal sequence and outputting a DFT result; and when the discrete Fourier transform type is IDFT, dividing the reordered intermediate result signal sequence by N, and outputting an IDFT result, wherein N is the number of sampling points of the input signal sequence.
The technical scheme of the embodiment of the invention utilizes the butterfly operation structure of the FFT algorithm extracted according to the frequency domain, determines the reordered sequence number sequence according to the calculated numerical value bit reversal sequence number sequence and the discrete Fourier transform type, reorders elements of the intermediate result signal sequence according to the reordered sequence number sequence, and finally performs numerical value correction on the obtained signal sequence according to different discrete Fourier transform types to obtain the final output signal.
Fig. 3 is a schematic structural diagram of a signal processing apparatus according to an embodiment of the present invention, which can execute the signal processing methods in the foregoing embodiments. The apparatus may be implemented in software and/or hardware, and as shown in fig. 3, the signal processing apparatus specifically includes: a frequency domain extraction butterfly module 310, an element reordering module 320, and a value modification module 330.
The frequency domain extraction butterfly operation module 310 is configured to acquire an input signal sequence, extract a butterfly operation structure of a Fast Fourier Transform (FFT) algorithm according to a frequency domain, and process the input signal sequence through the butterfly operation structure to obtain an intermediate result signal sequence;
an element reordering module 320, configured to reorder elements of the intermediate result signal sequence according to the discrete fourier transform type;
and the numerical value correction module 330 is configured to perform numerical value correction on the reordered intermediate result signal sequence according to the discrete fourier transform type to obtain a final output signal.
According to the technical scheme of the embodiment of the invention, the butterfly operation structure of the FFT algorithm is extracted according to the frequency domain, the input signal is processed to obtain the intermediate result signal sequence, and the intermediate result signal sequence is subjected to element reordering and numerical correction according to the discrete Fourier transform type to obtain the final output signal.
Optionally, the element reordering module 320 may include an element reordering sub-module, configured to determine a numerical bit flipping sequence number sequence according to a sequence number sequence of an element in the intermediate result signal sequence; determining a reordered sequence number sequence according to the numerical bit reversal sequence number sequence and the discrete Fourier transform type; and reordering the elements of the intermediate result signal sequence according to the reordered sequence number sequence.
Optionally, the element reordering sub-module may include a numerical bit flipping unit, configured to perform binary conversion on a sequence number of each element in the intermediate result signal sequence to obtain a binary value; the bit of the binary numerical value is inverted in high and low positions to obtain an inverted binary numerical value; and converting the inverted binary value into a binary system with the same element serial number as the element serial number in the intermediate result signal sequence to obtain a numerical value bit inversion serial number sequence.
Optionally, the discrete fourier transform type includes: a discrete fourier forward transform DFT and an inverse discrete fourier transform IDFT.
Optionally, the element reordering sub-module may further include a sequence number sequence determining unit, configured to use the numerical bit reversal sequence number sequence as a reordered sequence number sequence when the discrete fourier transform type is DFT; when the discrete fourier transform type is IDFT, a reordered sequence number is determined based on the numerical bit flip sequence number and a conversion relationship between DFT and IDFT.
Optionally, the sequence number sequence determining unit may be specifically configured to determine the reordered sequence number sequence based on the following formula: idx (i) ═ mod (N-L)cvt(i) N), i ═ 0, 1., N-1, where idx (i) is the reordered sequence number sequence corresponding to IDFT, Lcvt(i) And turning the serial number sequence for the numerical value bit corresponding to the DFT, wherein N is the number of sampling points of the input signal, and i is the serial number of the input signal sequence.
Optionally, the value correcting module 330 may include a DFT value correcting unit and an IDFT value correcting unit;
the DFT numerical value correcting unit is used for transmitting the reordered intermediate result signal sequence and outputting a DFT result when the discrete Fourier transform type is DFT;
and the IDFT numerical value correcting unit is used for dividing the reordered intermediate result signal sequence by N and outputting an IDFT result when the discrete Fourier transform type is IDFT, wherein N is the number of sampling points of the input signal sequence.
The signal processing device provided by the embodiment of the invention can execute the signal processing method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, as shown in fig. 4, the electronic device includes a processor 410, a memory 420, an input device 430, and an output device 440; the number of the processors 410 in the electronic device may be one or more, and one processor 410 is taken as an example in fig. 4; the processor 410, the memory 420, the input device 430 and the output device 440 in the electronic apparatus may be connected by a bus or other means, and the bus connection is exemplified in fig. 4.
The memory 420 serves as a computer-readable storage medium for storing software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the signal processing method in the embodiment of the present invention (for example, the frequency domain decimation butterfly module 310, the element reordering module 320, and the value modification module 330 in the signal processing apparatus). The processor 410 executes various functional applications of the electronic device and data processing by executing software programs, instructions, and modules stored in the memory 420, that is, implements the signal processing method described above.
The signal processing method comprises the following steps:
acquiring an input signal sequence, extracting a butterfly operation structure of a Fast Fourier Transform (FFT) algorithm according to a frequency domain, and processing the input signal sequence through the butterfly operation structure to obtain an intermediate result signal sequence;
reordering elements of the intermediate result signal sequence according to the discrete Fourier transform type;
and performing numerical correction on the reordered intermediate result signal sequence according to the discrete Fourier transform type to obtain a final output signal.
The memory 420 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 420 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, memory 420 may further include memory located remotely from processor 410, which may be connected to an electronic device over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 430 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the electronic apparatus. The output device 440 may include a display device such as a display screen.
Embodiments of the present invention also provide a storage medium containing computer-executable instructions, which when executed by a computer processor, perform a method of signal processing, the method comprising:
acquiring an input signal sequence, extracting a butterfly operation structure of a Fast Fourier Transform (FFT) algorithm according to a frequency domain, and processing the input signal sequence through the butterfly operation structure to obtain an intermediate result signal sequence;
reordering elements of the intermediate result signal sequence according to the discrete Fourier transform type;
and performing numerical correction on the reordered intermediate result signal sequence according to the discrete Fourier transform type to obtain a final output signal.
Of course, the storage medium provided by the embodiment of the present invention contains computer-executable instructions, and the computer-executable instructions are not limited to the method operations described above, and may also perform related operations in the signal processing method provided by any embodiment of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods according to the embodiments of the present invention.
It should be noted that, in the embodiment of the signal processing apparatus, the included units and modules are merely divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A signal processing method, comprising:
acquiring an input signal sequence, extracting a butterfly operation structure of a Fast Fourier Transform (FFT) algorithm according to a frequency domain, and processing the input signal sequence through the butterfly operation structure to obtain an intermediate result signal sequence;
reordering elements of the intermediate result signal sequence according to the discrete Fourier transform type;
and performing numerical correction on the reordered intermediate result signal sequence according to the discrete Fourier transform type to obtain a final output signal.
2. The method of claim 1, wherein reordering the elements of the intermediate result signal sequence according to the discrete fourier transform type comprises:
determining a numerical value bit reversal sequence number according to the sequence number sequence of the elements in the intermediate result signal sequence;
determining a reordered sequence number sequence according to the numerical bit reversal sequence number sequence and the discrete Fourier transform type;
and reordering the elements of the intermediate result signal sequence according to the reordered sequence number sequence.
3. The method of claim 2, wherein determining the sequence of numerical bit flip sequence numbers based on the sequence of sequence numbers of elements in the sequence of intermediate result signals comprises:
binary conversion is carried out on the serial number of each element in the intermediate result signal sequence to obtain a binary value;
the bit of the binary numerical value is inverted in high and low positions to obtain an inverted binary numerical value;
and converting the inverted binary value into a binary system with the same element serial number as the element serial number in the intermediate result signal sequence to obtain a numerical value bit inversion serial number sequence.
4. The method of claim 2, wherein the discrete fourier transform type comprises: a discrete fourier forward transform DFT and an inverse discrete fourier transform IDFT.
5. The method of claim 4, wherein determining the reordered sequence of sequence numbers from the sequence of numerical bit flips sequence numbers and the type of discrete Fourier transform comprises:
when the discrete Fourier transform type is DFT, the numerical value bit reversal sequence number is used as a reordered sequence number;
when the discrete fourier transform type is IDFT, a reordered sequence number is determined based on the numerical bit flip sequence number and a conversion relationship between DFT and IDFT.
6. The method of claim 5, wherein determining the reordered sequence of sequence numbers based on the sequence of numerical bit flip sequence numbers and the transition relationship between the DFT and the IDFT comprises:
determining a reordered sequence number sequence based on the following equation:
Idx(i)＝mod(N-Lcvt(i)，N)，i＝0，1，...，N-1；
wherein Idx (i) is the reordered sequence number corresponding to IDFT, Lcvt(i) And turning the serial number sequence for the numerical value bit corresponding to the DFT, wherein N is the number of sampling points of the input signal, and i is the serial number of the input signal sequence.
7. The method of claim 1, wherein numerically modifying the reordered intermediate result signal sequence according to a discrete fourier transform type to obtain a final output signal comprises:
when the discrete Fourier transform type is DFT, transparently transmitting the reordered intermediate result signal sequence, and outputting a DFT result;
and when the discrete Fourier transform type is IDFT, dividing the reordered intermediate result signal sequence by N, and outputting an IDFT result, wherein N is the number of sampling points of the input signal sequence.
8. A signal processing apparatus, characterized by comprising:
the frequency domain extraction butterfly operation module is used for acquiring an input signal sequence, extracting a butterfly operation structure of a Fast Fourier Transform (FFT) algorithm according to a frequency domain, and processing the input signal sequence through the butterfly operation structure to obtain an intermediate result signal sequence;
the element reordering module is used for reordering the elements of the intermediate result signal sequence according to the discrete Fourier transform type;
and the numerical value correction module is used for performing numerical value correction on the reordered intermediate result signal sequence according to the discrete Fourier transform type to obtain a final output signal.
9. An electronic device, comprising:
one or more processors;
a storage device for storing one or more programs,
when executed by the one or more processors, cause the one or more processors to implement the method of any one of claims 1-7.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1 to 7.
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| CN117235420B (en) * | 2023-11-15 | 2024-02-09 | 北京智芯微电子科技有限公司 | Signal processing circuit, method, processor, storage medium and chip |
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