KR100892292B1 - Parallel and Pipelined Radix - 2 to the Fourth Power FFT Processor - Google Patents

Abstract

The present invention relates to a Radix 2 quadratic fast Fourier transform processor using a parallel structure and a pipelined method, by using a structure of two parallel data paths and a single-path delay feedback (SDF) structure. The complexity of the hardware has been reduced to facilitate configuration while increasing operating speed and data throughput. To this end, the present invention applies the Radix-2 ⁴ algorithm to the fast Fourier transform, and by designating a multiplication amount corresponding to half of the programmable complex multiplier as a special complex constant multiplier using the CSD method, it is possible to reduce hardware cost and power consumption The Radix 2 quadratic fast Fourier transform processor is implemented using a parallel architecture and pipeline method. The technical configuration includes a fast Fourier transform processor comprising: a plurality of Radix-2 ⁴ first butterfly calculators for performing butterfly operations when an input signal is applied; And the ^Radix-24 but connected to the first butterfly operation unit of the next stage, the first Radix- ²⁴ butterfly plurality of Radix in the output data outputted from the operation unit for performing the butterfly operation - ²⁴ second butterfly operation unit It consists of, including the Radix-2 ⁴ FFT algorithm is characterized.

FFT, IFFT, Radix-2 power of 4, SDF, MB-OFDM, UWB

Description

Parallel and Pipelined Radix-2 to the Fourth Power FFT Processor}

1 is a schematic signal flow diagram of a 128 point Radix-2 ⁴ SDF FFT algorithm in accordance with the present invention;

2 is a block diagram schematically illustrating a Radix-2 ⁴ fast Fourier transform structure according to the present invention.

3 is a schematic configuration diagram of a Radix-2 ⁴ butterfly calculation unit according to the present invention.

4A is a block diagram illustrating a CSD complex constant multiplier for sin (π / 8) in accordance with the present invention.

4B is a block diagram illustrating a CSD complex constant multiplier for cos (π / 8) in accordance with the present invention.

4C is a block diagram illustrating a CSD complex constant multiplier for sin (π / 4) = cos (π / 4) in accordance with the present invention.

5 is a block diagram schematically illustrating a CSD complex constant multiplier according to the present invention.

6 is a graph showing the noise rate according to the internal word length of the FFT processor according to the present invention.

The present invention relates to a Radix 2 quadratic fast Fourier transform processor using a parallel architecture and a pipelined scheme, and more particularly, by using a structure of two parallel data paths and a single path delay feedback structure. At the same time, the complexity of the hardware is reduced to facilitate configuration. To this end, the present invention applies the Radix-2 ⁴ algorithm to the fast Fourier transform, thereby designing a multiplication amount corresponding to half of the programmable complex multiplier as a special complex constant multiplier using the CSD method, which can reduce hardware cost and power consumption. Radix 2 quadratic fast Fourier transform processor is implemented using parallel architecture and pipeline.

In general, orthogonal frequency division multiplexing (OFDM) and discrete multi-tone (DMT) are advantageous for high-speed data transmission over a multipath channel.

These methods convert the modulated data by the number of subcarriers in parallel / parallel and the corresponding subcarriers, which are implemented using a Discrete Fourier Transform (DFT). Fast Fourier Transform (FFT) algorithm is used to reduce the amount of computation.

Here, the processor for processing the FFT algorithm has the largest complexity in the OFDM system and requires a high speed operation. The FFT design of modem applications requiring high performance mainly uses a processor having a pipeline structure. The pipeline structure not only reduces hardware cost by providing one operation unit for each stage, but also achieves the effect of high-speed operation even at a low operating frequency. have.

However, as the number of required FFT points increases, the hardware cost increases logarithmically, especially complex multipliers consume 50% to 80% of the total power, increase hardware complexity, and reduce data throughput. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and by using a structure of two parallel data paths, a single path delay feedback structure and a pipelined method, it is possible to increase the operating speed and data throughput and to make the configuration hard. Implemented to reduce the complexity of the software. By applying the Radix-2 ⁴ algorithm to the fast Fourier transform, parallel structures and pipes can be used to reduce the hardware cost and power consumption by designing the multiplication amount of half of the programmable complex multiplier as a special complex constant multiplier using CSD. It is an object of the present invention to provide a Radix 2 quadratic fast Fourier transform processor using a line method.

In order to achieve the above object, the present invention provides a fast Fourier transform processor comprising: a plurality of Radix-2 ⁴ first butterfly calculating units for performing a butterfly operation when an input signal is applied; And the ^Radix-24 but connected to the first butterfly operation unit of the next stage, the first Radix- ²⁴ butterfly plurality of Radix in the output data outputted from the operation unit for performing the butterfly operation - ²⁴ second butterfly operation unit It consists of, including the Radix-2 ⁴ FFT algorithm is characterized.

Here, half of the total multipliers are designed with special complex constant multipliers.

The special complex constant multiplier is a CSD complex constant multiplier.

In addition, the fast Fourier transform processor is a pipelined FFT processor having two parallel data paths to which the algorithm is applied.

In addition, the fast Fourier transform processor is characterized in that the SDF FFT processor applying the algorithm.

On the other hand, the algorithm is characterized in that it is derived by the index decomposition method.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic signal flow diagram of a 128 point Radix-2 ⁴ SDF FFT algorithm according to the present invention. As shown in the figure, the development of Radix-2 ⁴ is briefly described.

Discrete Fourier Transform (DFT) having length N is defined as in Equation 1.

Here, W ^k _n denotes a rotation factor, k denotes a frequency index, and n denotes a time index. In order to derive the Radix-2 ⁴ algorithm according to the present invention, a 5-dimensional linear index map is applied to Equation 2.

In this case, when the common factor decomposition algorithm (CFA) is applied, Equation 3 is obtained.

When the rotation factor of Equation 3 is calculated, Equation 4 is obtained.

The structure of the fourth butterfly calculation unit is shown in Equation 5, and represents a rotation factor having four complex numbers.

In addition, the structure of the second butterfly calculation unit is represented by H (n), and is represented by Equation 6.

Where H (n) = H (n, k1, k2). As shown in Equation 5, the fourth butterfly operator has a form in which the second butterfly operator H (n) is connected to each other by the rotation factor Wn16.

The first butterfly calculation unit is expressed by Equation (7).

Finally, the algorithm according to the present invention uses a complex constant multiplier in place of the programmable complex multiplier, and the CSD constant multiplier reduces the area and power consumption of the hardware by simplifying the computation process to minimize the number of ones.

2 is a block diagram schematically illustrating a Radix-2 ⁴ fast Fourier transform structure according to the present invention. As shown in the figure, a 128-point Radix-2 ⁴ SDF FFT processor with two parallel data paths consists of a butterfly operator, a complex Booth multiplier, a CSD complex constant multiplier, a register and a memory block.

Here, the complex booth multiplier is reduced by using the CSD complex constant multiplier, thereby reducing the hardware complexity.

Since this structure is two parallel data structures, two complex values are entered differently from the general data flow. Therefore, after storing two complex numbers sequentially, if the 64th data is stored after half of the 128 points, the 65th data is transferred. The first (odd) value stored in S is calculated with the new input value, and the even value entered together is stored in the previous odd memory. After all the odd values are calculated by this operation, only the even pairs are calculated and two complex numbers are sequentially stored in the empty memory.

As the result of the first butterfly operation, the operation on the odd numbered input is performed first, so the N point of N / 2 ram area required for the butterfly operation is reduced except for the first and last stages, but the butterfly operation of the last stage is performed. Saves all the values during the start of even-numbered operations after completing the operation on odd-numbered inputs, thus increasing the RAM area compared to the general structure. However, additional RAM by two parallel data structures is not needed.

3 is a schematic configuration diagram of a Radix-2 ⁴ butterfly calculation unit according to the present invention. As shown in the figure, two calculation processes are performed.

In the first operation, real numbers and imaginary numbers are stored in RAM, and the values previously stored in RAM are output to the output.

In the second operation, the butterfly operator (BF1) inputs the real and imaginary numbers stored in the RAM and the new input real and imaginary numbers into the complex subtractor and the complex adder, respectively, and operates from the complex subtractor. The output data calculated by the complex adder is output for the next operation. These two operations are repeated sequentially.

On the other hand, the butterfly calculating unit BF2 includes some combination circuits for performing the calculation of (-j).

Here, in order to implement an algorithm for driving a Radix-2 ⁴ FFT having two parallel data paths according to the present invention, two complex Booth multipliers are provided.

The result data generated from the butterfly operation unit BF1 of the sixth stage is multiplied by the rotation factors, -j, W (16), and W (48), and the ROM stores 32 bytes of the rotation factor data. .

Also, half of the complex multipliers are designed with CSD complex constant multipliers.

Table 1 shows the rotation factors in decimal, 8-bit binary, and CSD formats.

Here, the complex multiplication coefficients corresponding to the rotation factors are trigonometric functions sin (π / 4) = cos (π / 4), cos (π / 8), sin (π / 8), and the rotation factors W (8), It may be represented by W (16), W (24), and W (48).

The constant multiplier generates partial products by shifting the value bits of the input according to the positions of the bits other than '0' in the multiplying coefficients, and adding them together to obtain a result. If the coefficient is N bits, the number of partial products generated in the multiplier is N maximum, and since the portion occupying the area is added to the partial product, the partial product must be reduced to reduce the area.

Thus, when designing a multiplier, the method of reducing the area is to express multiplication coefficients expressed in two's complement by the CSD method, which has a digit set of {-1, 0, 1} and two or more consecutive '1's. Cannot have a bit of ' The converted CSD expression can reduce the number of '1's as compared to two's complement.

At this time, 1 bar represents -1.

4A is a block diagram showing a CSD complex constant multiplier for sin (π / 8) according to the present invention, and FIG. 4B is a block diagram showing a CSD complex constant multiplier for cos (π / 8) according to the present invention. 4C is a block diagram illustrating a CSD complex constant multiplier for sin (π / 4) = cos (π / 4) according to the present invention. As shown in the figure, for sin (π / 4) = cos (π / 4), cos (π / 8), sin (π / 8), sin (π / 8) is an error compensation bias. (C) and a half adder and a vector add adder, cos (π / 8) includes an error compensation bias (C1, C2), a full adder, a half adder and a vector add adder, and sin (π / 4) = cos (π / 4) includes an error compensation bias C, a full adder and a vector add adder.

In order to efficiently compensate the quantization error, the error compensation bias is composed of the main group and the sub group according to the effect on the quantization error, and is represented by the main group truncation bit, and the probability of the effect of the truncation bit is calculated. The total sum of the error compensation biases is defined as C, or C1, C2.

On the other hand, the output of a two-complement multiplier of a general NXN bit is a (2N-1) input, and if you want to obtain only N-bit output like the input, omit the (N-1) LSB from the result of the (2N-1) bit. In this case, the FFT processor can use the existing multiplier as it is by repeating the digital operation, but the quantization error is not only increased but also waste of hardware. Therefore, we fix the output bits to N from the beginning and implement the error compensation bias to get the result to have the smallest error when designing the CSD multiplier.

5 is a block diagram schematically illustrating a CSD complex constant multiplier according to the present invention. As shown in the figure, the CSD complex constant multiplier comprises six CSD complex constant multipliers and two comparators.

Here, the real data and the imaginary data are inputted to output the real data and the imaginary data as result data of the six CSD complex constant multipliers.

Table 2 shows the rotation factor calculation scheduling of each data path. As shown in FIG. 5, six CSD complex constant multipliers having three types are shared to sequentially perform rotational natural acids according to the present invention.

In the embodiment of the present invention, a 128-point Radix 2 quadratic fast Fourier transform processor is implemented in hardware using a parallel structure and a pipeline method according to the present invention.

6 is a graph illustrating the noise rate according to the internal word length of the FFT processor according to the present invention. As shown in the figure, fixed-point simulation is performed prior to hardware implementation to determine the appropriate word length.

Here, the input noise ratio (IN SNR) is the ratio of AWGN (Additive White Gaussian Noise) by the channel according to the signal input to the FFT, and the output noise ratio (OUT SNR) is due to AWGN and quantization noise due to fixed-point arithmetic. Input signal ratio.

At this time, as shown in the drawing, if the length of the word is increased while the input noise rate is fixed, the quantization noise decreases and the output noise rate increases, and as the output noise rate approaches the input noise rate, it converges. This is negligible in quantization noise.

Although the exemplary embodiments of the present invention have been described above by way of example, the scope of the present invention is not limited to such specific embodiments, and a person of ordinary skill in the art may be provided within the scope of the claims of the present invention. Appropriate changes can be made.

As described above, the present invention having the configuration described above uses a structure of two parallel data paths and a single path delay feedback structure to increase the operation speed and data throughput and to reduce the complexity of hardware to facilitate the configuration. By applying the Radix-2 ⁴ algorithm to the fast Fourier transform, we can reduce the hardware cost and power consumption by designing the multiplication amount of half of the programmable complex multiplier with a special complex constant multiplier using CSD. This can be effective.

Claims (6)

In a pipeline fast Fourier transform processor with two parallel data paths applying the Radix-2 ⁴ algorithm, A plurality of Radix-2 ⁴ first butterfly calculators for outputting two parallel outputs after performing a butterfly operation capable of efficient data processing and memory operation when input signals of two parallel data paths are applied; And The ^Radix-24 first being connected to the next stage of the butterfly operation unit, said first plurality of Radix Butterfly Radix- ²⁴ for performing butterfly operation on the output data outputted from the computing unit fly-2 butterfly operation unit ^42, and It includes six CSD complex constant multipliers of three types, Radix 2 quadratic fast Fourier transform processor of 128 points using a parallel structure and a pipelined method characterized in that to perform the rotational natural acid in the two parallel paths by sequentially sharing the six CSD complex constant multiplier. delete delete delete The method of claim 1, And a quadratic fast Fourier transform processor of 128-point Radix 2 using a parallel structure and a pipelined method, wherein an SDF algorithm is applied to the two parallel structures of the fast Fourier transform processor. The method of claim 1, And the algorithm is derived by index decomposition. A 128-point Radix 2 quadratic fast Fourier transform processor using a parallel structure and a pipeline method.

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