CN112234953A - Edge modulation transmitter and digital isolator - Google Patents

Edge modulation transmitter and digital isolator Download PDF

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CN112234953A
CN112234953A CN202011228087.XA CN202011228087A CN112234953A CN 112234953 A CN112234953 A CN 112234953A CN 202011228087 A CN202011228087 A CN 202011228087A CN 112234953 A CN112234953 A CN 112234953A
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edge
signal
input
module
input signal
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李立松
方向明
伍荣翔
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Shenzhen Line Easy Microelectronics Co ltd
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Chongqing Xianyi Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/013—Modifications of generator to prevent operation by noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback

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Abstract

The application provides an edge modulation transmitter and a digital isolator, and relates to the technical field of digital circuits. The input signal of the edge modulation transmitter is a digital signal, and rising edges and falling edges alternately appear; the edge modulator transmitter includes a detection module; the edge modulator outputs a first number of pulses at a specified edge moment of the input signal when the detection module detects that a time interval between two adjacent edges of the input signal is smaller than a preset time length; the edge modulator outputs a second number of pulses at the specified edge time of the input signal when the detection module detects that the time interval between two adjacent edges of the input signal is greater than or equal to the preset time length, wherein the second number is greater than the first number. When the transmitter detects that common mode noise occurs in the system, adaptive edge modulation is carried out based on the data rate of the input signal, and the accuracy of signal output is guaranteed.

Description

Edge modulation transmitter and digital isolator
Technical Field
The present application relates to the field of digital circuit technology, and more particularly, to an edge modulation transmitter and a digital isolator.
Background
As the digital isolator is mainly used for transmitting digital signals between circuit modules with high voltage difference, the working environment thereof has more noise interference, especially Common Mode noise (CMT), which poses a significant threat to the transmission reliability of the digital isolator signals. The existing pulse-based edge coding and decoding technology can realize a small CMT interference resistance range, cannot perform targeted and different-mode modulation on an input signal according to the data rate of the input signal, and has the problem of poor digital signal modulation accuracy.
Disclosure of Invention
In view of the above, an object of the present invention is to provide an edge modulation transmitter and a digital isolator, so as to solve the problem that the prior art cannot perform targeted modulation on an input signal in different modes according to the data rate of the input signal, and has poor accuracy of digital signal modulation.
The embodiment of the application provides an edge modulation transmitter, wherein an input signal of the edge modulation transmitter is a digital signal, and rising edges and falling edges alternately appear;
the edge modulation transmitter includes a detection module;
the edge modulation transmitter outputs a first number of pulses at a specified edge moment of the input signal when the detection module detects that a time interval between two adjacent edges of the input signal is smaller than a preset time length;
and the edge modulation transmitter outputs a second number of pulses at the specified edge moment of the input signal when the detection module detects that the time interval between two adjacent edges of the input signal is greater than or equal to the preset time length, wherein the second number is greater than the first number.
In the implementation mode, the data rate detection of the input signal is realized through the detection module, and different adaptive edge modulation is carried out on the input signal under different data rates, so that the edge modulation of different data rates is more accurate, and the data transmission stability of the edge modulation transmitter is improved.
Optionally, the edge modulation transmitter further includes an edge modulation module, the detection module includes an edge trigger module and a counting module, the edge trigger module and the counting module are connected in parallel between an input end of the edge modulation module and a signal input end of the edge modulation transmitter, and an output end of the edge trigger module is connected to a reset end of the counting module;
the edge trigger module outputs a first pulse signal when the period of the input signal is longer than a preset time length, the first pulse signal is a reset signal of the counting module, the counting module outputs a signal indicating that the time interval between two adjacent edges of the input signal detected by the detection module is less than the preset time length based on the first pulse signal, the edge modulation module is used for enabling the driver to drive the input signal when the detection module detects that the time interval between two adjacent edges of the input signal is less than the preset time length, the first number of pulses are output at the appointed edge moment of the input signal, and the second number of pulses are output at the appointed edge moment of the input signal when the detection module detects that the time interval between two adjacent edges of the input signal is greater than or equal to the preset time length.
In the implementation manner, the data rate of the input signal is detected in real time through the edge trigger and the timer, and is represented through the first pulse signal, so that the counting module is cleared, and the data rate of the input signal is transmitted to the edge modulation module through the counting module.
Optionally, the edge trigger module includes an edge trigger and a timer, an input end of the edge trigger is connected to the signal input end, an output end of the edge trigger is connected to a reset end of the timer, and an output end of the timer is respectively connected to a reset end of the timer, a first input end of the edge modulation module, and a reset end of the counting module;
the edge trigger transmits a first reset signal to the timer when detecting the designated edge of the input signal so as to clear the timer, and outputs the first pulse signal through an output end of the timer when the timing of the timer reaches the preset duration.
In the implementation manner, the timer outputs the pulse signal when the period of the input signal is greater than the preset timing duration through the logic setting of the edge trigger and the timer, and does not output the pulse signal when the period of the input signal is less than or equal to the preset timing duration, so that the threshold detection is realized on the period of the input signal.
Optionally, the counting module is an asynchronous counter with an overflow protection function.
In the above implementation, the value of the counting module can be kept at a fixed value by the overflow protection function, so as to perform subsequent edge modulation based on the fixed value.
Optionally, the counting module includes a first D flip-flop, a second D flip-flop, a not gate, and a nor gate, a clock input end of the first D flip-flop is connected to the signal input end, a clear end of the first D flip-flop and a clear end of the second D flip-flop are both connected to an output end of the timer, and a D end, a Q end, and a Q end of the first D flip-flop are connected to an output end of the timer
Figure BDA0002763493510000031
The end of the first D flip-flop is connected with the input end of the NOR gate, the output end of the NOR gate is connected with the first input end of the NOR gate, the output end of the NOR gate is connected with the clock input end of the second D flip-flop, and the D end of the second D flip-flop is connected with the clock input end of the second flip-flop
Figure BDA0002763493510000032
And the second input end of the NOR gate and the Q end of the second D trigger are connected with the second input end of the edge modulation module.
In the implementation mode, the two-bit counting module is realized through the two D triggers, so that the cost is low and the element structure is simple.
Optionally, when the detection module detects that a time interval between two adjacent edges of the input signal is greater than or equal to the preset time length, the edge modulator outputs the second number of pulses at the specified edge time of the input signal, where an interval between the second number of pulses is a first interval.
In the implementation mode, the pulse interval is increased for the input signal with high data rate through the edge modulation module, so that the pulse signal which cannot be received by the receiver when the CMT event occurs is transmitted to the receiver after the CMT event occurs, and the data transmission stability is ensured.
The embodiment of the application provides that the digital isolator comprises the edge modulation transmitter, the driver and the receiver, wherein the receiver comprises a comparator circuit and a latch, the output end of the driver is connected with the input end of the comparator circuit, the output end of the comparator circuit is connected with the input end of the latch, and the output end of the latch is the output end of the digital isolator;
the comparator circuit compares the output signal of the driver, when the output signal of the driver is a pulse of a first polarity, the latch is set to a first logic latch state, the output end of the latch outputs a first logic, when the output signal of the driver is a pulse of a second polarity, the latch is set to a second logic latch state, and the output end of the latch outputs a second logic.
In the implementation mode, the logic latch state switching is carried out through the latch which can be triggered by a single pulse, and the CMT interference resistant stable output of the digital signal is realized.
Optionally, the driver is a six-terminal transformer formed by two mutually coupled coils.
In the above implementation, the driver converts and outputs the input signal, so as to reduce signal interference and transmission distortion.
Optionally, the receiver further comprises a resistor-capacitor circuit connected in series between the driver and the comparator.
In the implementation mode, the waveform of the output signal of the driver is adjusted through the resistor-capacitor circuit, and the output accuracy of the digital signal is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a digital isolator according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of an edge modulation transmitter according to an embodiment of the present disclosure.
Fig. 3 is a schematic structural diagram of a counting module according to an embodiment of the present disclosure.
Fig. 4 is a signal diagram illustrating an increase in the number of pulses of a low data rate input signal according to an embodiment of the present application.
Fig. 5 is a signal diagram illustrating an increase in pulse spacing of a high data rate input signal according to an embodiment of the present disclosure.
Fig. 6 is a schematic structural diagram of a driver according to an embodiment of the present application.
Icon: 10-a digital isolator; 11-edge modulated emitter; 111-a detection module; 1111-edge trigger module; 1112-a counting module; 112-edge modulation module; 12-a driver; 13-a receiver; 131-a comparator circuit; 132-a latch; 133-resistor-capacitor circuit.
Detailed Description
The technical solution in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
First, the digital isolator is introduced from a digital isolator, which is a chip that enables an electronic system to have a high voltage-resistant isolation characteristic when a digital signal and an analog signal are transmitted in the electronic system, so as to achieve isolation between the electronic systems, and the common mode noise has a large influence on the transmission reliability of the digital isolator signal, whereas the digital isolator in the prior art has a small CMT interference resistance range, cannot perform targeted edge modulation on input signals with different transmission rates, and cannot ensure the signal transmission quality in some environments, so the present embodiment provides a digital isolator 10 to solve the above problems.
The edge modulation transmitter 11 provided in the embodiment of the present application has an input signal that is a digital signal, and rising edges and falling edges alternately appear, the edge modulation transmitter 11 includes a detection module 111, the detection module 111 is configured to detect a size relationship between a time interval between two adjacent edges of the input signal and a preset time duration, so that the edge modulation transmitter 11 outputs a first number of pulses at a specified edge time of the input signal when the time interval between the two adjacent edges of the input signal is smaller than the preset time duration, and outputs a second number of pulses at the specified edge time of the input signal when the time interval between the two adjacent edges of the input signal is greater than or equal to the preset time duration.
Optionally, the second number is greater than the first number, and in this embodiment, the second number may be 2, and the first number may be 1. It should be understood that in other embodiments, any other number may be selected for the first number and the second number.
Alternatively, the above-mentioned specified edge may be an upper edge or a lower edge.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a digital isolator according to an embodiment of the present disclosure.
The digital isolator 10 includes an edge modulation transmitter 11, a driver 12, and a receiver 13, and the edge modulation transmitter 11 is electrically connected to the receiver 13 through the driver 12.
Referring to fig. 2, fig. 2 is a schematic structural diagram of an edge modulation transmitter according to an embodiment of the present disclosure.
The edge modulation transmitter 11 comprises a detection module 111 and an edge modulation module 112, the detection module 111 comprises an edge trigger module 1111 and a counting module 1112 which are connected in parallel between an input terminal of the edge modulation module 112 and a signal input terminal of the edge modulation transmitter 11, and an output terminal of the edge trigger module 1111 is connected with a reset terminal of the counting module 1112.
The edge triggering module 1111 outputs a first pulse signal when the period of the input signal at the signal input terminal is longer than a preset time, the first pulse signal is a reset signal of the counting module 1112, the counting module 1112 outputs a data rate determination signal indicating the input signal based on the first pulse signal, and the edge modulation module 112 is configured to perform adaptive edge modulation in different modes on the input signal when the data rate determination signal is different, and transmit the adaptive edge modulation to the receiver 13 through at least one multi-stage buffer and the driver 12.
Specifically, the edge triggered module 1111 includes an edge trigger T1 and a timer T2, an input terminal of the edge trigger T1 is connected to the signal input terminal, an output terminal of the edge trigger T1 is connected to a reset terminal of the timer T2, and an output terminal of the timer T2 is connected to a reset terminal of the timer T2, a first input terminal of the edge modulation module 112, and a reset terminal of the counting module 1112, respectively.
The output signal of the edge flip-flop T1 when the rising edge or the falling edge of the input signal is detected serves as a reset clear signal (first reset signal) of the timer T2, and the first reset signal is transmitted to the timer T2 to clear the timer T2, that is, each edge of the input signal clears the timing of the timer T2, and the timer T2 does not output the first pulse signal. When the count of the timer T2 reaches the pre-designed time length, the count of the timer T2 is not cleared, and the first pulse signal is output through its own output terminal.
Alternatively, the counting module 1112 in this embodiment is an asynchronous counter with overflow protection function, and the asynchronous counter may be implemented in many ways, for example, a 2-bit counter is formed by a D flip-flop.
One way to implement overflow protection is presented below, and other ways may be used by those skilled in the art to achieve similar functionality. The specific implementation method is not limiting to the application.
Specifically, please refer to fig. 3, and fig. 3 is a schematic structural diagram of a counting module according to an embodiment of the present disclosure.
The counting module 1112 comprises a first D flip-flop D1, a second D flip-flop D2, a not gate and a nor gate, a clock input end of the first D flip-flop D1 is connected with a signal input end D, a clear end CLR of the first D flip-flop D1 and a clear end CLR of the second D flip-flop D2 are both connected with an output end of a timer T2, and a D end, a Q end and a nor end of the first D flip-flop D1 are connected with each other
Figure BDA0002763493510000072
The input end of the end NAND gate is connected, the output end of the NOR gate is connected with the first input end of the NOR gate, the output end of the NOR gate is connected with the clock input end of the second D flip-flop D2, and the D end of the second D flip-flop D2 is connected with the clock input end of the second flip-flop
Figure BDA0002763493510000073
The second input terminal of the nor gate and the Q terminal of the second D flip-flop D2 are connected to the second input terminal of the edge modulation module 112. A first input terminal of the edge modulation module 112 is connected to an output terminal of the timer T2, and a third input terminal of the edge modulation module 112 is connected to a signal input terminal of the edge modulation transmitter 11.
For the first D flip-flop D1 and the second D flip-flop D2, when the second D flip-flop D2 of the second stage outputs the second logic through the D terminal, the first D flip-flop D1
Figure BDA0002763493510000071
The output may be transmitted directly to the second D flip-flop D2 of the second stage. When the second D flip-flop D2 of the second stage is turned to output the first logic through the D terminal, the clock input of the second D flip-flop D2 of the second stage is turned to the second logic, and the latch state is maintained. And the first pulse signal of the timer T2 may clear the D-side outputs of the first D-flip-flop D1 and the second D-flip-flop D2 at the same time.
The operation principle of the counting module 1112 is as follows: when the data rate of the input signal input by the signal input end of the edge modulation transmitter 11 is low, and the period of the input signal input by the signal input end of the edge modulation transmitter 11 is greater than the preset time duration of the timer T2, the timer T2 outputs a first pulse signal, the counting module 1112 is continuously cleared and cannot count up, and the most significant signal continues to be the second logic (the second logic may be selected from 1 and 0 according to specific requirements, and the second logic is taken as an example of 0 in this embodiment).
When the data rate of the input signal at the signal input end of the edge modulation transmitter 11 is high, when the period of the input signal at the signal input end of the edge modulation transmitter 11 is less than or equal to the preset time duration of the timer T2, the clock of the timer T2 is frequently cleared, the first pulse signal is not output, the counting module 1112 continues to count, and the most significant bit signal is the first logic (the first logic is 1 in this embodiment for example) due to the overflow protection mechanism.
Therefore, when the most significant signal of the counting module 1112 is of the second logic, the input signal inputted to the signal input terminal of the edge modulation transmitter 11 may be determined to be of the low data rate, and when the most significant signal of the counting module 1112 is of the first logic, the input signal inputted to the signal input terminal of the edge modulation transmitter 11 may be determined to be of the high data rate.
It should be understood that the preset time duration in this implementation can be flexibly adjusted according to the specific structure and requirements of the digital isolator 10.
In this embodiment, the edge modulation module 112 performs adaptive edge modulation on the input signal of the edge modulation transmitter 11 with a low data rate based on the data rate determination signal, and the specific steps may include:
(1) when the most significant bit signal is the first logic, the edge modulation module 112 outputs a first number of pulse signals for the first edge signal and a second number of pulse signals for the second edge signal.
(2) When the most significant bit signal is the second logic, the edge modulation module 112 outputs a third number of pulse signals for the first edge signal and a fourth number of pulse signals for the second edge signal;
(3) the third number is greater than the first number, the fourth number is greater than the second number, and the first edge signal and the second edge signal are complementary edge signals with rising edges or falling edges.
In this embodiment, the first signal edge is taken as a rising edge, the first number is 1, the second number is 1, the third number is 2, and the fourth number is 2 as an example, please refer to fig. 4, and fig. 4 is a signal diagram of increasing the number of pulses of the low data rate input signal according to the embodiment of the present application. The first output end waveform refers to a waveform output by the upper output end of the edge modulation module 112, the second output end waveform refers to a waveform output by the lower output end of the edge modulation module 112, the output waveform is a final output waveform of the digital isolator 10, and t1 is a preset timing duration.
The present embodiment has a technical advantage that, since a certain number of pulse signals are additionally transmitted at a low data rate by corresponding edges, even if the initial signal cannot be normally received due to interference, for example, a CMT event is damaged, the pulse signals additionally transmitted subsequently can still be received, thereby ensuring the accuracy of signal transmission.
In this embodiment, the edge modulation module 112 performs adaptive edge modulation on the input signal of the edge modulation transmitter 11 with a high data rate based on the data rate determination signal, and the specific steps may include:
(1) when the most significant bit signal is the first logic, the edge modulation module 112 outputs a fifth number of pulse signals with a first pulse interval for the first edge signal, and outputs a sixth number of pulse signals with a second pulse interval for the second edge signal;
(2) when the most significant bit signal is the second logic, the edge modulation module 112 outputs a fifth number of pulse signals with a third pulse interval for the first edge signal, and outputs a sixth number of pulse signals with a third pulse interval for the second edge signal;
(3) the third interval is larger than the first interval, the fourth interval is larger than the second interval, and the first edge signal and the second edge signal are complementary edge signals with rising edges or falling edges.
In the present embodiment, taking the first signal edge as the rising edge as an example, please refer to fig. 5, and fig. 5 is a signal diagram illustrating an increase of the pulse interval of the high data rate input signal according to the present embodiment. The first output end waveform refers to a waveform output by the upper output end of the edge modulation module 112, the second output end waveform refers to a waveform output by the lower output end of the edge modulation module 112, the output waveform is a final output waveform of the digital isolator 10, and t1 is a preset timing duration.
The technical advantage of this embodiment is that, because the pulse interval corresponding to the lower edge of the low data rate is large, it can tolerate longer interference, such as CMT event, and continue to transmit and receive signals after the CMT is finished, thereby ensuring the accuracy of signal transmission.
It should be understood that the present embodiment is not limited to the specific manner as long as the high-speed and low-speed signals have different pulse numbers or intervals according to the signal of the counting module 1112, so as to perform the adaptive edge modulation on the input signal.
Optionally, the drive buffer of driver 12 may also provide a feedback signal to edge modulation module 112, and different embodiments may depend on the logic design of edge modulation module 112 and its cooperation with the drive buffer feedback signal of driver 12.
Next, the driver 12 and the receiver 13 of the digital isolator 10 will be described in detail.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a driver according to an embodiment of the present application. Optionally, in this embodiment, the driver 12 is a six-terminal transformer formed by two mutually coupled coils, the first input terminal and the second input terminal of the driver 12 are respectively connected to the first output terminal and the second output terminal of the edge modulation module 112 through a multi-stage buffer, and the first output terminal and the second output terminal of the driver 12 are connected to the receiver 13.
Further, the driver 12 has a third output terminal connected to the receiver 13 between the first output terminal and the second output terminal, and a third access terminal connected to ground between the first input terminal and the second input terminal.
With continued reference to fig. 1, the receiver 13 includes a comparator circuit 131 and a latch 132, an output terminal of the driver 12 is connected to an input terminal of the comparator circuit 131, an output terminal of the comparator circuit 131 is connected to an input terminal of the latch 132, and an output terminal of the latch 132 is an output terminal of the digital isolator 10.
Optionally, the receiver 13 may further include a resistor-capacitor (RS) circuit 133 connected in series between the driver 12 and the comparator circuit 131 for adjusting the received waveform, and the specific adjustment method is not essential to the present invention and therefore will not be described in detail.
Specifically, the comparator circuit 131 includes a first comparator C1 and a second comparator C2, a positive phase input terminal of the first comparator C1 is connected to a negative phase input terminal of the second comparator C2 and a first output terminal of the resistor-capacitor circuit 133, respectively, and a negative phase input terminal of the first comparator C1 is connected to a positive phase input terminal of the second comparator C2 and a second output terminal of the resistor-capacitor circuit 133, respectively.
Latch 132 may be an R-S latch, an output terminal of fifth comparator C5 is connected to an S terminal of latch 132, an output terminal of sixth comparator C6 is connected to an R terminal of latch 132, and a Q terminal of latch 132 is a signal output terminal of digital isolator 10.
In summary, the embodiment of the present application provides an edge modulation transmitter and a digital isolator, where an input signal of the edge modulation transmitter is a digital signal, and rising edges and falling edges alternately appear; the edge modulation transmitter includes a detection module; the edge modulator outputs a first number of pulses at a specified edge moment of the input signal when the detection module detects that a time interval between two adjacent edges of the input signal is smaller than a preset time length; the edge modulator outputs a second number of pulses at the specified edge time of the input signal when the detection module detects that the time interval between two adjacent edges of the input signal is greater than or equal to the preset time length, wherein the second number is greater than the first number.
In the implementation mode, the data rate detection of the input signal is realized through the detection module, and different adaptive edge modulation is carried out on the input signal under different data rates, so that the edge modulation of different data rates is more accurate, and the data transmission stability of the edge modulation transmitter is improved.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. The apparatus embodiments described above are merely illustrative, and for example, the block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of devices according to various embodiments of the present application.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Claims (9)

1. An edge modulation transmitter is characterized in that an input signal of the edge modulation transmitter is a digital signal, and rising edges and falling edges alternately appear;
the edge modulation transmitter includes a detection module;
the edge modulation transmitter outputs a first number of pulses at a specified edge moment of the input signal when the detection module detects that a time interval between two adjacent edges of the input signal is smaller than a preset time length;
and the edge modulation transmitter outputs a second number of pulses at the specified edge moment of the input signal when the detection module detects that the time interval between two adjacent edges of the input signal is greater than or equal to the preset time length, wherein the second number is greater than the first number.
2. The edge modulation transmitter of claim 1 further comprising an edge modulation module, wherein the detection module comprises an edge trigger module and a counter module, wherein the edge trigger module and the counter module are connected in parallel between an input of the edge modulation module and a signal input of the edge modulation transmitter, and wherein an output of the edge trigger module is connected to a reset of the counter module;
the edge trigger module outputs a first pulse signal when the period of the input signal is longer than a preset time length, the first pulse signal is a reset signal of the counting module, the counting module outputs a signal indicating that the time interval between two adjacent edges of the input signal detected by the detection module is less than the preset time length based on the first pulse signal, the edge modulation module is used for enabling the driver to drive the input signal when the detection module detects that the time interval between two adjacent edges of the input signal is less than the preset time length, the first number of pulses are output at the appointed edge moment of the input signal, and the second number of pulses are output at the appointed edge moment of the input signal when the detection module detects that the time interval between two adjacent edges of the input signal is greater than or equal to the preset time length.
3. The edge modulation transmitter of claim 2 wherein the edge trigger module comprises an edge trigger and a timer, an input of the edge trigger is connected to the signal input, an output of the edge trigger is connected to a reset of the timer, and outputs of the timer are connected to a reset of the timer, a first input of the edge modulation module, and a reset of the count module, respectively;
the edge trigger transmits a first reset signal to the timer when detecting the designated edge of the input signal so as to clear the timer, and outputs the first pulse signal through an output end of the timer when the timing of the timer reaches the preset duration.
4. The edge modulation transmitter of claim 2 wherein the counting module is an asynchronous counter with overflow protection.
5. The edge modulation transmitter of claim 3 wherein the counting module comprises a first D flip-flop, a second D flip-flop, a NOR gate, and a NOR gate, wherein a clock input of the first D flip-flop is connected to the signal input, a clear terminal of the first D flip-flop and a clear terminal of the second D flip-flop are both connected to an output of the timer, and a D terminal, a Q terminal, and a NOR terminal of the first D flip-flop are connected to an output of the timer
Figure FDA0002763493500000021
The end of the first D flip-flop is connected with the input end of the NOR gate, the output end of the NOR gate is connected with the first input end of the NOR gate, the output end of the NOR gate is connected with the clock input end of the second D flip-flop, and the D end of the second D flip-flop is connected with the clock input end of the second D flip-flop
Figure FDA0002763493500000022
And the second input end of the NOR gate and the Q end of the second D trigger are connected with the second input end of the edge modulation module.
6. The edge modulation transmitter of claim 1, wherein the edge modulation transmitter outputs the second number of pulses at the specified edge time of the input signal when the detection module detects that a time interval between two adjacent edges of the input signal is greater than or equal to the preset time duration, and a distance between the second number of pulses is a first distance.
7. A digital isolator comprising an edge modulated transmitter according to any one of claims 2 to 6, a driver and a receiver, the receiver comprising a comparator circuit and a latch, an output of the driver being connected to an input of the comparator circuit, an output of the comparator circuit being connected to an input of the latch, an output of the latch being an output of the digital isolator;
the comparator circuit compares the output signal of the driver, when the output signal of the driver is a pulse of a first polarity, the latch is set to a first logic latch state, the output end of the latch outputs a first logic, when the output signal of the driver is a pulse of a second polarity, the latch is set to a second logic latch state, and the output end of the latch outputs a second logic.
8. The digital isolator according to claim 7, wherein the driver is a six-terminal transformer of two mutually coupled coils.
9. The digital isolator of claim 8, wherein the receiver further comprises a resistor-capacitor circuit connected in series between the driver and the comparator.
CN202011228087.XA 2020-11-05 2020-11-05 Edge modulation transmitter and digital isolator Pending CN112234953A (en)

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