CN112233622A - GOA circuit and display panel - Google Patents
GOA circuit and display panel Download PDFInfo
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- CN112233622A CN112233622A CN202011136603.6A CN202011136603A CN112233622A CN 112233622 A CN112233622 A CN 112233622A CN 202011136603 A CN202011136603 A CN 202011136603A CN 112233622 A CN112233622 A CN 112233622A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a GOA circuit and a display panel, wherein the GOA circuit comprises a plurality of cascaded GOA units, and the front m-level GOA unit comprises a starting circuit. The starting circuit is connected with the pull-up control modules of the corresponding GOA units and is used for controlling the pull-up control modules of the previous m-level GOA units to be started in sequence; wherein m is a positive integer. According to the invention, the pull-up control modules of the previous m-level GOA units are controlled to be sequentially started through the starting circuits corresponding to the previous m-level GOA units one by one, so that the charging time of the nodes Q of the previous m-level GOA units can be equalized, and the brightness uniformity of the display panel is improved.
Description
Technical Field
The invention relates to the field of display, in particular to a GOA circuit and a display panel.
Background
The Gate Driver on Array (GOA) technology is an Array substrate line driving technology, which utilizes a Thin Film Transistor (TFT) Array process to fabricate a Gate scan driving circuit on a TFT Array substrate of an LCD and an OLED display device, so as to implement a line-by-line scanning driving method, and has the advantages of reducing production cost and implementing a narrow frame design of a panel. The GOA circuit has two basic functions: the first is to output a grid scanning driving signal to drive a grid line in a panel and open a TFT in a display area so as to charge a pixel; the second is a shift register function, when one gate scanning driving signal is output, the next gate scanning driving signal is output through clock control and is sequentially transmitted.
As shown in fig. 1 (taking 8 clock signals as an example), the basic architecture of a conventional GOA circuit is generally as follows, in each row (except for the first 4 stages), the thin film transistor T1 is turned on by the output terminal G (N-4), the node Q (N) rises, the thin film transistor T2 is turned on, the clock signal CK (N) is at a high level, the output terminal G (N) outputs a high level, and the pixels in the nth row are ready to be charged. Because the thin film transistor T1 of the previous 4-level GOA is uniformly turned on by the start signal STV signal, the charging time of the node Q (N) point is unequal, and the charging time of the nodes Q (1) -Q (4) is sequentially reduced, thereby causing different opening degrees of the thin film transistor T2, unequal output voltages of the output ends G (1) -G (4), and further causing unequal charging rates of pixel circuits, and the problem of uneven brightness of the front 4 rows of the display panel.
Therefore, how to avoid the problem of uneven brightness of the display panel caused by the unequal output voltages of the output terminals of the G0A cells in the previous stages becomes a technical problem to be solved and a focus of research is always needed by those skilled in the art.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a GOA circuit and a display panel to solve the problem of uneven brightness of the display panel caused by unequal output voltages of output terminals of the G0A cells in the previous stages.
Therefore, the embodiment of the invention provides the following technical scheme:
the invention provides a GOA circuit in a first aspect, which comprises a plurality of cascaded GOA units, wherein the first m-level GOA unit comprises a starting circuit;
the starting circuit is connected with the pull-up control modules of the corresponding GOA units and is used for controlling the pull-up control modules of the previous m-level GOA units to be started in sequence; wherein m is a positive integer.
Further, the turn-on circuit includes a first thin film transistor (T01) and a second thin film transistor (T02);
the grid electrode of the first thin film transistor (T01) is connected with a pull-down signal (PD), the source electrode of the first thin film transistor is connected with a starting Signal (STV), and the drain electrode of the first thin film transistor is connected with the output end of the starting circuit;
the grid electrode of the second thin film transistor (T02) is connected with a pull-up signal (PU), the source electrode of the second thin film transistor is connected with a constant-voltage low-level signal (VSS), and the drain electrode of the second thin film transistor is connected with the output end of the starting circuit;
and the output end of the starting circuit is connected with the pull-up control module of the corresponding GOA unit.
Further, the turn-on circuit further comprises a first capacitor (C0);
one end of the first capacitor (C0) is connected with the constant-voltage low-level signal (VSS), and the other end of the first capacitor is connected with the output end of the starting circuit.
Furthermore, N is a positive integer greater than m, and a level signal output end of the nth-m level GOA unit is connected to the pull-up control module of the nth level GOA unit for providing a turn-on signal.
Further, the pull-up signal (PU) and the pull-down signal (PD) are independent signals, respectively.
Further, the pull-up signal (PU) is provided by a first clock signal;
the pull-down signal (PD) is provided by a second clock signal.
In a second aspect, the present invention provides a display panel including the GOA circuit according to any one of the embodiments of the first aspect of the present invention.
The technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a GOA circuit. In the conventional GOA circuit, taking 8 clock signals as an example, the thin film transistors of the first 4-level GOA are usually turned on uniformly by a start signal, which causes unequal charging rates of pixel circuits and uneven brightness of the first 4 rows of the display panel. According to the invention, the pull-up control modules of the previous m-level GOA units are controlled to be sequentially started through the starting circuits corresponding to the previous m-level GOA units one by one, so that the charging time of the nodes Q of the previous m-level GOA units can be equalized, and the brightness uniformity of the display panel is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram of a GOA circuit according to a conventional embodiment.
Fig. 2 is a circuit diagram of a power-on circuit according to an embodiment of the invention.
Fig. 3 is a waveform diagram of a node Q in the first 4-stage GOA unit of the GOA circuit of fig. 1.
Fig. 4 is a waveform diagram of a node Q in a previous 4-stage GOA unit of the GOA circuit of fig. 2.
Fig. 5 is a waveform diagram of an output waveform of the first 16 stages of the GOA unit in the GOA circuit of fig. 1.
Fig. 6 is a waveform diagram of the output of the first 16 stages of the GOA unit in the GOA circuit of fig. 2.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Fig. 1 is a schematic diagram of a GOA circuit according to a conventional embodiment. As shown in fig. 1, the pull-up control module includes a thin film transistor T1. The thin film transistor T1 is turned on by the stage signal output terminal G (N-4) of the GOA unit of the nth-4 stage. The potential of the node Q (N) rises, the pull-up thin film transistor T2 is turned on and the clock signal CK (N) is high, the stage signal output terminal G (N) outputs high, and the pixels in the nth row are ready to be charged. Because the thin film transistor T1 of the pull-up control module of the previous 4-level GOA unit is uniformly turned on by the start signal STV, the charging time of the node Q (N) is unequal, and the charging time of the nodes Q (1) -Q (4) is sequentially reduced, thereby causing different turning-on degrees of the thin film transistor T2 in the previous 4-level GOA unit, unequal output voltages of the level signal output ends G (1) -G (4), and further causing unequal charging rates of the pixel circuits, and the problem of uneven brightness of the previous 4 rows of the display panel.
The invention provides a GOA circuit which comprises a plurality of cascaded GOA units, wherein the GOA unit of the previous m levels comprises a starting circuit. The starting circuit is connected with the pull-up control modules of the corresponding GOA units and is used for controlling the pull-up control modules of the previous m-level GOA units to be started in sequence; wherein m is a positive integer.
In this embodiment, each single-stage GOA unit includes a node Q, and a pull-up control module, a pull-up module, and a pull-down module electrically connected to the node Q, respectively. The pull-up control module is used for pulling up the potential of the node Q. The pull-up module is used for outputting an output signal under the potential control of the node Q. The pull-down module is used for pulling down the potential of the node Q to a low potential and pulling down the output stage signal to a low potential. And N is a positive integer larger than m, and the pull-up control module of the Nth-level GOA unit is started by a level signal output end of the N-m-level GOA unit. And the starting circuits of the GOA units in the previous m levels sequentially send starting signals to the corresponding pull-up control modules according to the sequence from the 1 st level to the m th level. And the starting circuits of two adjacent stages of GOA units send starting signals at set time intervals.
Compared with the prior art, the pull-up control modules of the previous m-level GOA units are controlled to be sequentially started through the starting circuits corresponding to the previous m-level GOA units one by one, so that the charging time of the nodes Q of the previous m-level GOA units can be equalized, and the brightness uniformity of the display panel is improved.
Fig. 2 is a circuit diagram of a power-on circuit according to an embodiment of the invention. In one embodiment, as shown in fig. 2, the turn-on circuit includes a first thin film transistor T01 and a second thin film transistor T02. The gate of the first thin film transistor T01 is connected to the pull-down signal PD, the source is connected to the start signal STV, and the drain is connected to the output terminal of the turn-on circuit. The gate of the second thin film transistor T02 is connected to the pull-up signal PU, the source is connected to the constant voltage low level signal VSS, and the drain is connected to the output terminal of the turn-on circuit. The output end of the starting circuit is connected with the pull-up control module of the corresponding GOA unit.
In this embodiment, the pull-up control module includes a thin film transistor T1. The output terminal of the turn-on circuit is connected to the gate of the thin film transistor T1. Preferably, the pull-up signal PU and the pull-down signal PD are respectively provided by separate control chips. The pull-up signal PU may optionally be provided by a first clock signal. The pull-down signal PD may optionally be provided by a second clock signal.
In a specific embodiment, the turn-on circuit further comprises a first capacitor (C0). One end of the first capacitor (C0) is connected with a constant-voltage low-level signal (VSS), and the other end is connected with the output end of the starting circuit.
In this embodiment, the first capacitor (C0) can adjust the output waveform of the GOA circuit.
In a specific embodiment, N is a positive integer greater than m, and the stage signal output terminal of the N-m stage GOA unit is connected to the pull-up control module of the nth stage GOA unit for providing the turn-on signal.
In this embodiment, m may be 4. The gate of the third thin film transistor T1 of the nth level GOA unit is connected to the level signal output terminal of the nth-4 level GOA unit, and the source and drain are connected to the level signal output terminal of the nth-4 level GOA unit and the node Q of the nth level GOA unit, respectively.
Fig. 3 is a waveform diagram of a node Q in the first 4-stage GOA unit of the GOA circuit of fig. 1. The upper one in fig. 3 is a waveform of the initial signal STV, and the lower 4 are waveforms of the nodes Q of the 1 st to 4 th-stage GOA units. Fig. 4 is a waveform diagram of a node Q in a previous 4-stage GOA unit of the GOA circuit of fig. 2. The upper one in fig. 4 is a waveform of the initial signal STV, and the lower 4 are waveforms of the nodes Q of the 1 st to 4 th-stage GOA units. Fig. 5 is a waveform diagram of an output waveform of the first 16 stages of the GOA unit in the GOA circuit of fig. 1. In fig. 5, the on voltage, the rising time, the falling time, and the off voltage are shown in order from top to bottom. Fig. 6 is a waveform diagram of the output of the first 16 stages of the GOA unit in the GOA circuit of fig. 2. In fig. 6, the on voltage, the rising time, the falling time, and the off voltage are shown in order from top to bottom. As shown in fig. 3, 4, 5 and 6, in the GOA circuit provided by the embodiment of the present invention, the uniformity of the output (including the on/off voltages VG _ on/VG _ off, rise time and fall time) of the node Q (N) in the first 4 rows is significantly better than that of the conventional GOA circuit. And the output of 5-16 rows of the GOA circuit provided by the embodiment of the invention is the same as that of the existing GOA circuit. Compared with the prior art, the starting circuit can balance the charging time of the node Q of the previous 4-level GOA unit, does not influence the output of other GOA units, and can improve the brightness uniformity of the display panel.
The invention also provides a display panel comprising the GOA circuit of any embodiment of the invention.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (7)
1. A GOA circuit comprises a plurality of cascaded GOA units, and is characterized in that the GOA unit of the previous m levels comprises a starting circuit;
the starting circuit is connected with the pull-up control modules of the corresponding GOA units and is used for controlling the pull-up control modules of the previous m-level GOA units to be started in sequence; wherein m is a positive integer.
2. A GOA circuit according to claim 1, characterized in that the turn-on circuit comprises a first thin film transistor (T01) and a second thin film transistor (T02);
the grid electrode of the first thin film transistor (T01) is connected with a pull-down signal (PD), the source electrode of the first thin film transistor is connected with a starting Signal (STV), and the drain electrode of the first thin film transistor is connected with the output end of the starting circuit;
the grid electrode of the second thin film transistor (T02) is connected with a pull-up signal (PU), the source electrode of the second thin film transistor is connected with a constant-voltage low-level signal (VSS), and the drain electrode of the second thin film transistor is connected with the output end of the starting circuit;
and the output end of the starting circuit is connected with the pull-up control module of the corresponding GOA unit.
3. A GOA circuit in accordance with claim 2, characterized in that said turn-on circuit further comprises a first capacitance (C0);
one end of the first capacitor (C0) is connected with the constant-voltage low-level signal (VSS), and the other end of the first capacitor is connected with the output end of the starting circuit.
4. The GOA circuit of claim 1, wherein N is a positive integer greater than m, and a stage signal output terminal of the GOA unit of the N-m stage is connected to the pull-up control module of the GOA unit of the Nth stage for providing a turn-on signal.
5. A GOA circuit according to claim 2, characterized in that the pull-up signal (PU) and the pull-down signal (PD) are separate signals.
6. A GOA circuit according to claim 2, characterized in that the pull-up signal (PU) is provided by a first clock signal;
the pull-down signal (PD) is provided by a second clock signal.
7. A display panel comprising the GOA circuit of any one of claims 1-6.
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| CN202011136603.6A CN112233622B (en) | 2020-10-22 | 2020-10-22 | GOA circuit and display panel |
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| CN202011136603.6A CN112233622B (en) | 2020-10-22 | 2020-10-22 | GOA circuit and display panel |
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