CN101040315A - Drive circuit for display device, and display device having the circuit - Google Patents

Abstract

Output signals (QB) from individual flip-flops (SR1, SR2 and so on) are used to create sampling signals (SMP1, SMP2 and so on) to individual data signal lines, and output signals from output terminals (PO) in the flip-flops (SR1, SR2 and so on) are used to create precharge signals (PSMP1, PSMP2 and so on) for charging the same data signal lines preliminarily as the data signal lines, from which the individual sampling signals (SMP1, SMP2 and so on) are outputted. NOR circuits (NOR1, NOR2 and so on) are provided to prevent overlaps between the active periods of the precharge signals (PSMP1, PSMP2 and so on) and the individual sampling signals (SMP1, SMP2 and so on). As a result, a drive circuit for a display device, which is equipped therein with a preliminary charging circuit for charging signal supply lines preliminarily from a preliminary charging power source, can reduce the number of steps of shift registers and accordingly the size of the circuit.

Description

The driving circuit of display device and possess the display device of this circuit

Technical field

The present invention relates to a kind of driving circuit and possess the display device of this circuit, this driving circuit is formerly carried out after the preparation charging, provides line to provide to write to the signal of display device and uses signal.

Background technology

In the active array type LCD that dot sequency drives, when carrying out the AC driving of liquid crystal panel, in order to make each pixel stablize, charge, before providing vision signal, each data signal line execution is prepared charge (precharge) through data-signal alignment pixel with the quantity of electric charge of expecting.At this moment, if the total data signal wire is once carried out the preparation charging, then because the total amount of the wiring capacitance of total data signal wire is big, so the essential driving force that improves the preparation charge power supply.As the technology that can address this problem, the technology by each unit execution preparation charging to few data signal line is arranged.

For example, open in the flat 7-295520 communique (November 10 nineteen ninety-five is open) the spy who openly speciallys permit communique as Japan, following formation is disclosed, promptly when the time to a data signal line outputting video signal, use is used to sample from the signal of the vision signal of the shift register output of data-signal line drive, the switch of another data signal line is made as the ON state, carries out the preparation charging from the preparation charge power supply.

Open in the flat 7-295520 communique the spy, in order to press dot sequency to the data signal line outputting video signal, the switch that the MOSFET comprise TFT etc. has capacitive character control terminal (for example grid) is set in each data signal line, control the charging voltage of this control terminal, press dot sequency switched conductive and non-conduction.The control signal (for example signal) of switching this switch by dot sequency is generally exported by the shift register along continuous straight runs displacement back that multistage bistable multivibrator constituted.In addition, contact order switched conductive and non-conduction the same switch also are set in addition in order to carry out the preparation charging in each data signal line.

Open the formation of flat 7-295520 communique according to the spy, the circuit of carrying out preparation charging usefulness is set, can guarantee the sufficient housing area of liquid crystal indicator etc., realize that the area of preparation charging circuit reduces by inside at the data-signal line drive.

But, open in the data-signal line drive of flat 7-295520 communique the spy, also use the signal of switch owing to switching being used for the sample video signals sampling with the signal of switch, so exist the homogeneity that shows to hang down inferior, as to show grade deterioration problem as the preparation charging of other data signal line of switching.

That is owing to carry out the preparation charging of carrying out based on AC driving, the current potential that makes each data signal line and pixel capacitance with last time vision signal sampling the time reversal of poles, change big, so big pulse type charging current is followed in the conversion of switch at this moment.Because the control terminal of above-mentioned switch is a capacitive character, be delivered to the control signal circuit of switch through the electric capacity of control terminal so worry the higher frequency component of the charging current that this is big, the current potential of control signal circuit is shaken, write the control terminal of the switch of usefulness again through vision signal, cause shaking of the vision signal that offers data signal line.Shaking of this vision signal makes show uniformity low inferior, makes to show that grade worsens.

As the scheme that solves this problem, the application's applicant opens in the 2004-54235 communique (on February 19th, 2004 is open) in openly specially permit the disclosed spy of communique in first to file and as Japan, following formation is disclosed, promptly not shared switching sampling with the output circuit of the signal of switch, with open and close the output circuit of preparation charging with the signal of switch.In view of the above, can avoid following big electric current that the preparation charging flows through data signal line through the preparation charging with the capacitive character control terminal of switch, make and should write the current potential of just carrying out the vision signal in the data signal line that writes at this moment and shake.

Below, illustrate that with Figure 30 and Figure 31 above-mentioned spy opens a configuration example of disclosed data-signal line drive in the 2004-54235 communique.

As shown in figure 30, data-signal line drive 131 possesses shift register 131a and the 131b of sampling portion.In addition, shift register 131a possess multistage be provided with restoration type bistable multivibrator srff1, srff2 ..., corresponding at different levels, possess on-off circuit asw1, asw2 ...

Bistable multivibrator srff1, srff2, srff3 ... output be followed successively by output signal dq1, q1, q2 ...Wherein, output signal q1, the q2 after the bistable multivibrator srff2 after the 2nd grade ... impact damper Buf1, the Buf2 that possesses through the 131b of sampling portion ... be input to switch v_asw1, v_asw2 ...Switch v_asw1, the v_asw2 of the 131B of sampling portion ... be switch with capacitive character control terminal (for example grid), by output signal q1, q2 ... the input conducting.If conducting, the current potential of the analog video signal VIDEO that then will import jointly output to data signal line sl1, sl2 ...That is, output signal q1, q2 ... it is the sampling timing pulse of video signal VIDEO.

These output signals dq1, q1, q2 ... be used as on-off circuit asw1, asw2, asw3 ... control signal import in proper order.On-off circuit asw1, asw2 ... if conducting is then if odd level then is taken into and clock signal sck, if even level then is taken into and clock signal sckb.Clock signal sckb is the reverse signal of clock signal sck.

These on-off circuits asw1, asw2 ... output be followed successively by output signal dsr1, sr1, sr2 ... these output signals are in the signalization that constitutes secondary bistable multivibrator srff, constitute the reset signal of prime bistable multivibrator srff, and, here, be constituted to the 131b of sampling portion switch p_asw2, p_asw3 ... input signal.In addition, to elementary bistable multivibrator srff1 input starting impulse ssp, as signalization, this starting impulse ssp also constitutes the input signal of switch p_asw1.

Switch p_asw1, the p_asw2 of the 131b of these sampling portions ... with switch v_asw1, v_asw2 ... the same, it is switch with capacitive character control terminal, by starting impulse ssp, output signal dsr1, sr1, sr2 ... the input conducting, if conducting, the preparation charging potential PVID that then will import jointly output to data signal line sl1, sl2 ...That is, starting impulse ssp, output signal dsr1, sr1, sr2 ... it is the control signal of preparation charging usefulness.

At data signal line sl1, sl2 ... in, be provided with orthogonally scan signal line gl1, gl2 ...In addition, on the intersection point of data signal line sl and scan signal line gl, form pixel Pix1_1, Pix1_2 rectangular.

Figure 31 is the time diagram of the data-signal line drive 131 of above-mentioned formation.If input starting impulse ssp, then also with its input switch p_asw1, preparation charging data signal line s11.At this moment, because switch v_asw1 is non-conduction, so preparation charging potential PVID can not conflict on data signal line sl1 with video signal VIDEO.

In addition, by input starting impulse ssp, from bistable multivibrator srff1 output signal output dq1, thus, on-off circuit asw1 conducting is taken into clock signal sck, output signal output dsr1.Output signal dsr1 constitutes the signalization of bistable multivibrator srff2, bistable multivibrator srff2 output signal output q1.

By output signal output q1, switch asw2 conducting, switch asw2 is taken into clock signal sckb, output signal output sr1.In addition, output signal q1 through impact damper Buf1, makes switch v_asw1 conducting as timing pip.Thus, data signal line sl1 provides video signal VIDEO.At this moment, because starting impulse ssp become Low, so that switch p_asw1 becomes is non-conduction.Therefore, at this moment, preparation charging potential PVID can not conflict on data signal line sl1 with video signal VIDEO yet.

In addition, because switch p_asw1 is output signal dsr1 conducting, so when video signal VIDEO is outputed to data signal line sl1, preparation charging data signal line sl2.

Like this, be repeated below action successively, promptly after the preparation charging of carrying out data signal line sln, sln provides video signal VIDEO to data signal line, during the providing of this video signal VIDEO, carry out the preparation charging of data signal line sl (n+1), press dot sequency and carry out and sample.

In addition, open in the flat 11-218738 communique (on August 10th, 1999 is open) the spy who openly speciallys permit communique as Japan, put down in writing following technology, promptly, write precharging signal to data line by the line order possessing bidirectional shift register, carrying out in the electrooptical device of counter-rotating demonstration.In the technology of in the document, putting down in writing, output stage before 2 grades of the output stages of sample circuit drive signal is carried out the output of pre-charge circuit drive signal, by the precharging signal commutation circuit, corresponding to the direction of displacement of bidirectional shift register, select the output stage of pre-charge circuit drive signal.

Applicant in the application opens in the 2001-135093 communique (May 18 calendar year 2001 is open) in openly specially permit the disclosed spy of communique in first to file and as Japan, following formation is disclosed, promptly receive and constitute the shift register output that the restoration type bistable multivibrator is set at different levels, be taken into clock signal by on-off circuit, this clock signal is made as the signalization that subordinate is provided with the restoration type bistable multivibrator.In addition, the disclosed spy of communique opens 2001-307495 communique (November 2 calendar year 2001 is open) and the spy opens in the 2000-339985 communique (on Dec 8th, 2000 disclosed) in openly speciallyying permit in first to file and as Japan the application's applicant, following formation is disclosed, promptly, receive and constitute the shift register output that the restoration type bistable multivibrator is set at different levels, be taken into clock signal, carry out the level shift of this clock signal, form the signalization that subordinate is provided with the restoration type bistable multivibrator.

But, open in the technology of flat 7-295520 communique and Te Kai 2004-54235 communique above-mentioned spy, before a data signal line outputting video signal, use signal to output stage before the vision signal output stage of this data signal line, carry out the preparation charging.

Therefore, in order to carry out the preparation charging of the 1st data signal line or the 1st and the 2nd data signal line, must append the output stage (pseudo-level, tseudo circuit) of preparation charging usefulness to the prime of shift register, it is big that the area of driving circuit becomes.For example the output before using 2 grades is carried out in the formation of preparation charging, and 2 grades of pseudo-levels must be set.

And except that the occupied area increase of pseudo-level, the area that the cabling of wiring is used also increases, and the housing area outside the viewing area increases.Therefore, be unsuitable for for example being equipped on portable with display device on equipment etc. etc., require small-sized, make the narrow display device of housing outside the viewing area for miniaturization.

In addition, open in the technology of flat 11-218738 communique, must possess the precharging signal commutation circuit, be used for direction of displacement, select the output stage of pre-charge circuit drive signal corresponding to bidirectional shift register the spy.To the input of this precharging signal commutation circuit from the pre-charge circuit drive signal of 2 grades of output stages each direction of displacement, preceding and pre-charge circuit drive signal from back 2 grades of output stages.Therefore, the cabling area of the occupied area of precharging signal commutation circuit and wiring increases, and causes the maximization of driving circuit.

Like this, in the driving circuit of existing display device, exist in order to carry out preparation charging, the area of driving circuit and the problems such as cabling area increase of wiring.In addition, above-mentioned spy opens that 2001-135093 communique, spy are opened the 2001-307495 communique, the spy opens in the 2000-339985 communique does not have any prompting to the preparation charging.

Summary of the invention

The present invention makes in view of above-mentioned existing issue, its purpose be miniaturization inside possess the preparation charging circuit display device driving circuit area and a kind of display device that possesses the viewing area field width of this driving circuit is provided.

In order to solve above-mentioned problem, the driving circuit of display device of the present invention is provided with: write circuit, the a plurality of signals that are provided with in the display device line is provided each possess the 1st switch, and utilize the conducting of above-mentioned each the 1st switch, carry out the writing of write signal that above-mentioned each signal is provided line; Shift register possesses multistage generation and is used to make the pulse of the timing pip of above-mentioned the 1st switch conduction to generate parts, exports the timing pip that above-mentioned each signal is provided line successively; With the preparation charging circuit, above-mentioned signal line is provided each possess the 2nd switch, and utilize the conducting of above-mentioned each the 2nd switch, execution provides the preparation charging of line to above-mentioned each signal, it is characterized in that: above-mentioned each pulse generates the parts input generates parts output from the above-mentioned pulse of each prime above-mentioned timing pip, after this timing pip becomes the activation level that makes above-mentioned the 1st switch conduction, in during before the above-mentioned timing pip of above-mentioned each pulse generation parts self output activation level, generate the timing pip of parts self output according to above-mentioned each pulse, make the above-mentioned signal that writes corresponding to execution that above-mentioned the 2nd switch conduction of line is provided, output is used to prepare the preparation charging pulse that this signal of charging provides line.

According to above-mentioned formation, above-mentioned each pulse generates parts according to the timing pip of self exporting, and makes the above-mentioned signal that writes corresponding to execution that above-mentioned the 2nd switch conduction of line is provided, and output is used to prepare the preparation charging pulse that this signal of charging provides line.Thus, essential tseudo circuit before needn't being provided with, this tseudo circuit generates the timing pip that parts or elementary and the 2nd grade of pulse generate parts output according to elementary above-mentioned pulse, and output is used to prepare charging and carries out the above-mentioned signal that writes and provide the preparation of line and charge and use pulse.Therefore, Miniaturizable inside possess the preparation charging circuit display device driving circuit area and around the above-mentioned driving circuit wiring area of cabling.

In order to solve above-mentioned problem, display device of the present invention possesses a plurality of pixels; The data signal line of line is provided and the scan signal line of line is provided as a plurality of signals corresponding to a plurality of signals of the conduct of above-mentioned pixel setting; To write the data-signal line drive of above-mentioned data signal line and above-mentioned pixel as the vision signal of write signal; With the sweep signal line drive, in order to select to write the pixel of above-mentioned vision signal, write sweep signal as write signal to above-mentioned scan signal line, it is characterized in that: possess the driving circuit of above-mentioned display device, as above-mentioned data-signal line drive.

According to above-mentioned formation owing to can reduce the size of the driving circuit of display device, so can reduce display part the housing area, be the area of non-display area, realize the display device of viewing area field width.

Description of drawings

Fig. 1 is the formation block diagram of the data-signal line drive of expression an embodiment of the present invention.

Fig. 2 is the formation block diagram of display device that expression possesses the data-signal line drive of an embodiment of the present invention.

Fig. 3 is the block diagram that the pixel of the display device of presentation graphs 2 constitutes.

Fig. 4 is the formation block diagram of the bistable multivibrator that possesses in the data-signal line drive of expression an embodiment of the present invention.

Fig. 5 is the formation block diagram of the level shifter control circuit that possesses in the data-signal line drive of expression an embodiment of the present invention.

Fig. 6 is the formation block diagram of the level shifter that possesses in the data-signal line drive of expression an embodiment of the present invention.

Fig. 7 is the formation block diagram of the bistable multivibrator that possesses in the bistable multivibrator of presentation graphs 4.

Fig. 8 relates to the signal timing figure of action of the bistable multivibrator of Fig. 8.

Fig. 9 relates to the signal timing figure of the action of bistable multivibrator shown in Figure 4.

Figure 10 relates to possess the signal timing figure of action of the shift register portion of bistable multivibrator shown in Figure 4.

Figure 11 is in the data-signal line drive of expression an embodiment of the present invention, the overlapping formation block diagram that prevents the delay circuit that possesses in the portion.

Figure 12 is the signal timing figure of the action of expression delay circuit shown in Figure 11.

Figure 13 is in the data-signal line drive of expression an embodiment of the present invention, the overlapping formation block diagram that prevents the buffer circuits that possesses in the portion.

Figure 14 is the overlapping timing diagram that prevents portion in the data-signal line drive of an embodiment of the present invention.

Figure 15 is a block diagram in the data-signal line drive of expression an embodiment of the present invention, a configuration example of sampling portion.

Figure 16 is a block diagram in the data-signal line drive of expression an embodiment of the present invention, another configuration example of sampling portion.

Figure 17 be in the data-signal line drive of expression an embodiment of the present invention, the block diagram of a configuration example again of sampling portion.

Figure 18 is in the data-signal line drive of expression an embodiment of the present invention, replace the formation block diagram of the shift register piece that bistable multivibrator possesses.

Figure 19 relates to the signal timing figure of action of the shift register piece of Figure 18.

Figure 20 is the formation block diagram of the data-signal line drive of another embodiment of expression the present invention.

Figure 21 is a formation block diagram that possess, bistable multivibrator SRFF in the data-signal line drive of expression the present invention another embodiment.

Figure 22 is the formation block diagram of the selector switch that possesses in the bistable multivibrator of expression Figure 21.

Figure 23 relate to Figure 21 bistable multivibrator action signal, the timing diagram when direction of displacement is forward.

The timing diagram of bistable multivibrator signal, that make Figure 21 of data-signal line drive action that Figure 24 relates to another embodiment of the present invention during along forward shift.

Figure 25 relate to Figure 21 bistable multivibrator action signal, the timing diagram when direction of displacement is reverse.

The timing diagram of bistable multivibrator signal, that make Figure 21 of data-signal line drive action that Figure 26 relates to another embodiment of the present invention during along shift reverse.

Figure 27 is in the data-signal line drive of expression the present invention another embodiment, replace the formation block diagram of the shift register piece that the bistable multivibrator of Figure 21 possesses.

Figure 28 relate to Figure 27 shift-register circuit action signal, the timing diagram when direction of displacement is forward.

Figure 29 relate to Figure 27 shift-register circuit action signal, the timing diagram when direction of displacement is reverse.

Figure 30 is the formation block diagram of the existing data-signal line drive of expression.

Figure 31 relates to the timing diagram of signal of the data-signal line drive action of Figure 22.

Figure 32 is the block diagram of variation that possess, bistable multivibrator in the data-signal line drive of expression an embodiment of the present invention.

Figure 33 is the formation block diagram of the level shifter control circuit that possesses in the expression bistable multivibrator shown in Figure 32.

Figure 34 is the formation block diagram of the level shifter that possesses in the expression bistable multivibrator shown in Figure 32.

Figure 35 relates to the timing diagram of the signal of bistable multivibrator action shown in Figure 32.

Embodiment

[embodiment 1]

With accompanying drawing one embodiment of the present invention is described.Fig. 1 is formation block diagram driving circuit, data-signal line drive 31 of expression as the display device of present embodiment.Data-signal line drive 31 as shown in Figure 2, be the data signal line SL1, the SL2 that drive liquid crystal indicator (display device) ... the data-signal line drive.

(liquid crystal indicator 1)

Liquid crystal indicator 1 is dot sequency according to pixels and the active array type LCD of carrying out AC driving, possesses: have the display part 2 that is configured to rectangular pixel PIX, the data-signal line drive 31 that drives each pixel PIX and sweep signal line drive 4, control circuit 5 and data signal line SL1, SL2 ... with scan signal line GL1, GL2 ...In addition, control circuit 5 generates the video signal VIDEO of the show state of each pixel PIX of expression, and according to this video signal VIDEO, display image.

Each pixel PIX is configured in respectively by cross one another m bar scan signal line GL1-GLm and n bar data signal line SL1-SLn and distinguishes in rectangular each zone that forms.In addition, data-signal line drive 31 and sweep signal line drive 4 will be by writing each pixel PIX successively through data signal line SL1-SLn and scan signal line GL1-GLm from the VIDEO signal of control circuit 5 inputs, and carries out image shows.

Fig. 3 represents to be configured in constituting by the pixel PIX in the zone of j scan signal line GLj and i data signal line SLi differentiation.The formation of each pixel PIX is the same.

As shown in the figure, pixel PIX is made of with transistor (field effect transistor) SW and pixel capacitance Cp conversion.Pixel capacitance Cp is by liquid crystal capacitance C1c, constitute with additional in case of necessity auxiliary capacitor Cs.

Conversion is connected in scan signal line GL with the grid of transistor SW, and source electrode is connected in data signal line SL, and drain electrode is connected in pixel capacitance Cp (liquid crystal capacitance C1c and auxiliary capacitor Cs).Another electrode of pixel capacitance Cp is connected on the common common electrode lines of whole pixel PIX.

Therefore, if select scan signal line GL, then conversion puts on the voltage that puts on the data signal line SL on the pixel capacitance Cp with transistor SW conducting.On the other hand, finish during the selection of scan signal line GL, block conversion with transistor SW during, the voltage when pixel capacitance Cp continues to keep this to block.Here, the transmitance of liquid crystal or reflectivity are along with the change in voltage that puts on the liquid crystal capacitance C1c.Therefore, by selecting scan signal line GL, and apply voltage, the show state of pixel PIX and video signal VIDEO are consistently changed corresponding to video signal VIDEO to data signal line SL.

Control circuit 5 generates clock signal (just changeing clock signal) SCK and reverse signal (counter-rotating clock signal) SCKB, starting impulse SSP and reverse signal SSPB and video signal VIDEO, and outputs to data-signal line drive 31.In addition, control circuit 5 provides preparation charging potential PVID to data-signal line drive 31.Control circuit 5 also generates clock signal GCK, starting impulse GSP and signal GPS, and outputs to sweep signal line drive 4.

Data-signal line drive 31 possesses shift register 31a, the 31b of sampling portion, overlapping 31c of portion and the level shifter LS of preventing.

Here, transmit the video signal VIDEO of conduct to 31 time-divisions of data-signal line drive to the image signal of each pixel PIX.Data-signal line drive 31 based on the clock signal SCK that becomes timing signal, SCKB, with by level shifter LS starting impulse SSPB is transformed to the timing of the signal SSPB ' of assigned voltage, from video signal VIDEO, extract Image Data to each pixel PIX.Particularly, shift register 31a by with the connection of the clock signal SCK starting impulse SSPB ' that regularly is shifted synchronously, successively, generate regularly at different output signal S1-Sn of per semiperiod of clock signal SCK, the 31b of sampling portion is in the timing shown in each output signal S1-Sn, sampling VIDEO signal outputs to each data signal line SL1-SLn.

Sweep signal line drive 4 possesses shift register 4a.To this shift register 4a input clock signal GCK, starting impulse GSP, signal GPS.Afterwards, shift register 4a by with the clock signal GCK starting impulse GSP that is shifted synchronously, successively, will regularly output to each scan signal line GL1-GLm by the line order in the different sweep signal of every predetermined distance.Thus, write video signal VIDEO to each pixel PIX successively, carry out image and show.

Formality and wiring capacitance and cloth line resistance when making in order to cut down, with display part 2, and the peripheral circuit monolithic that comprises data-signal line drive 31 and gate drivers 4 be formed on the same substrate.In addition, for integrated more pixel PIX, enlarge display area, display part 2, data-signal line drive 31 and sweep signal line drive 4 are made of the polycrystalline SiTFT that is formed on the glass substrate.And, under the treatment temperature below 600 degree, make above-mentioned polycrystalline SiTFT, even if, also do not produce warpage or bending that the above processing of deformation point causes so that use common glass substrate (deformation point is the following glass substrates of 600 degree).

(data-signal line drive 31)

As shown in Figure 1, data-signal line drive 31 possesses shift register 31a, the 31b of sampling portion, overlapping 31c of portion and the level shifter LS of preventing.

(shift register 31a)

Shift register 31a by multistage be provided with restoration type bistable multivibrator (pulse generation parts) SR (SR1, SR2 ..., SRn+2) constitute.In addition, each bistable multivibrator SR RB terminal, output precharge of possessing CINB terminal, the input reset signal of CK terminal, CKB terminal, the input signalization of input clock signal with signal (preparation charging pulse) PO (PO1, PO2 ..., POn) the PO terminal and output sampling with signal (timing pip) QB (QB1, QB2 ..., QBn) the QB terminal.

Bistable multivibrator SR1, the SR3 of odd level ... to CK terminal input just commentaries on classics clock signal (clock signal) SCK, to CKB terminal input counter-rotating clock signal (clock signal) SCKB.In addition, bistable multivibrator SR2, the SR4 of even level ... to CK terminal input counter-rotating clock signal (clock signal) SCKB, to CKB terminal input just commentaries on classics clock signal (clock signal) SCK.

In addition, to the output signal SSPB ' of the CINB terminal incoming level shift unit LS of the 1st grade of bistable multivibrator SR1, as signalization.Bistable multivibrator SR2, SR3 after the 2nd grade ..., SRn+2 CINB terminal input from the sampling of the prime bistable multivibrator output of each bistable multivibrator with signal (timing pip) QB1, QB2 ..., QBn+1.

In addition, to the 1st grade of bistable multivibrator SR1, SR2 to the n level ..., SRn RB terminal input from output signal QB3, the QB4 of the bistable multivibrators after 2 grades of each bistable multivibrator ..., QBn+2, as reset signal.In addition, import the output signal QBn+2 of the bistable multivibrator SRn+2 of n+2 level to the RB terminal of the bistable multivibrator SRn+1 of n+1 level, to the output signal QBn+2 of the RB terminal input self of the bistable multivibrator SRn+2 of n+2 level.

The 1st grade of bistable multivibrator SR1, SR2 to the n level ..., SRn the PO terminal be connected in overlapping prevent among the 31c of portion corresponding to delay circuit Pd at different levels (Pd1, Pd2 ..., Pdn) on, from this PO terminal output precharge with signal (preparation charging pulse) PO.

(bistable multivibrator SR)

Fig. 4 is the formation block diagram of each bistable multivibrator SR of expression.As shown in the figure, each bistable multivibrator SR possesses level shifter control circuit CN, level shifter LS1, restoration type bistable multivibrator SR-FF, phase inverter I1, phase inverter I2 is set.

(level shifter control circuit CN)

Fig. 5 is the formation block diagram of expression level shifter control circuit (control circuit) CN.As shown in the figure, level shifter control circuit CN by possess two input terminal IN1, IN2 and lead-out terminal CNOUT's or non-(NOR) circuit NR1 constitute.Output signal Q to input terminal IN1 input bistable multivibrator SR-FF.Input to the input signal of the CINB terminal of each bistable multivibrator SR to input terminal IN2.In addition, the PO terminal output signal output CNO from the ENA terminal of lead-out terminal CNOUT to level shifter LS1 and each bistable multivibrator SR.

(level shifter LS1)

Fig. 6 is the block diagram of the configuration example of expression level shifter LS1.This level shifter LS1 roughly possesses the voltage raising and reducing portion 21 of level shift clock signal SCK, SCKB; Needn't provide described clock signal SCK, SCKB during in, block power supply control part 22 to described reduction portion 21 power supply of boosting; In stopping period, block the input control part 23,24 of the signal wire of described boost reduction portion 21 and transmission clock signal SCK, SCKB; In described stopping period, block the input signal control part 25,26 of the input conversion element (P11, P12) of the described reduction portion 21 of boosting; With in stopping period, the output of the reduction portion 21 of boosting is maintained the output stabilizers 27 of setting.

The differential input that the described reduction portion 21 of boosting is input stages is right, possess constitute described input conversion element, source electrode P type connected to one another MOS transistor P11, P12; The constant current source Ic of rated current is provided to the source electrode of two transistor P11, P12; Constitute current mirroring circuit, and be connected in the drain electrode of described transistor P11, P12, constitute can dynamic load N type MOS transistor N13, N14; Transistor P15, the P16 of the CMOS structure of right output with amplifying differential input.The formation of Fig. 6 illustrate from output LSOUT just transferring out the input CK of transistor P12 side odd number bistable multivibrator SR1, SR3 ... in the example of the level shifter LS1 that possesses, even number bistable multivibrator SR2, SR4 ... in under the situation of the level shifter LS1 that possesses, alternately the input of clock signal SCK, SCKB constitutes each other.

Through constituting the N type MOS transistor N31 of described input control part 24, to the grid input clock signal SCKB of described transistor P11, through constituting the N type MOS transistor N33 of described input control part 23, to the grid input clock signal SCK of transistor P12.In addition, through constituting the P type MOS transistor P32 of described input signal control part 26, draw (pull up) power lead on the grid with described transistor P11 to the driving voltage of high level Vdd, equally, through constituting the P type MOS transistor P34 of described input signal control part 25, the grid of described transistor P12 is pulled to the power lead of the driving voltage of high level Vdd.Grid to described transistor N31, N33, P32, P34 provides the output signal CNO from level shifter control circuit CN that is input to the ENA terminal jointly (enable signal ENA).

Therefore, if become the high level of activation from the output signal CNO of level shifter control circuit CN, then allow through described transistor N31, N33 to transistor P11, P12 input clock signal SCKB, SCK, simultaneously, transistor P32, P34 block.On the contrary, if the output signal CNO from level shifter control circuit CN becomes nonactivated low level, then described transistor N31, N33 block, prevent input clock signal SCKB, SCK, simultaneously, transistor P32, P34 conducting are pulled to high level Vdd with the grid of transistor P11, P12, and this transistor P11, the P12 of input stage end really.

On the other hand, the grid of described transistor N13, N14 is connected to each other, and simultaneously, is connected in the drain electrode of transistor P11, N13.On the contrary, the drain electrode of transistor P12 connected to one another, N14 becomes output terminal, is connected on the grid of described transistor P15, N16.The source electrode of transistor N13, N14 is through constituting the N type MOS transistor N21 of described power supply control part 22, is connected on the power lead of driving voltage of low level Vssd.Provide output signal CNO to the grid of described MOS transistor N21 from level shifter control circuit CN.

Therefore, if the output signal CNO of level shifter control circuit CN becomes the high level of activation, then power to the described reduction portion 21 of boosting through described transistor N21, if the output signal CNO of level shifter control circuit CN becomes nonactivated low level, then prevent to described reduction portion 21 power supplies of boosting.

In addition, described output stabilizers 27 is to make the output signal LSOUT of this level shifter LS1 in the stopping period be stabilized in the circuit of the drive voltage level of low level Vssd, P41 constitutes by P type MOS transistor, this P type MOS transistor P41 provides the output signal CNO of level shifter control circuit CN to grid, draws on the power lead of the driving voltage that is connected in described high level Vdd on the grid with described transistor P15, N16.

In the level shifter LS1 that so constitutes, under the situation that the output signal of level shifter control circuit CN is represented to move (high level), transistor N21, N31, N33 conducting, transistor P32, P34, P41 block.Under this state, after transistor P11, N13 or transistor P12, N14, flow out through transistor N21 again from the electric current of constant current source Ic.In addition, the grid to two transistor P12, P11 applies clock signal SCK, SCKB.As a result, the grid of two transistor P11, P12 flows through the electric current of size corresponding to voltage ratio between gate-to-source separately.On the other hand, because transistor N13, N14 are as the energy dynamic load, so the voltage of the tie point of transistor P12, N14 becomes the voltage corresponding to the voltage level difference of described clock signal SCK, SCKB.This voltage is exported as output signal OUT after by transistor P16, N16 power amplification.

Described voltage raising and reducing portion 21 with utilize clock signal SCK, SCKB switches the transistor P12 of input stage, the formation of the conduction and cut-off of P11, it is the voltage driven type difference, be in action, the transistor P12 of input stage, the current drive-type of P11 conducting all the time, as mentioned above, by corresponding to two transistor P12, the ratio of the gate source voltage across poles of P11, shunting is from the electric current of constant current source Ic, even if at described clock signal SCK, the transistor P12 of the amplitude ratio input stage of SCKB, under the also low situation of the threshold value of P11, can there be any obstacle ground level shift clock signal SCK yet, SCKB.

The result, if level shifter LS1 is to apply the high level of activation to the ENA terminal from the output signal CNO of level shifter control circuit CN, even if then output is under the high side of the amplitude ratio driving voltage of clock signal SCK, SCKB and poor (Vcc=Vdd-Vssd is for example about the 15V) of downside low situation (for example about the 5V from the generative circuit of described image signal), also can be with the amplitude voltage raising and reducing output signal LSOUT of described poor Vcc extremely.

On the contrary, under the output signal CNO from level shifter control circuit CN represents to move the nonactivated low level situation that stops, being ended by transistor N21 through the electric current that transistor P11, N13 or transistor P12, N14 flow through from constant current source Ic.Therefore, can cut down the power consumption that this electric current causes.

Under this state, by transistor N33, the N31 of each input control part 23,24.Therefore, cut off the grid of each transistor P12, P11 of the signal wire of transmission clock signal SCK, SCKB and input stage.In addition because transistor P34, the P32 conducting of each input signal control part 25,26 in stopping, so the grid voltage of described two transistor P11, P12 all by on move the driving voltage Vdd of high level to, two transistor P11, P12 end.Thus, the same with the situation of "off" transistor N12, can reduce power consumption corresponding to the electric current of constant current source Ic output.

But, under this state, owing to do not provide electric current,, output terminal, be that the current potential of the drain electrode tie point each other of transistor P12, N14 be can not determine so two transistor P11, P12 can not be as differential input to actions to two transistor P11, P12.Therefore, under described enable signal ENA represented to move situation about stopping, further the transistor P41 of stabilizers 27 was exported in conducting.As a result, described output terminal, be transistor P15, N16 grid potential by on move the driving voltage Vdd of high level to, transistor N16 conducting, output signal LSOUT becomes low level.

The output signal CNO from level shifter control circuit CN represent to move stop during in, the output signal LSOUT of level shifter LS1 all is held in low level regardless of clock signal SCK, SCKB.

(bistable multivibrator SR-FF)

Fig. 7 is the block diagram of expression bistable multivibrator SR-FF one configuration example.As shown in the figure, bistable multivibrator SR-FF is between the power lead of the power lead of the driving voltage Vdd of high level and low level driving voltage Vssd, and being one another in series connects P type MOS transistor P1 and N type MOS transistor N2, N3.

The grid of transistor P1, N3 is connected among this bistable multivibrator SR-FF as being provided with on the SB terminal of input terminal, and the output signal LSO that level shifter LS1 is provided is after by phase inverter I1 counter-rotating, the low signal SB that activates.

In addition, the grid of transistor N2 is connected among this bistable multivibrator SR-FF on the R terminal as the RESET input, and the output signal QB that the bistable multivibrator SR after 2 grades of the RB terminal that is input to each bistable multivibrator SR are provided is after by phase inverter I2 counter-rotating, the high signal R that activates.And the drain potential of described transistor P1 connected to one another, N2 is become described counter-rotating output signal QB by after the phase inverter INV1 counter-rotating, by after 1 grade the phase inverter INV2 counter-rotating, constitutes and is just transferring out signal Q again.

On the other hand, between power lead, also be one another in series and connect P type MOS transistor P4, P5 and N type MOS transistor N6, N7.The drain electrode of transistor P5, N6 is connected in the input of described phase inverter INV1, feeds back the counter-rotating output signal QB of this phase inverter INV1 generation to the grid of two transistor P5, N6.

And the grid of described transistor P4 is connected among this bistable multivibrator SR-FF on the R terminal as the RESET input, and signal R is provided.In addition, the grid of described transistor N7 is connected in being provided with on the input terminal among this bistable multivibrator SR-FF, and signal SB is provided.

Therefore, bistable multivibrator SR-FF during reset signal R is non-activation (low level), is changed to activation (low level) as if signalization SB as shown in Figure 8, and then described transistor P1 conducting makes the input of phase inverter INV1 be changed to high level.Thus, just transferring out signal Q and be changed to high level, counter-rotating output signal QB is changed to low level.Under this state, utilize the counter-rotating output signal QB of reset signal R and phase inverter INV1, transistor P4, P5 conducting remain on described high level with the input of phase inverter INV1.In addition, utilize the counter-rotating output signal QB of reset signal R and phase inverter INV1, transistor N2, N6 end, signalization SB is changed to non-activation (high level), nonetheless, also the input of phase inverter INV1 can be remained on high level, will just transfer out signal Q former state and remain on high level, the output signal of will reversing QB former state remains on low level.

Afterwards, if reset signal R becomes activation (high level), then transistor P4 ends, transistor N2 conducting.Here, because signalization SB still is non-activation (high level), so transistor P1 ends transistor N3 conducting.Therefore, the input of phase inverter INV1 is driven to low level, is just transferring out signal Q and is being changed to low level, and counter-rotating output signal QB is changed to high level.That thus, can realize that signalization SB with described low activation is provided with the low counter-rotating output signal QB that activates, the reset signal R that activates with height resets described counter-rotating output signal QB is provided with the restoration type bistable multivibrator.

(action of bistable multivibrator SR)

Fig. 9 be odd level bistable multivibrator SR1, SR3 ... timing diagram.With regard to bistable multivibrator SR2, the SR4 of even level ..., each the signal relative time clock signal SCK among Fig. 9 moved after the dislocation semiperiod.That is, bistable multivibrator SR2, the SR4 of even level ... as shown in Figure 1, to CK terminal input counter-rotating clock signal (clock signal) SCKB, to CBK terminal input just commentaries on classics clock signal (clock signal) SCK.Therefore, the action of 1 clock (semiperiod) of the bistable multivibrator of execution and odd level dislocation clock signal.

As shown in Figure 9, when the signal CINB of incoming level shift unit control circuit CN is low (Low) level, this moment same stages bistable multivibrator SR in the output Q of bistable multivibrator SR-FF export nonactivated low level.Therefore, the output signal CNO of level shifter control circuit CN becomes height (High) level.

The signal CNO of this high level is input to the ENA terminal of level shifter LS1.In addition, if level shifter LS1 then becomes the state that can carry out the level shifter action to ENA terminal input high level, and the signal of output level displacement input signal SCK is as output signal LSO.

Here, become moment of high level, because clock signal SCK is a low level, so the output signal LSO of level shifter LS1 still is a low level at the signal that is input to the ENA terminal (the output signal CNO of level shifter control circuit CN).In addition, if clock signal SCK (after about semiperiod of clock signal SCK) after about 1 clock becomes high level, then the output signal LSO of level shifter LS1 switches to high level.

The output signal LSO of the level shifter LS1 of this high level becomes low level by phase inverter I1, is input to the input terminal SB of bistable multivibrator SR-FF.

If to the input terminal SB of bistable multivibrator SR-FF input low level, SR-FF then is set, become activation, the output signal Q of bistable multivibrator SR-FF becomes high level, and output signal QB becomes low level.

Here, because level shifter control circuit CN is arrived in the output signal Q of bistable multivibrator SR-FF input (feedback), so become moment of high level at output signal Q, the output signal CNO of level shifter control circuit CN becomes low level.

As if the terminal ENA that the low level of output signal CNO is input to level shifter LS1, then level shifter LS1 becomes non-action status.If level shifter LS1 becomes non-action status, then the output signal LSO of level shifter LS1 becomes low level.Even if output signal LSO becomes low level, the output signal Q of bistable multivibrator SR-FF, QB also export activation level (output signal Q is a high level, and output signal QB is a low level) continuously, up to till reseting terminal R input high level.

The output signal QB that possesses the bistable multivibrator SR after 2 grades of bistable multivibrator SR of this bistable multivibrator SR-FF by phase inverter I2 counter-rotating after, be input to the reseting terminal R of bistable multivibrator SR-FF.Therefore, the output signal Q of bistable multivibrator SR-FF, QB as shown in Figure 9, after becoming activation, clock signal SCK is reset to non-activation at input 2 clocks when (1 cycle of clock signal SCK).

In addition, because being input to the input signal CINB of the input terminal IN2 of level shifter control circuit CN is the output signal QB of the bistable multivibrator SR of prime, so after output signal Q, the QB of bistable multivibrator SR-FF became activation, clock signal SCK became high level at 1 clock of input when (semiperiod of clock signal SCK).

Therefore, when output signal Q, the QB of bistable multivibrator SR-FF revert to non-activation level from activation level, become high level owing to be input to the input signal CINB of input terminal IN2, so the lead-out terminal CNO of level shifter control circuit CN still is a low level.Thus, because level shifter LS1 is a non-action status, so the output signal LSO of level shifter LS1 still is a low level.Therefore, output signal Q, the QB with bistable multivibrator SR-FF remains on non-activation level (output signal Q is a low level, and output signal QB is a high level) really.

In addition, pulse (precharging signal) PO that the output signal CNO of level shifter control circuit CN shown in the timing diagram of Fig. 9 uses as bistable multivibrator formerly (PO1, PO2 ..., POn), be input to the overlapping delay circuit Pd that prevents the own level among the 31c of portion (Pd1, Pd2 ..., Pdn).

As mentioned above, bistable multivibrator SR feeds back to level shifter control circuit CN with output signal Q, becomes activation (low level) before at output signal QB, and the output signal CNO of level shifter control circuit CN becomes high level.Therefore, be used as precharging signal PO, can before constituting the QB of sampling, carry out precharge with pulse by output signal CNO with this level shifter control circuit CN.

Figure 10 be the expression each bistable multivibrator SR1, SR2 ..., SRn the timing diagram of signal output waveform.

As shown in the figure, among the 1st grade the bistable multivibrator SR1, if the output signal SSPB ' of the level shifter LS of input CINB terminal becomes low level from high level, then the output signal PO1 from the PO terminal becomes high level.In addition, if clock signal SCK becomes high level from low level, then the output signal QB1 from the QB terminal switches to low level from high level.In addition, output signal Q1 is fed back to level shifter control circuit CN as mentioned above, if output signal QB1 becomes low level (output signal Q1 is a high level), then the output signal PO1 from the PO terminal becomes high level.

In addition, owing to the output signal QB1 of bistable multivibrator SR1 is input to the CINB terminal of the 2nd grade bistable multivibrator SR2, so if output signal QB1 becomes low level, then the output signal PO2 from the terminals P O of the 2nd grade of bistable multivibrator SR2 becomes high level.Afterwards, if clock signal SCK becomes low level (clock signal SCKB is a high level), then the output signal QB2 from the QB terminal switches to low level from high level.Thus, the output signal PO2 from the PO terminal becomes low level.

Because the output signal QB2 of bistable multivibrator SR2 is imported into the CINB terminal of 3rd level bistable multivibrator SR3, so if output signal QB2 becomes low level, then the output signal PO3 from the PO terminal of the bistable multivibrator SR3 of 3rd level becomes high level.Afterwards, if clock signal SCK becomes high level from low level, then the output signal QB3 from the QB terminal switches to low level from high level.Thus, the output signal PO3 from the PO terminal becomes low level.Here, owing to the output signal QB3 of 3rd level bistable multivibrator SR3 is input to the RB terminal of the 1st grade bistable multivibrator SR1, so if the output signal QB3 of 3rd level bistable multivibrator SR3 is switched to low level, then the output signal QB1 with the 1st grade bistable multivibrator SR1 resets to high level.

Bistable multivibrator SR afterwards also carries out same action, after the output signal QBn at the bistable multivibrator SRn of n level becomes low level, the output signal QBn+2 of bistable multivibrator SRn+2 by the n+2 level becomes low level, is reset to till the high level.Here, the bistable multivibrator of n+1 level and n+2 is as the tseudo circuit of the timing of output signal QBn-1, the QBn of the bistable multivibrator of exporting reset n-1 level and n-2 level.

(the overlapping 31c of portion that prevents)

As Fig. 9 and shown in Figure 10, local overlapped period is arranged from (between low period) between (between high period) between the active period of precharge of each bistable multivibrator SR and the active period of sampling with output signal QB with output signal PO.Therefore, if former state is used output signal PO and the output signal QB of each bistable multivibrator SR, carry out the precharge and the sampling of each source bus line, then the wiring of video signal VIDEO and the wiring meeting that preparation charging potential PVID is provided are through the source bus line short circuit.

Therefore, in data-signal line drive 31, the overlapping 31c of portion that prevents is set, is used to prevent that the output signal PO of each bistable multivibrator SR and output signal QB from overlapping each other.

Overlapping prevent the 31c of portion possess delay (delay) circuit Pd (Pd1, Pd2 ..., Pdn) and buffer circuits Pb (Pb1, Pb2 ..., Pbn) (delay unit) and as remove superposing circuit (removing overlapping parts) or (NOR) circuit NOR (NOR1, NOR2 ..., NORn).

Figure 11 is the formation block diagram of expression delay circuit Pd.As shown in the figure, delay circuit Pd constitutes after inverter circuit inv is with input signal in counter-rotating, be branched off into two, a signal B former state is input to or circuit nor, another signal A is input to or circuit nor after by a plurality of inverter circuits that vertically connect in order to make signal delay.Shown in the timing diagram of Figure 12, the output signal out of delay circuit Pd remains unchanged at the negative edge (rear end) of the pulse of input signal in, in rising edge (front end) delay of pulse.

Be connected in relatively each bistable multivibrator SR1, SR2 among the shift register 31a ..., SRn terminals P O on each preparation charging with pulse PSMP (PSMP1, PSMP2 ..., PSMPn) output line each possess delay circuit Pd.Delay circuit Pd1, Pd2 ... output be followed successively by output signal DO1, DO2 ..., be input to each self-corresponding buffer circuits Pb1, Pb2 ...

Each buffer circuits Pb is the circuit of electric current amplification input signal, and is for example shown in Figure 13, is the impact damper that vertically connects a plurality of (being 4 in the figure) inverter circuit.Buffer circuits Pb1, Pb2 ... output be followed successively by output signal (preparation charging uses pulse) PSMP1, PSMP2 ..., be input to the 31b of sampling portion respectively.

In addition, the output signal PSMP of buffer circuits Pb (PSMP1, PSMP2 ..., PSMPn) also be input to respectively or circuit NOR1, NOR2 ..., NORn an input terminal.In addition, to each or circuit NOR1, NOR2 ..., NORn another input terminal respectively each bistable multivibrator SR1, the SR2 among input shift register 31a ..., SRn output signal QB1, QB2 ..., QBn.

Or circuit NOR1, NOR2 ..., NORn output be followed successively by output signal NOUT1, NOUT2 ..., NOUTn, be input to respectively corresponding buffer circuits Sb1, Sb2 ..., Sbn.In addition, buffer circuits Sb1, Sb2 ..., Sbn output successively as sampling with signal (timing pip) SMP1, SMP2 ..., SMPn, be input to the 31b of sampling portion.

Figure 14 is the overlapping timing diagram that prevents the 31c of portion.As shown in the figure, be delayed circuit Pd1 and buffer circuits Pb1 postpones, export as output signal PSMP1 from the output signal PO1 of the terminals P O among the 1st grade the bistable multivibrator SR1.

This output signal PSMP1 is input to the input terminal of NOR circuit NOR1.In addition, to another input terminal input of NOR circuit NOR1 output signal QB1 from the terminal QB among the 1st grade the bistable multivibrator SR1.Therefore, all become under the low level situation at the output signal PSMP1 of buffer circuits Pb1 and output signal QB1 from the terminal QB among the bistable multivibrator SR1, the output signal NOUT1 of NOR circuit NOR1 becomes high level, and under the situation in addition, output signal NOUT1 becomes low level.

Thus, from NOR circuit NOR1 output remove from the output signal QB of the 1st grade bistable multivibrator SR1, with the output signal NOUT1 of overlapping part (with reference to the oblique line portion of Figure 11) the back counter-rotating of the output signal PSMP1 of buffer circuits Pb1.

Afterwards, the output signal NOUT1 of this NOR circuit NOR1 is input to buffer circuits Sb1, after the delay,, outputs to the 31b of sampling portion as output signal SMP1.

Thus, as shown in figure 14, (between low period) used the lap of (between high period) between the active period among the signal PSMP1 between the active period among the output signal QB1 of the 1st grade bistable multivibrator SR1 by removal of NOR circuit and precharge (preparation charging), become (between low period) between non-active period, become after the signal NOUT1 after the counter-rotating again, be cushioned device circuit Sb1 again and postpone back output, become the signal SMP1 of sampling usefulness.Therefore, between the active period of the signal PSMP1 that uses of precharge and not overlapping between the active period of the signal SMP1 of sampling usefulness.

Each bistable multivibrator SR too, remove the signal PSMP that precharge uses (PSMP1, PSMP2 ...) active period between with the sampling usefulness signal SMP (SMP1, SMP2 ...) active period between lap.

Like this, remove superposing circuit (the overlapping portion that prevents) 31c between the active period of the output signal QB of each bistable multivibrator SR, remove with the preparation charging with the lap between the active period of pulse PSMP, generation is input to the timing pip SMP of the 31b of sampling portion.Thus, even if utilize the output of preparation charging with the synchronous bistable multivibrator of the rear end (negative edge) of pulse PSMP and the front end (rising edge) of timing pip SMP, it is overlapping with the front end of the rear end of pulse PSMP and timing pip SMP also can to prevent to prepare charging really.Therefore, can avoid really video signal VIDEO and preparation charging potential PVID data signal line SL (SL1, SL2 ..., SKn) state of affairs that goes up conflict takes place.

Therefore, become between active period (low level) afterwards at the output signal QBi of the bistable multivibrator SRi of i level (i is the integer of 1-n), the low level of the output signal QBi+2 of the bistable multivibrator SRi+2 of i+2 level is when being input to the RB terminal of bistable multivibrator SRi, be reset, become (high level) between non-active period.Therefore, as shown in figure 14, the front end of the output signal QBi+2 of bistable multivibrator SRi+2 (negative edge) is with the basic while of the rear end (rising edge) of the output signal QBi of bistable multivibrator SRi or have overlapped period slightly.

On the other hand, if the sampling of different data signal lines (source bus line) overlaps each other with signal (timing pip) SMP, then different data signal lines can be shared identical video signal VIDEO, produces the defective that also has noise in the picture.

On the contrary, data-signal line drive 31 utilize NOR circuit NOR to remove between the active period of output signal QB of each bistable multivibrator SR and precharge with the overlapping period between the active period of signal PSMP.Here, precharge is the signal that is postponed the output signal PO of each bistable multivibrator SR by delay circuit Pd and buffer circuits Pb with signal PSMP, this retardation (time delay) than between the active period of the output signal QBi of the bistable multivibrator SRi of i level and the overlapping period (overlapping time) between the active period of the output signal QBi+2 of the bistable multivibrator SRi+2 of i+2 level long.

Therefore, can remove really corresponding to the sampling of i data signal line SLi signal SMPi and the overlapping period of using signal SMPi+2 corresponding to the sampling of i+2 data signal line SLi+2.For example shown in Figure 14, use signal SMP1 and use between signal SMP3 active period each other not overlapping corresponding to the sampling of the 1st data signal line SL1 corresponding to the sampling of the 3rd data signal line SL3.Thus, also can avoid sampling with each other overlapping of signal (timing pip) SMP, so can prevent the reduction of image quality really.

(31b of sampling portion)

Figure 15 is the circuit diagram of the configuration example of the expression sampling 31b of portion.As shown in the figure, the 31b of sampling portion (write circuit, preparation charging circuit) possess by phase inverter IP (Ip1, Ip2 ..., IPn) and switch (the 2nd switch) SWp (SWp1, SWp2 ..., SWpn) constitute the preparation charging circuit, with by phase inverter Is (Is1, Is2 ..., Isn) and switch (the 2nd switch) SWs (SWs1, SWs2 ..., SWsn) write circuit that constitutes.

Switch SW s is by N-channel MOS transistor (TFT) that input signal is directly inputted to grid (the 1st control terminal) and analog switch that the P channel MOS transistor (TFT) of the signal behind inversion input signal input grid is constituted.

The sampling signal SMP of phase inverter Is counter-rotating input, Yi Bian make it to have the ability of the electric capacity that the grid of the P channel MOS transistor among the switch SW s that can fully discharge and recharge correspondence has, Yi Bian be input to grid.(thinking that phase inverter Is makes the counter-rotating of above-mentioned input signal and has an overlapping part that prevents the function of the buffer circuits Sb among the 31c of portion) is the above-mentioned overlapping output signal that prevents each the buffer circuits Sb among the 31c of portion as each sampling of the input signal of above-mentioned each switch SW s with signal SMP in addition.

The grid of each MOS transistor is capacitive control terminal, and each switch SW s is corresponding to the charging voltage of grid, switched conductive and non-conduction.Vision signal (write signal) VIDEO of the simulation that provides from the outside is provided respectively jointly to an end of the channel path of each switch SW s.

Switch SW p is the analog switch by the P channel MOS transistor formation of the input of the signal behind the N-channel MOS transistor that input signal is directly inputted to grid (the 2nd control terminal) and this input signal that will reverse grid.

The precharge signal PSMP of phase inverter Ip counter-rotating input, Yi Bian make it to have the ability of the electric capacity that the grid that can fully discharge and recharge the P channel MOS transistor has, Yi Bian be input to grid.(thinking that phase inverter Ip makes above-mentioned input signal counter-rotating and has an overlapping part that prevents the function of the buffer circuits Pb among the 31c of portion).In addition, each precharge as the input signal of above-mentioned each switch SW p is the above-mentioned overlapping output signal that prevents each the buffer circuits Pb among the 31c of portion with signal PSMP.

The grid of each MOS transistor is capacitive control terminal, and each switch SW p is corresponding to the charging voltage of grid, switched conductive and non-conduction.The preparation charging potential PVID that applies from the outside to the common input of an end of the channel path of each switch SW p.

In addition, the other end of the channel path of the other end of the channel path of each switch SW s and each switch SW p is connected in data signal line (signal the provides line) SL that is arranged in the display panels (SL1, SL2 ..., SLn) on.

Thus, become activation (high level) by precharge with signal PSMPi, switch SW pi conducting (below show as switch conduction or non-conduction) will prepare charging potential PVID and put on the data signal line SLi, the electric capacity of the pixel of preparation charging data signal line SLi and selection.Here, as mentioned above, precharge activate with signal PSMPi (high level) during in, sampling becomes non-activation with signal SMPi really by the overlapping 31c of portion that prevents.Therefore, switch SW si is non-conduction really, and preparation charging potential PVID does not conflict on data signal line SLi with video signal VIDEO.

In addition, if sampling becomes activation (high level), then switch SW si conducting with signal SMPi.Thus, SLi provides video signal VIDEO to data signal line, and data signal line SLi and pixel capacitance charges are arrived the voltage of stipulating.That is, carry out the sampling of video signal VIDEO, beginning afore mentioned rules each data signal line in the cycle becomes (writing during the actual effect) during the sampling actual effect between sampling period successively.At this moment, because precharge becomes non-activation really with signal PSMPi,, prepare charging potential PVID and on data signal line SLi, do not conflict with video signal VIDEO so that switch SW pi becomes is non-conduction.

Like this, repeat after the preparation charging of carrying out data signal line SLi, to provide the action of video signal VIDEO successively, sample by dot sequency to this data signal line SLi.Here, the per semiperiod at clock signal SCK, SCKB repeats between each sampling period of front and back.The pixel capacitance during at this moment, with the negative edge (rear end) of the timing pip between each sampling period and the charging potential of data signal line are determined the sampling current potential.

As mentioned above, data-signal line drive 31 uses the signal of own level among each bistable multivibrator Sri, carries out the preparation charging corresponding to the data signal line and the pixel capacitance of this grade.Therefore, different with conventional example, the initial stage of shift register needn't pseudo-level.Therefore, when can and twine the size in the wiring zone around it and dwindle panel physical dimension, increase the ratio of the relative panel physical dimension of display area size in the size of miniaturization data-signal line drive 31.

In addition, in the data-signal line drive 31, from output signal DO1, the DO2 of delay circuit Pd ... be used to electric current and amplify the preparation charging and postpone with the buffer circuits Pb of pulse, thus as final preparation charging with pulse, from the end between the active period of the output signal PSMP of buffer circuits Pb output and overlapping from the front end between the active period of the output signal QB of bistable multivibrator SR.Therefore, NOR circuit NOR1, NOR2 ... can remove really in the front end between the active period of timing pip SMP, and the preparation charging with the lap between the active period of pulse.

In addition, delay circuit Pd is arranged to reduce the delay of signal rear end as far as possible, but as long as signal by circuit, certainly leads to delay.Therefore, think except that the signal delay that buffer circuits Pb produces that the delay of the signal rear end that delay circuit Pd produces also assists in removing the preparation charging with each other overlapping of the overlapping and timing pip of pulse and timing pip.

The preparation charging of input NOR circuit NOR can not fully prevent under the timing pip SMP overlapping situation each other by the front end of removal timing pip SMP with respect to the retardation from the output signal PO of bistable multivibrator SR with pulse PSMP, also can append the inverter circuit that postpones usefulness before the delay circuit Pd or before the buffer circuits Pb, or append the delay inverter circuit to the output line that will be input to NOR circuit NOR from the output signal PSMP of buffer circuits Pb.

In addition, if preparation charging is overlapping, then big to showing influence with the rear end corresponding to the timing pip SMP of other data signal line with the front end of pulse PSMP or timing pip SMP.This is because the front end of these pulses means the conducting of switch SW p or SWs, when these switch SW p, SWs conducting, data signal line SL is not fully charging also, so in the conducting moment of switch SW p, SWs, with data signal line SL between have the electric capacity part or be connected part, cause big potential change.Therefore, above-mentioned delay circuit Pd prepares charging with the pulse PSMP overlapping function each other except that preventing, also has to prevent to prepare the charging front end of pulse PSMP and the overlapping function in rear end of timing pip SMP.

And, in data-signal line drive 31, since preparation charging with pulse PSMP make each bistable multivibrator SR1, SR2 ... output signal PO1, PO2 ... in active period between separately front end postpone, so the preparation charging does not overlap each other with pulse PSMP.Thus, can avoid really not supposing that the data signal line SL that charges simultaneously also is connected on the preparation charging potential PVID generation of the states of affairs such as driving force deficiency of preparation charge power supply.Therefore, according to above-mentioned formation, can prepare charging data signal line SL really in rule ground.

In addition, during the above-mentioned sampling actual effect be sampling after the data signal line SL of the 1st of beginning sampling, in final data signal wire SLn finish during.In addition, the output signal PO of each the bistable multivibrator SR that generates from the output signal QB (or counter-rotating amplifying signal SSPB ' of starting impulse SSP) of the prime bistable multivibrator SR of each bistable multivibrator SR, with output signal Q to the 31b of sampling portion output by delayed circuit Pd and buffer circuits Pb by self, the control terminal of the switch SW p of the charging sampling 31b of portion, the preparation charging that unsampled data signal line is carried out in this period is carried out in switch SW p conducting.

Promptly, in each bistable multivibrator SRi, between the output signal QB active period of prime bistable multivibrator SRi-1 (or starting impulse SSP be activation level during), the output signal Qi of self is under the situation between non-active period, the activation level of the output signal PO that output precharge is used.In addition, export the signal PO of this activation level to the 31b of sampling portion by delayed circuit Pd and buffer circuits Pb, can be by line order preparation charging data signal line SLi.

In addition, at this moment, because the system that sampling timing pulse SMP is provided separates with the system that the signal PSMP that carries out the preparation charging is provided, so the control signal circuit of the control signal circuit of common switch SWs and SWp not.Thus, can avoid following the big electric current that data signal line SL is flow through in the preparation charging current potential of the video signal VIDEO of the data signal line SL that is writing this moment to be shaken through the capacitive character control terminal of switch SW p.

(variation)

(variation of the 31b of sampling portion)

In addition, in the present embodiment, explanation to 1 group of precharge with signal PSMP and sampling with signal SMP (1 group prepare the output line of charging pulse and the output line of timing pip), possess the liquid crystal indicator of the formation of 1 data signal line (signal provides line), but be not limited thereto.

For example, also can constitute to 1 group of precharge with signal PSMP and the sampling possess the data signal line that corresponds respectively to R, G, B three looks with signal SMP.At this moment, as long as the 31b of sampling portion is replaced into as shown in figure 16 the 31b ' of sampling portion.

Configuration example when the 31b ' of sampling portion shown in Figure 16 (write circuit, preparation charging circuit) illustrates 1 group of precharge is used to correspond respectively to (for example being used for 3 pixels demonstrations), the no phase demodulation of charging of 3 data signal lines of R (red), G (green), B (indigo plant) with signal SMP with signal PSMP and sampling.

Sampling portion (write circuit, the preparation charging circuit) 31b ' possesses (Ip1 by phase inverter Ip, Ip2, Ipn), switch SW pr (SWpr1, SWpr2, SWprn), switch SW pg (SWpg1, SWpg2, SWpgn), switch SW pb (SWpb1, SWpb2, SWpbn) the preparation charging circuit of Gou Chenging, with by phase inverter Is (Is1, Is2, Isn), switch SW sr (SWsr1, SWsr2, SWsrn), switch SW sg (SWsg1, SWsg2, SWsgn), switch SW sb (SWsb1, SWsb2, SWsbn) write circuit of Gou Chenging.

Switch SW sr, switch SW sg, switch SW sb are by N-channel MOS transistor (TFT) that input signal is directly inputted to grid (the 1st control terminal) and analog switch that the P channel MOS transistor (TFT) of the signal behind inversion input signal input grid is constituted.

The sampling signal SMP of phase inverter Is counter-rotating input, on one side make it to have the ability of the electric capacity that the grid that can fully discharge and recharge corresponding each switch SW sr, SWsg, the P channel MOS transistor among the SWsb has, be input to grid on one side and (think that phase inverter Is reverses above-mentioned input signal and has an overlapping part that prevents the function of the buffer circuits Sb among the 31c of portion.)。In addition, the sampling as the input signal of above-mentioned each switch SW sr, SWsg, SWsb is the above-mentioned overlapping output signal that prevents the buffer circuits Sb among the 31c of portion with signal SMP.

The grid of each MOS transistor is capacitive control terminal, and each switch SW sr, SWsg, SWsb are corresponding to the charging voltage of grid, switched conductive and non-conduction.Vision signal (write signal) VIDEO (VIDEO (R), VIDEO (G), VIDEO (B)) of the simulation that provides from the outside is provided respectively to an end of the channel path of each switch SW sr, SWsg, SWsb.Promptly, to switch SW sr1, SWsr2 ..., SWsrn the common incoming video signal VIDEO of an end (R) of channel path, to switch SW sg1, SWsg2 ..., SWsgn the common incoming video signal VIDEO of an end (G) of channel path, to switch SW sb1, SWsb2 ..., SWsbn the common incoming video signal VIDEO of an end (B) of channel path.

Switch SW pr, switch SW pg, switch SW pb are the analog switches by the P channel MOS transistor formation of the input of the signal behind the N-channel MOS transistor that input signal is directly inputted to grid (the 2nd control terminal) and this input signal that will reverse grid.

The precharge signal PSMP of phase inverter Ip counter-rotating input, on one side make it to have the ability of the electric capacity that the grid that can fully discharge and recharge the P channel MOS transistor has, be input to grid on one side and (think that phase inverter Ip reverses above-mentioned input signal and has an overlapping part that prevents the function of the buffer circuits Pb among the 31c of portion.)。In addition, the precharge as the input signal of above-mentioned each switch SW pr, SWpg, SWpb is the above-mentioned overlapping output signal that prevents the buffer circuits Pb among the 31c of portion with signal PSMP.

The grid of each MOS transistor is capacitive control terminal, and each switch SW pr, SWpg, SWpb are corresponding to the charging voltage of grid, switched conductive and non-conduction.The preparation charging potential PVID that applies from the outside to the common input of an end of the channel path of each switch SW pr, SWpg, SWpb.

In addition, with each switch SW pr (SWpr1, SWpr2 ..., SWprn) the other end of channel path and each switch SW sr (SWsr1, SWsr2 ..., SWsrn) the other end of channel path be connected to data signal line (signal the provides line) SLr that is arranged in the display panels (SLr1, SLr2 ..., SLrn) on.Equally, with each switch SW pg (SWpg1, SWpg2 ..., SWpgn) the other end of channel path and each switch SW sg (SWsg1, SWsg2 ..., SWsgn) the other end of channel path be connected to data signal line (signal the provides line) SLg that is arranged in the display panels (SLg1, SLg2 ..., SLgn) on.In addition, with each switch SW pb (SWpb1, SWpb2 ..., SWpbn) the other end of channel path and each switch SW sb (SWsb1, SWsb2 ..., SWsbn) the other end of channel path be connected to data signal line (signal the provides line) SLb that is arranged in the display panels (SLb1, SLb2 ..., SLbn) on.

Thus, become activation (high level) by precharge with signal PSMPi, switch SW pri, SWpgi, SWpbi conducting will prepare charging potential PVID and put on data signal line SLri, SLgi, the SLbi, the electric capacity of the pixel of preparation charging data signal line SLri, SLgi, SLbi and selection.Here, as mentioned above, precharge activate with signal PSMPi (high level) during in, sampling becomes non-activation with signal SMPi really by the overlapping 31c of portion that prevents.Therefore, switch SW sri, SWsgi, SWsbi are non-conduction really, and preparation charging potential PVID does not conflict on data signal line SLri, SLgi, SLbi with video signal VIDEO.

In addition, if sampling becomes activation (high level) with signal SMPi, then switch SW sri, SWsgi, SWsbi conducting.Thus, on data signal line SLri, SLgi, SLbi, provide video signal VIDEO (VIDEO (R), VIDEO (G), VIDEO (B)), with data signal line SLri, SLgi, SLbi and each pixel capacitance charges voltage to regulation.That is, carry out the sampling of video signal VIDEO, beginning afore mentioned rules each data signal line in the cycle becomes (writing during the actual effect) during the sampling actual effect between sampling period successively.At this moment, because precharge becomes non-activation really with signal PSMPi,, prepare charging potential PVID and on data signal line SLri, SLgi, SLbi, do not conflict with video signal VIDEO so that switch SW pi becomes is non-conduction.

Like this, repeat after the preparation charging of carrying out data signal line SLri, SLgi, SLbi, to provide the action of video signal VIDEO successively, sample by dot sequency to this each data signal line.

Like this, 1 group of precharge is being possessed in the formation of the data signal line that corresponds respectively to R, G, B three looks with signal SMP with signal PSMP and sampling, around each vision signal wiring winding shift register 31a of R, G, B.Therefore, in the data-signal line drive 31 of present embodiment, owing to do not need tseudo circuit, so can effectively dwindle panel physical dimension.

In addition, for example also can constitute the phase that three looks that possess a plurality of R, G, B constitute, to 1 group of precharge with signal PSMP with sample and possess the data signal line of the video signal cable of all kinds in corresponding respectively to respectively mutually with signal SMP.At this moment, as long as the 31b of sampling portion is replaced into as shown in figure 17 the 31b of sampling portion ".

The 31b of sampling portion shown in Figure 17 (write circuit, preparation charging circuit) " illustrate and possess 2 phases that constitute by R (red), G (green), B (indigo plant), the configuration example when 1 group of precharge being used for altogether 6 (for example being used for amounting to the demonstration of 6 pixels), the no phase demodulation of charging of data signal line with signal SMP with signal PSMP and sampling.

Sampling portion (write circuit, the preparation charging circuit) 31b " and possess by phase inverter Ip (Ip1; Ip2; ...; Ipn); switch SW pra (SWpra1, SWpra2, SWpran), switch SW prb (SWprb1, SWprb2, SWprbn), switch SW pga (SWpga1, SWpga2, SWpgan), switch SW pgb (SWpgb1, SWpgb2, SWpgbn), switch SW pba (SWpba1, SWpba2, SWpban), switch SW pbb (SWpbb1, SWpbb2, SWpbbn) the preparation charging circuit of Gou Chenging, with by phase inverter Is (Is1, Is2, Isn), switch SW sra (SWsra1, SWsra2, SWsran), switch SW srb (SWsrb1, SWsrb2, SWsrbn), switch SW sga (SWsga1, SWsga2, SWsgan), switch SW sgb (SWsgb1, SWsgb2, SWsgbn), switch SW sba (SWsba1, SWsba2, SWsban), switch SW sbb (SWsbb1, SWsbb2, SWsbbn) write circuit of Gou Chenging.

Switch SW sra, SWsrb, SWsga, SWsgb, SWsba, SWsbb are by N-channel MOS transistor (TFT) that input signal is directly inputted to grid (the 1st control terminal) and analog switch that the P channel MOS transistor (TFT) of the signal behind inversion input signal input grid is constituted.

The sampling signal SMP of phase inverter Is counter-rotating input, on one side make it to have the ability of the electric capacity that the grid that can fully discharge and recharge the P channel MOS transistor among corresponding each switch SW sra, SWsrb, SWsga, SWsgb, SWsba, the SWsbb has, be input to grid on one side and (think that phase inverter Is reverses above-mentioned input signal and has an overlapping part that prevents the function of the buffer circuits Sb among the 31c of portion.)。In addition, the sampling as the input signal of above-mentioned each switch SW sra, SWsrb, SWsga, SWsgb, SWsba, SWsbb is the above-mentioned overlapping output signal that prevents the buffer circuits Sb among the 31c of portion with signal SMP.

The grid of each MOS transistor is capacitive control terminal, and each switch SW sra, SWsrb, SWsga, SWsgb, SWsba, SWsbb are corresponding to the charging voltage of grid, switched conductive and non-conduction.Vision signal (write signal) VIDEO (VIDEO (Ra), VIDEO (Rb), VIDEO (Ga), VIDEO (Gb), VIDEO (Ba), VIDEO (Bb)) of the simulation that provides from the outside is provided respectively to an end of the channel path of each switch SW sra, SWsrb, SWsga, SWsgb, SWsba, SWsbb.That is, to the common incoming video signal VIDEO of an end (Ra) of the channel path of switch SW sra, to the common incoming video signal VIDEO of an end (Rb) of the channel path of switch SW srb.In addition, to the common incoming video signal VIDEO of an end (Ga) of the channel path of switch SW sga, to the common incoming video signal VIDEO of an end (Gb) of the channel path of switch SW sgb.In addition, to the common incoming video signal VIDEO of an end (Ba) of the channel path of switch SW sba, to the common incoming video signal VIDEO of an end (Bb) of the channel path of switch SW sbb.

Switch SW pra, SWprb, switch SW pga, switch SW pgb, switch SW pba, switch SW pbb are by N-channel MOS transistor that input signal is directly inputted to grid (the 2nd control terminal) and analog switch that the P channel MOS transistor of the signal behind inversion input signal input grid is constituted.

The precharge signal PSMP of phase inverter Ip counter-rotating input, on one side make it to have the ability of the electric capacity that the grid that can fully discharge and recharge the P channel MOS transistor has, be input to grid on one side and (think that phase inverter Ip reverses above-mentioned input signal and has an overlapping part that prevents the function of the buffer circuits Pb among the 31c of portion.)。In addition, the precharge as the input signal of above-mentioned each switch SW pra, SWprb, SWpga, SWpgb, SWpba, SWpbb is the above-mentioned overlapping output signal that prevents the buffer circuits Pb among the 31c of portion with signal PSMP.

The grid of each MOS transistor is capacitive control terminal, and each switch SW pra, SWprb, SWpga, SWpgb, SWpba, SWpbb are corresponding to the charging voltage of grid, switched conductive and non-conduction.The preparation charging potential PVID that applies from the outside to the common input of an end of the channel path of each switch SW pra, SWprb, SWpga, SWpgb, SWpba, SWpbb.

In addition, with each switch SW pra (SWpra1, SWpra2 ..., SWpran) the other end of channel path and each switch SW sra (SWsra1, SWsra2 ..., SWsran) the other end of channel path be connected to data signal line (signal the provides line) SLra that is arranged in the display panels (SLra1, SLra2 ..., SLran) on.Equally, with each switch SW prb (SWprb1, SWprb2 ..., SWprbn) the other end of channel path and each switch SW srb (SWsrb1, SWsrb2 ..., SWsrbn) the other end of channel path be connected to data signal line (signal the provides line) SLrb that is arranged in the display panels (SLrb1, SLrb2 ..., SLrbn) on.

In addition, with each switch SW pga (SWpga1, SWpga2 ..., SWpgan) the other end of channel path and each switch SW sga (SWsga1, SWsga2 ..., SWsgan) the other end of channel path be connected to data signal line (signal the provides line) SLga that is arranged in the display panels (SLga1, SLga2 ..., SLgan) on.In addition, with each switch SW pgb (SWpgb1, SWpgb2 ..., SWpgbn) the other end of channel path and each switch SW sgb (SWsgb1, SWsgb2 ..., SWsgbn) the other end of channel path be connected to data signal line (signal the provides line) SLgb that is arranged in the display panels (SLgb1, SLgb2 ..., SLgbn) on.

In addition, with each switch SW pba (SWpba1, SWpba2 ..., SWpban) the other end of channel path and each switch SW sba (SWsba1, SWsba2 ..., SWsban) the other end of channel path be connected to data signal line (signal the provides line) SLba that is arranged in the display panels (SLba1, SLba2 ..., SLban) on.In addition, with each switch SW ppb (SWppb1, SWppb2 ..., SWppbn) the other end of channel path and each switch SW sbb (SWsbb1, SWsbb2 ..., SWsbbn) the other end of channel path be connected to data signal line (signal the provides line) SLbb that is arranged in the display panels (SLbb1, SLbb2 ..., SLbbn) on.

Thus, become activation (high level) by precharge with signal PSMPi, switch SW prai, SWprbi, SWpgai, SWpgbi, SWpbai, SWpbbi conducting, to prepare charging potential PVID and put on data signal line SLrai, SLrbi, SLgai, SLgbi, SLbai, the SLbbi, the electric capacity of the pixel of preparation charging data signal line SLrai, SLrbi, SLgai, SLgbi, SLbai, SLbbi and selection.

Here, as mentioned above, precharge activate with signal PSMPi (high level) during in, sampling becomes non-activation with signal SMPi really by the overlapping 31c of portion that prevents.Therefore, switch SW srai, SWsrbi, SWsgai, SWsgbi, SWsbai, SWsbbi are non-conduction really, and preparation charging potential PVID does not conflict on data signal line SLrai, SLrbi, SLgai, SLgbi, SLbai, SLbbi with video signal VIDEO.

In addition, if sampling becomes activation (high level) with signal SMPi, then switch SW srai, SWsrbi, SWsgai, SWsgbi, SWsbai, SWsbbi conducting.Thus, on data signal line SLrai, SLrbi, SLgai, SLgbi, SLbai, SLbbi, provide video signal VIDEO (VIDEO (Ra), VIDEO (Rb), VIDEO (Ga), VIDEO (Gb), VIDEO (Ba), VIDEO (Bb)), with data signal line SLrai, SLrbi, SLgai, SLgbi, SLbai, SLbbi and each pixel capacitance charges voltage to regulation.That is, carry out the sampling of video signal VIDEO, beginning afore mentioned rules each data signal line in the cycle becomes (writing during the actual effect) during the sampling actual effect between sampling period successively.At this moment, because precharge becomes non-activation really with signal PSMPi,, prepare charging potential PVID and on data signal line SLrai, SLrbi, SLgai, SLgbi, SLbai, SLbbi, do not conflict with video signal VIDEO so that switch SW pi becomes is non-conduction.

Like this, repeat after the preparation charging of carrying out data signal line SLrai, SLrbi, SLgai, SLgbi, SLbai, SLbbi, to provide the action of video signal VIDEO successively, sample by dot sequency to this each data signal line.

Like this, under the situation of the formation of heterogeneous expansion vision signal, with more vision signal wiring be wrapped in shift register 31a around.Therefore, in the data-signal line drive 31 of present embodiment, needn't tseudo circuit, with regard to the formation of heterogeneous expansion vision signal, can especially effectively dwindle panel physical dimension.

(variation 1 of bistable multivibrator SR)

In the present embodiment, illustrate that shift register 31a is made of the multistage restoration type bistable multivibrator SR that is provided with, but be not limited thereto.

For example, also can use the gating circuit of record in shown in Figure 180, the patent documentation 8 and the shift register piece SRB that bistable multivibrator constitutes (SRB1, SRB2 ..., SRBn+2), replace above-mentioned bistable multivibrator SR (SR1, SR2 ..., SRn+2).Among Figure 18, for convenience, the formation of the bistable multivibrator in the change patent documentation 8.

As shown in the figure, shift register piece SRB is made of control circuit CN, gating circuit GC, bistable multivibrator F, phase inverter I50.In addition, shift register piece SRB is the same with bistable multivibrator SR, possess CK terminal, CKB terminal, CINB terminal, RB terminal, PO terminal, with the QB terminal.To above-mentioned each terminal input and output signal the same with bistable multivibrator SR.

The formation of control circuit CN is the same with above-mentioned level shifter control circuit CN.The input terminal IN1 of control circuit CN is connected on the CINB terminal, and the input terminal IN2 of control circuit CN is connected on the Q terminal.Thus, import the output signal Q of bistable multivibrator F to input terminal IN2.In addition, the lead-out terminal CNOUT of control circuit CN is connected on the input terminal of PO terminal and phase inverter I50.

Gating circuit GC possesses transistor P51, N50, N51, N52.Bistable multivibrator F possesses transistor P52, P53, P54, N53, N54.Transistor P51-P54 is the P channel type MOS transistor, and transistor N50-N54 is the N channel type MOS transistor.

Transistor P51 and N51 are connected in series between power vd D and the clock input terminal CK.Transistor N50 is connected between the tie point and power supply VSS of transistor P51 and N51.The grid of transistor P51, N50 is connected on the lead-out terminal of phase inverter I50.Thus, provide enable signal ENAB to the grid of transistor P51, N50 as the signal after the output signal (output signal PO) of reverse turn control circuit CN.The grid of transistor P51 activates for low.

Transistor P52 and N52 are connected in series between power vd D and the clock input terminal CKB, and its tie point constitutes the lead-out terminal of gating circuit GC.The grid of transistor N52 is connected on the grid of transistor N52, and these grids are connected in the drain electrode of transistor N51.The grid of transistor P52 is low the activation, provides to the input signal of RB terminal.

Transistor P53 and N53 are connected in series between power vd D and the power supply VSS.Transistor P54 and N54 are connected in series between power vd D and the power supply VSS.The grid of the grid of transistor P53 and transistor N53 is connected to each other, and its tie point is connected on the tie point of transistor P54 and N54.The grid of the grid of transistor P54 and transistor N54 is connected to each other, and its tie point is connected on the lead-out terminal of the tie point of transistor P53 and N53 and gating circuit GC, simultaneously, constitutes the sub-QB of inversion output terminal of bistable multivibrator F.What the tie point of transistor P54 and N54 constituted bistable multivibrator F just transfers out terminal Q.

Below, the action of the shift register piece SR of above-mentioned formation is described with timing diagram shown in Figure 19.Figure 19 represents among the 1st grade-n+2 level shift register piece SRB, each signal waveform of the shift register piece SRB of odd level.With regard to the shift register piece SRB of even level, 1 clock (semiperiod) of each signal waveform dislocation clock signal SCK, SCKB.That is, the clock signal SCK among Figure 19 is converted to its reverse signal SCKB.

When input signal CINB is high level, because the signal Q that just transfers out of bistable multivibrator F becomes nonactivated low level in advance, so the output signal of control circuit CN (output signal PO) becomes low level.This low level signal is become the signal of high level by after the phase inverter I50 counter-rotating, and as enable signal ENAB, what be input to gating circuit GC enables terminal ENAB.

Gating circuit GC is between low period at enable signal ENAB, is movable state.Under movable state, level shift clock signal SCK outputs to bistable multivibrator F.

If input signal CINB becomes low level, then because the end signal Q that just transfers out of bistable multivibrator F becomes nonactivated low level in advance, so the output signal of control circuit CN (output signal PO) becomes high level.Therefore, through the signal that enable terminal ENAB input low level of phase inverter I50 to gating circuit GC.

To the initial moment of the signal that enables terminal ENAB input low level, because clock signal SCK is a low level, clock signal SCKB is a high level, so the counter-rotating output signal QB of bistable multivibrator F still is a high level.

Afterwards, after the length of the pulse of clock signal SCK (after 1/2 cycle of clock signal SCK), clock signal SCK becomes high level, clock signal SCKB becomes low level, so the output signal Q of bistable multivibrator F becomes high level, counter-rotating output signal QB becomes low level.

Owing to the input terminal IN1 that output signal Q is input to control circuit CN, so the timing after the timing that becomes high level from output signal Q is through the time delay of control circuit CN, the output signal of control circuit CN (output signal PO) becomes low level.In addition, the enable signal ENAB of input gating circuit GC becomes high level.

If to the signal that enables terminal ENAB input high level of gating circuit GC, then gating circuit GC becomes non-action status.

If gating circuit GC becomes non-action status, then its output signal becomes low level, (output signal Q is a high level but the output signal Q of bistable multivibrator F and counter-rotating output signal QB keep activation level, counter-rotating output signal QB1 is a low level), up to till the signal of reseting terminal RB input low level.Afterwards, these output signals Q and counter-rotating output signal QB become low level timing at the signal that is input to reseting terminal RB, become non-activation (output signal Q is a low level, and counter-rotating output signal QB is a high level).In addition, the counter-rotating output signal QB of the bistable multivibrator F that possesses among the shift register piece SR after reseting terminal RB imports 2 grades.

Like this, even if use the formation of shift register piece SRB, much the same output signal PO, Q, QB in the time of also can obtaining and use bistable multivibrator SR.Much the same action when therefore, data-signal line drive 31 is with use bistable multivibrator SR.

Even if under the situation of using shift register piece SRB, in the prior art, in order to generate the precharge signal, the output signal of the shift register piece before also must having more than 2 grades or more than 1 grade before the output signal and the starting impulse SSP of shift register piece.Therefore, the data signal line for the 1st of precharge or the 1st, 2 must be provided with tseudo circuit (pseudo-shift register piece).

On the contrary, according to above-mentioned formation, because each shift register piece SRB uses the output signal of self to generate the signal PO that precharge is used, so needn't this tseudo circuit.Therefore, when can and twine the size in the wiring zone around it and dwindle panel physical dimension, increase the ratio of the relative panel physical dimension of size of viewing area in the size of miniaturization data-signal line drive 31.

In addition, under the little situation of the amplitude of the amplitude ratio supply voltage of the clock signal SCK that is input to gating circuit GC, SCKB, produce the electric current that gating circuit GC is crossed in steady flow.If find the enable signal ENAB of Figure 19, then as can be known during the action of gating circuit GC (between the low period of enable signal ENAB) become about 1 pulse length (about 1/2 cycle of clock signal SCK) of clock signal SCK.Determine that this enable signal ENAB becomes and state time delay on the nonactivated timing mainly based on the time delay in the control circuit CN.Under existing situation about constituting, during the input signal CINB activation (about 2 pulse lengths of clock signal SCK (about 1 cycle of clock signal SCK)), produce the electric current of steady flow, but in the case of this example, can cut down the electric current that gating circuit GC is crossed in steady flow.

The time delay that signal Processing is arranged among gating circuit GC or bistable multivibrator F, the control circuit CN in addition.Gating circuit GC exports behind the signal of clock signal SCK, the SCKB of the input of deferred telegram translational shifting slightly, but after gating circuit GC output signal, when behind delay output signal Q slightly, exporting, the output signal of output counter-rotating forthwith QB, regularly postpone slightly from the output of counter-rotating output signal QB, the output signal PO to the PO terminal as the output signal of control circuit CN becomes low level, and enable signal ENAB becomes high level.Therefore, after gating circuit GC output signal, becoming time delay before the high level as enable signal ENAB, mainly is the time delay of control circuit CN.

According to if become state that the pulse of the output signal Q of bistable multivibrator F can guarantee, then needn't gating circuit GC action in addition basic consideration, if beginning slightly in the pulse from counter-rotating output signal QB, the moment in elapsed time becomes non-activation with enable signal ENAB, then after becoming the state that the pulse that obtains output signal Q begins, the action of gating circuit GC is stopped really.For this reason, as long as control circuit CN obtains time delay.

In addition, do not postpone till the output counter-rotating output signal QB, so as long as the condition that control circuit CN obtains getting final product time delay also is suitable for being made as actuation time with gating circuit GC minimal consideration from gating circuit GC output signal to bistable multivibrator F.

In addition, because output signal QB becomes the input signal CINB of next shift register piece SRB, so described retardation causes the enable signal ENAB among next shift register piece SRB to become the delay of the timing of activation, the pulse width of enable signal ENAB is about 1 pulse length (about 1/2 cycle of clock signal SCK).

(variation 2 of bistable multivibrator SR)

In addition, also can use bistable multivibrator SR_100 (SR_100 shown in Figure 32 ₁, SR_100 ₂..., SR_100 _N+2), replace bistable multivibrator SR shown in Figure 4 (SR1, SR2 ..., SRn+2).Figure 32 is the formation block diagram of each bistable multivibrator SR_100 of expression.As shown in the figure, each bistable multivibrator SR possesses level shifter control circuit CN_100, level shifter LS_100, restoration type bistable multivibrator SR-FF, phase inverter I1, phase inverter I2, phase inverter I3 is set.In addition, the formation of bistable multivibrator SR-FF is with shown in Figure 4 the same.

(level shifter control circuit CN_100)

Figure 33 is the formation block diagram of expression level shifter control circuit (control circuit) CN_100.As shown in the figure, level shifter control circuit CN_100 possesses two input terminal IN1, IN2, phase inverter I _CN, switch SW _CN, P channel MOS transistor (TFT) P _CN2, lead-out terminal CNOUTB.Switch SW _CNBe by N-channel MOS transistor (TFT) N _CNWith P channel MOS transistor (TFT) P _CN1The analog switch that constitutes.

Output signal Q to input terminal IN1 input bistable multivibrator SR-FF.Input to the input signal of the CINB terminal among each bistable multivibrator SR_100 to input terminal IN2.

Input terminal IN1 is connected in P channel MOS transistor P _CN1Grid on.In addition, input terminal IN1 is also through phase inverter I _CNBe connected in N-channel MOS transistor N _CNGrid and P channel MOS transistor P _CN2Grid on.

Input terminal IN2 is connected in P channel MOS transistor P _CN1Source electrode and N-channel MOS transistor N _CNSource electrode on.In addition, P channel MOS transistor P _CN1Drain electrode and N-channel MOS transistor N _CNDrain electrode be connected on the lead-out terminal CNOUTB.

In addition, P channel MOS transistor P _CN2Source electrode be connected on the power lead of driving voltage of high level Vdd, drain electrode is connected on the lead-out terminal CNOUTB.

Thus, to the input signal (being the output signal Q of bistable multivibrator SR-FF) of input terminal IN1 and at least one side of the input signal of input terminal IN2 (i.e. the input signal of the CINB terminal to each bistable multivibrator SR_100) be under the situation of high level, become high level from the output signal CNOB100 of lead-out terminal CNOUTB.In addition, be under the low level situation, becoming low level from the output signal CNOB100 of lead-out terminal CNOUTB to the input signal of input terminal IN1 with to the input signal of input terminal IN2.

Shown in figure 32, be input to the ENAB terminal of level shifter LS_100 from the output signal CNOB100 former state of lead-out terminal CNOUTB, and, after by phase inverter I3 counter-rotating, output to the PO terminal of each bistable multivibrator SR_100.

(level shifter LS_100)

Figure 34 is the block diagram of the configuration example of expression level shifter LS_100.This level shifter LS_100 possess haply level shift clock signal SCK, SCKB voltage raising and reducing portion 121, block power supply control part 122 at the stopping period that clock signal SCK, SCKB needn't be provided to the power supply of voltage raising and reducing portion 121, in stopping period, block voltage raising and reducing portion 121 and the signal wire of transmission clock signal SCK, SCKB input control part 123,124, in stopping period, block the input conversion element (N of voltage raising and reducing portion 121 _LS2, N _LS3) input signal control part 125,126; With the output stabilizers 127 that in stopping period, the output of voltage raising and reducing portion 121 is maintained setting.

Voltage raising and reducing portion 121 is that the differential input of input stage is right, constitute possess constitute above-mentioned input conversion element, source electrode N type connected to one another MOS transistor N _LS2, N _LS3Be connected in two transistor N _LS2, N _LS3Constant current source Ic between the power lead of the driving voltage of middle source electrode and low level Vssd; Constitute current mirroring circuit, be connected to transistor N _LS2, N _LS3Drain electrode on constitute can dynamic load P type MOS transistor P _LS3, P _LS4The transistor P of the CMOS structure of right output with amplifying differential input _LS7, P _LS5The formation of Figure 34 illustrates from output LSOUT and is just transferring out transistor N _LS3The odd number bistable multivibrator SR_100 of the input CK of side ₁, SR_100 ₃In the example of the level shifter LS1 that possesses.At even number bistable multivibrator SR_100 ₂, SR_100 ₄In under the situation of the level shifter LS_100 that possesses, the input of switching clock signal SCK, SCKB mutually.

Through constituting the P type MOS transistor P of described input control part 124 _LS1, to transistor N _LS2Grid input clock signal SCKB, through constituting the P type MOS transistor P of described input control part 123 _LS6, to transistor N _LS3Grid input clock signal SCK.In addition, through constituting the N type MOS transistor N of described input signal control part 126 _LS1, with transistor N _LS2Grid pull down to the power lead of the driving voltage of low level Vssd, same, through constituting the N type MOS transistor N of described input signal control part 125 _LS4, with transistor N _LS3Grid pull down to the power lead of the driving voltage of low level Vssd.In addition, to described transistor P _LS1, P _LS6, N _LS1, N _LS4Grid provide be input to the ENAB terminal, from the output signal CNOB100 (enable signal ENAB100) of level shifter control circuit CN_100.

Therefore, the low level as if become activation from the output signal CNOB100 of level shifter control circuit CN_100 then allows through described transistor P _LS1, P _LS6To transistor N _LS2, N _LS3Input clock signal SCKB, SCK, simultaneously, transistor N _LS1, N _LS4End.On the contrary, become nonactivated high level, then described transistor P as if output signal CNOB100 from level shifter control circuit CN_100 _LS1, P _LS6End, stop input clock signal SCKB, SCK, simultaneously, transistor N _LS1, N _LS4Conducting is with transistor N _LS2, N _LS3Grid pull down to low level Vssd, this transistor N of input stage _LS2, N _LS3Really disconnect.

On the other hand, described transistor P _LS3, P _LS4Grid be connected to each other, simultaneously, be connected in transistor P _LS3With transistor N _LS2Drain electrode on.On the contrary, transistor P connected to one another _LS4With transistor N _LS3Drain electrode constitute output terminal, be connected in described transistor P _LS7, N _LS5Grid on.Transistor P _LS3, P _LS4Source electrode through constituting the P type MOS transistor P of described power supply control part 122 _LS2, be connected on the power lead of driving voltage of high level Vdd.To MOS transistor P _LS2Grid output signal CNOB100 from level shifter control circuit CN_100 is provided.

Therefore, as if the low level that becomes activation from the output signal CNOB100 of level shifter control circuit CN_100, then through transistor P _LS2To 121 power supplies of voltage raising and reducing portion,, then prevent 121 power supplies to voltage raising and reducing portion if the output signal CNOB100 of level shifter control circuit CN_100 becomes nonactivated high level.

In addition, output stabilizers 127 is to make the output signal LSOUT of this level shifter LS_100 in the stopping period be stabilized in the circuit of the drive voltage level of low level Vssd, by phase inverter I _LSWith P type MOS transistor P _LS5Constitute.Phase inverter I _LSBe provided to ENAB terminal and transistor P _LS5Grid between.Therefore, the output signal CNOB100 of level shifter control circuit CN_100 is by phase inverter I _LSAfter the counter-rotating, offer transistor P _LS5Grid.Thus, when the output signal CNOB100 of level shifter control circuit CN_100 is high level, MOS transistor P _LS5With transistor P _LS7, N _LS5Grid on draw on the power lead of the driving voltage that is connected to high level Vdd.

In the level shifter LS_100 of above-mentioned formation, be under the low level situation in the output signal of level shifter control circuit CN_100, transistor P _LS1, P _LS2, P _LS6Conducting, transistor N _LS1, N _LS4, N _LS5End.Under this state, through transistor P _LS2The electric current that provides passes through P _LS3And N _LS2, or P _LS4And N _LS3, flow out through constant current source Ic.In addition, to two transistor N _LS3, N _LS2Grid apply clock signal SCK, SCKB respectively.As a result, at two transistor N _LS3, N _LS2Grid flow through size corresponding to the electric current of voltage ratio between gate-to-source separately.On the other hand, transistor P _LS3, P _LS4As the energy dynamic load, so transistor P _LS4, N _LS3The voltage of tie point be voltage corresponding to the voltage level difference of described clock signal SCK, SCKB.This voltage is by transistor P _LS7, N _LS5After the power amplification, export from lead-out terminal LSOUT as output signal LSO100.

The transistor P of input stage is switched with utilizing clock signal SCK, SCKB in described voltage raising and reducing portion 21 _LS3, P _LS4Conduction and cut-off formation, be the voltage driven type difference, be in action, the transistor P of input stage _LS4, P _LS3The current drive-type of conducting all the time, as mentioned above, by corresponding to two transistor P _LS4, P _LS3The ratio of gate source voltage across poles, even if the shunting steady current is at the transistor N of the amplitude ratio input stage of described clock signal SCK, SCKB _LS3, N _LS2The also low situation of threshold value under, can not have any obstacle ground level shift clock signal SCK, SCKB yet.

The result, if level shifter LS_100 is to apply the high level of activation to the ENAB terminal from the output signal CNOB100 of level shifter control circuit CN_100, even if then output is under the high side of the amplitude ratio driving voltage of clock signal SCK, SCKB and poor (Vcc=Vdd-Vssd is for example about the 15V) of downside low situation (for example about the 5V from the generative circuit of described image signal), also can be with the amplitude voltage raising and reducing output signal LSO100 of described poor Vcc extremely.

On the contrary, under the output signal CNOB100 from level shifter control circuit CN_100 represents to move the situation of the nonactivated high level that stops, through transistor P _LS3, N _LS2Or transistor P _LS4, N _LS3The electric current that flows through is by transistor P _LS2End.Therefore, can cut down the power consumption that this electric current causes.

Under this state, by the transistor P of each input control part 123,124 _LS6, P _LS1Therefore, cut off the signal wire of transmission clock signal SCK, SCKB and each transistor N of input stage _LS2, N _LS3Grid.In addition, since in stopping the transistor N of each input signal control part 125,126 _LS4, N _LS1So conducting is described two transistor N _LS2, N _LS3Grid voltage all pulled down to low level driving voltage Vssd, two transistor N _LS2, N _LS3End.Thus, with "off" transistor P _LS2Situation the same, can reduce power consumption corresponding to the electric current of constant current source Ic output.

But, under this state, because not to two transistor N _LS2, N _LS3Provide electric current, so two transistor N _LS2, N _LS3Can not output terminal, be transistor P as differential input to action _LS4, N _LS3The current potential of drain electrode tie point each other can not determine.Therefore, under described enable signal ENAB represented to move situation about stopping, further the transistor P of stabilizers 127 was exported in conducting _LS5As a result, described output terminal, be transistor P _LS7, N _LS5Grid potential by on move the driving voltage Vdd of high level, transistor N to _LS5Conducting, output signal LSO100 becomes low level.

The output signal CNOB100 from level shifter control circuit CN_100 represent to move stop during in, the output signal LSO100 of level shifter LS_100 all is held in low level regardless of clock signal SCK, SCKB.

(action of bistable multivibrator SR_100)

Figure 35 is the bistable multivibrator SR_100 of odd level ₁, SR_100 ₃Timing diagram.Bistable multivibrator SR_100 with regard to even level ₂, SR_100 ₄, each the signal relative time clock signal SCK among Figure 35 moved after the dislocation semiperiod.That is the bistable multivibrator SR_100 of even level, ₂, SR_100 ₄As shown in Figure 1, to CK terminal input counter-rotating clock signal (clock signal) SCKB, to CBK terminal input just commentaries on classics clock signal (clock signal) SCK.Therefore, the action of 1 clock (semiperiod) of the bistable multivibrator of execution and odd level dislocation clock signal.

As shown in figure 35, when the signal CINB of incoming level shift unit control circuit CN_100 is low (Low) level, this moment same stages bistable multivibrator SR_100 in the output Q of bistable multivibrator SR-FF export nonactivated low level.Therefore, the output signal CNOB100 of level shifter control circuit CN_100 becomes high level.

This low level signal CNOB100 is input to the ENAB terminal of level shifter LS_100.In addition, if level shifter LS_100 then becomes the state that can carry out the level shifter action to ENAB terminal input low level, and the signal of output level displacement input signal SCK is as output signal LSO100.Like this, the rising edge of the negative edge level shift clock signal SCK of the output signal CNOB of level shifter control circuit CN_100 is exported as output signal LSO100.

Here, (the output signal CNO of level shifter control circuit CN_100) becomes the low level moment at the signal that is input to the ENAB terminal, because clock signal SCK is a low level, so the output signal LSO100 of level shifter LS_100 still is a low level.In addition, if clock signal SCK (after about semiperiod of clock signal SCK) after about 1 clock becomes high level, then the output signal LSO100 of level shifter LS_100 switches to high level.

The output signal LSO100 of the level shifter LS_100 of this high level becomes low level by phase inverter I1, is input to the input terminal SB of bistable multivibrator SR-FF.

If to the input terminal SB of bistable multivibrator SR-FF input low level, SR-FF then is set, become activation, the output signal Q of bistable multivibrator SR-FF becomes high level, and output signal QB becomes low level.

Here, because level shifter control circuit CN_100 is arrived in the output signal Q input (feedback) of bistable multivibrator SR-FF, so become moment of high level at output signal Q, the output signal CNOB100 of level shifter control circuit CN_100 becomes high level.

As if the terminal ENAB that the high level of output signal CNOB100 is input to level shifter LS_100, then level shifter LS_100 becomes non-action status.If level shifter LS_100 becomes non-action status, then the output signal LSO100 of level shifter LS_100 becomes low level.Even if output signal LSO100 becomes low level, the output signal Q of bistable multivibrator SR-FF, QB also export activation level (output signal Q is a high level, and output signal QB is a low level) continuously, up to till reseting terminal R input high level.

The output signal QB that possesses the bistable multivibrator SR after 2 grades of bistable multivibrator SR of this bistable multivibrator SR-FF by phase inverter I2 counter-rotating after, be input to the reseting terminal R of bistable multivibrator SR-FF.Therefore, the output signal Q of bistable multivibrator SR-FF, QB as shown in figure 35, after becoming activation, clock signal SCK is reset to non-activation at input 2 clocks when (1 cycle of clock signal SCK).

In addition, because being input to the input signal CINB of the input terminal IN2 of level shifter control circuit CN_100 is the output signal QB of the bistable multivibrator SR of prime, so after output signal Q, the QB of bistable multivibrator SR-FF became activation, clock signal SCK became high level at 1 clock of input when (semiperiod of clock signal SCK).

Therefore, when output signal Q, the QB of bistable multivibrator SR-FF revert to non-activation level from activation level, become high level owing to be input to the input signal CINB of input terminal IN2, so the lead-out terminal CNOB100 of level shifter control circuit CN_100 still is a high level.Thus, because level shifter LS_100 is a non-action status, so the output signal LSO100 of level shifter LS_100 still is a low level.Therefore, output signal Q, the QB with bistable multivibrator SR-FF remains on non-activation level (output signal Q is a low level, and output signal QB is a high level) really.

In addition, pulse (precharging signal) PO that the output signal CNOB100 of level shifter control circuit CN_100 shown in the timing diagram of Figure 35 uses as bistable multivibrator formerly (PO1, PO2 ..., POn), be input to the overlapping delay circuit Pd that prevents the own level among the 31c of portion (Pd1, Pd2 ..., Pdn).

As mentioned above, bistable multivibrator SR_100 feeds back to level shifter control circuit CN_100 with output signal Q, become activation (low level) before at output signal QB, the output signal CNOB100 of level shifter control circuit CN_100 becomes low level.Therefore, be used as precharging signal PO, can before constituting the QB of sampling, carry out precharge with pulse by output signal CNOB100 with this level shifter control circuit CN_100.

Like this, even if using bistable multivibrator SR_100 shown in Figure 32 to replace under the situation of bistable multivibrator SR shown in Figure 4, much the same action in the time of also can carrying out and use bistable multivibrator SR.

Use NOR circuit (logical circuit) NR1 opposite with the level shifter control circuit CN of bistable multivibrator SR, the level shifter control circuit CN_100 of bistable multivibrator SR_100 uses switch (on-off circuit) SW _CNTherefore, under the little situation of the retardation when the retardation of pulse when the on-off circuit passed through logical circuit than this pulse, can make the shift register high speed motion.

Under the big situation of the retardation of CNOB100, do not select the rising edge of clock signal SCK.At this moment, can not be shifted successively in the timing of the rising edge (even level is a negative edge) of clock signal SCK, shift register can not normal regularly under action.Therefore, preferably determine to be to use bistable multivibrator SR also to be to use bistable multivibrator SR_100 corresponding to the output delay of output signal amount in the level shifter control circuit.

In addition, in the present embodiment, illustrate that monolithic forms the liquid crystal indicator 1 of display part 2, data-signal line drive 31 and sweep signal line drive 4, but be not limited thereto, also each driver 3,4 can be formed on the different substrates with display part 2.

In addition, in the present embodiment, the situation that possesses data-signal line drive 31 in the liquid crystal indicator 1 is described, but is not limited thereto, for example so long as the display device of essential charging such as organic EL display wiring capacitance, then applicable to any display device.

[embodiment 2]

Another embodiment of the present invention is described.In addition, only otherwise special the qualification, the symbol identical with the symbol of parts that use in the embodiment 1 or signal has identical function, handles as the symbol of parts that can be out of shape (constituting change) equally and signal, omits its explanation.

(data-signal line drive 41)

Figure 20 is the formation block diagram of the data-signal line drive 41 of expression present embodiment.Possesses data-signal line drive 41, the data-signal line drive 31 in the liquid crystal indicator 1 of replacement embodiment 1.

As shown in the figure, data-signal line drive 41 possesses level shifter LS, shift register 41a, the 31b of sampling portion, the overlapping 31c of portion that prevents.Level shifter LS, the 31b of sampling portion, overlappingly prevent that the formation of the 31c of portion is the same with embodiment 1.

(shift register 41a)

Shift register 41a possess multistage be provided with restoration type bistable multivibrator SRFF (SRFFd1, SRFFd2, SRFF1, SRFF2 ..., SRFFn, SRFFd3, SRFFd4), be can along from SRFFd1 to the forward of SRFFd4, with from the bidirectional shift register of SRFFd4 to the reverse switching direction of displacement of SRFFd1.

The RB1 terminal, RB2 terminal, output sampling that each bistable multivibrator SRFF possesses CINB1 terminal, CINB2 terminal, the input reset signal of CK terminal, CKB terminal, input signalization with signal QB (QB1, QB2 ..., QBn) QB terminal, output precharge with signal PO (PO1, PO2 ... POn) PO terminal, input are used to control the SC terminal (not shown) of signal (the scanning switching signal) SC of direction of displacement.In addition, control circuit 5 outputs from liquid crystal indicator 1 with signal SC are switched in scanning.

Bistable multivibrator SRFFd1, the SRFF1 of odd level, SRFF3 ... to CK terminal input just commentaries on classics clock signal (clock signal) SCK, to CKB terminal input counter-rotating clock signal (clock signal) SCKB.In addition, bistable multivibrator SRFFd2, the SRFFd4 of even level ... to CK terminal input counter-rotating clock signal (clock signal) SCKB, to CKB terminal input just commentaries on classics clock signal (clock signal) SCK.

In addition, to the CINB1 terminal of the 1st grade of bistable multivibrator SRFF1 and the output signal SSPB ' of the CINB2 terminal incoming level shift unit LS of the bistable multivibrator SRFFd4 of final level, as signalization.Bistable multivibrator SRFFd2, SRFFd1 after the 2nd grade ..., SRFFd3, SRFFd4 the CINB1 terminal be connected on the QB terminal of prime bistable multivibrator of each bistable multivibrator.

On the other hand, the 1st grade of bistable multivibrator SRFFd1 is connected in to the CINB2 terminal in the bistable multivibrator of the bistable multivibrator SRFFd3 of the prime of final level on the QB terminal of subordinate's bistable multivibrator of each bistable multivibrator.

In addition, to the RB1 terminal input of the bistable multivibrator of the 1st grade of bistable multivibrator SRFFd1 to the n+2 level bistable multivibrator SRFFn from output signal QB1, the QB2 of the bistable multivibrator after 2 grades of each bistable multivibrator ..., QBd4.In addition, to the output signal QBd4 of the bistable multivibrator SRFFd4 of the final level of RB1 terminal input of the bistable multivibrator SRFFd3 of the prime of final level, to the output signal QBd4 of the RB1 terminal input self of the bistable multivibrator SRFFd4 of final level.

On the other hand, import the output signal QBd1 of self to the RB2 terminal of the 1st grade of bistable multivibrator SRFFd1.In addition, import the output signal QBd1 of the 1st grade bistable multivibrator SRFFd1 to the RB2 terminal of the 2nd grade bistable multivibrator SRFFd2.Import to the RB2 terminal of each bistable multivibrator of the bistable multivibrator SRFFd4 of final level to 3rd level bistable multivibrator SRFF1 output signal QB before 2 grades of each bistable multivibrator (QBd1, QBd2, QB1 ..., QBn).

In addition, bistable multivibrator SR1, the SR2 of 3rd level to the n+2 level ... the PO terminal of SRn be connected in overlapping prevent among the 31c of portion corresponding to delay circuit Pd at different levels (Pd1, Pd2 ..., Pdn) on.

(bistable multivibrator SRFF)

Figure 21 be each bistable multivibrator SRFF of expression (SRFFd1, SRFFd2, SRFF1 ..., SRFFd4) the block diagram of configuration example.

As shown in the figure, each bistable multivibrator SRFF possesses level shift control circuit CN, level shifter LS1, restoration type bistable multivibrator SR-FF, selector switch SELa, selector switch SELb, phase inverter I1, phase inverter I2 is set.

Level shift control circuit CN, level shifter LS1, bistable multivibrator SR-FF constitute the formation the same with each circuit of embodiment 1.

Selector switch SELa possesses input terminal SI1, SI2 and lead-out terminal SO.The input terminal SI1 of selector switch SELa is connected on the CINB1 terminal of bistable multivibrator SR-FF, and input terminal SI2 is connected on the CINB2 terminal of bistable multivibrator SR-FF.In addition, the lead-out terminal SO of selector switch SELa is connected on the input terminal IN2 of level shifter control circuit CN.Provide scanning to switch the signal SC of usefulness to selector switch SELa.

Selector switch SELb is the same with selector switch SELa to be constituted, and possesses input terminal SI1, SI2 and lead-out terminal SO.The input terminal SI1 of selector switch SELb is connected on the RB1 terminal of bistable multivibrator SR-FF, and input terminal SI2 is connected on the RB2 terminal of bistable multivibrator SR-FF.In addition, the lead-out terminal SO of selector switch SELb is connected on the input terminal of phase inverter I2, and the lead-out terminal of phase inverter I2 is connected on the R terminal of bistable multivibrator SR-FF.Provide scanning to switch the signal SC of usefulness to selector switch SELb.

Figure 22 is the block diagram of the configuration example of presentation selector SELa and selector switch SELb.As shown in the figure, selector switch SELa, SELb possess phase inverter Sinv and switch S sw1, Ssw2.

Switch S sw1, Ssw2 are by N-channel MOS transistor (TFT) that input signal is directly inputted to grid and analog switch that the P channel MOS transistor (TFT) of the signal behind inversion input signal input grid is constituted.

The scanning of phase inverter Sinv counter-rotating input selector SELa, SELb is switched and is used signal SC, Yi Bian make it to have the ability of the electric capacity that the grid of the P channel MOS transistor among fully charge and discharge switch Ssw1, the Ssw2 has, Yi Bian be input to grid.

The grid of each MOS transistor is capacitive control terminal, and each switch S sw1, Ssw2 are corresponding to the charging voltage of grid, switched conductive and non-conduction.

Input signal SI1 is input to an end of the channel path of switch S sw1.Input signal SI2 is input to an end of the channel path of switch S sw1.The other end of the channel path of switch S sw1 is connected jointly with the other end of the channel path of switch S sw2, constitutes lead-out terminal SO.

In the selector switch SELa, the SELb that so constitute, switching with signal SC in scanning is when representing the high level of forward scan, each transistor turns of switch S sw1, each transistor of switch S sw2 becomes non-conduction, so be input to the signal of input terminal SI1 from lead-out terminal SO, as output signal a, b.

In addition, switching with signal SC in scanning is when representing the low level of reverse scan, and each transistor of switch S sw1 becomes non-conduction, each transistor turns of switch S sw2, so be input to the signal of input terminal SI2 from lead-out terminal SO, as output signal a, b.

Below, the action of shift register 41a is described.At first, illustrate that direction of displacement is the situation of forward (just scanning).Figure 23 is the timing diagram of each the bistable multivibrator SR-FF of direction of displacement when being forward.

At this moment, because it is to represent the high level that just scanning that scanning is switched with signal SC, so the signal CINB1 that will be input to the CINB1 terminal from selector switch SELa is as output signal a output, will export as output signal b from the signal RB1 that selector switch SELb is input to the RB1 terminal.

Become low level if be input to the signal CINB1 of the CINB1 terminal of bistable multivibrator SR-FF, then the output signal a of selector switch SELa becomes low level, and described in enforcement mode 1, the output signal of level shifter control circuit CN becomes high level.Therefore, the precharge from the output of PO terminal becomes high level with signal PO.

Afterwards, if clock signal SCK becomes high level, then the output signal LSO of level shifter LS1 becomes high level, and the output signal of bistable multivibrator SR-FF becomes activation level (signal Q is a high level, and signal QB is a low level).Here, the output signal Q of SR-FF is imported into the input terminal IN1 of level shifter control circuit CN, so if output signal Q becomes high level, then the output signal of level shifter control circuit CN (output signal PO) becomes low level, and the output signal LSO of level shifter LS1 becomes low level.

Afterwards, if be input to the signal RB1 of the RB1 terminal of bistable multivibrator SRFF, promptly 2 grades of bistable multivibrator SRFF afterwards output signal QB (wherein, in bistable multivibrator SRFFd3, SRFFd4, be the output signal QBd4 of bistable multivibrator SRFFd4) become low level, then the output signal b of selector switch SELb becomes low level, output signal Q, the QB of bistable multivibrator SR-FF reset, become non-activation level (signal Q is a low level, and signal QB is a high level).

Figure 24 is the timing diagram of the data-signal line drive 41 of direction of displacement when being forward.

As shown in the figure, in bistable multivibrator SRFFd1, from level shifter LS output, based on the signal SSPB ' of starting impulse SSPB if become low level, then the precharge from the output of PO terminal becomes high level with signal POd1.Afterwards, if clock signal SCK becomes high level, then sampling becomes low level with output signal QBd1.In addition, because output signal Qd1 is fed back to level shifter control circuit CN, if output signal QBd1 becomes low level (output signal Qd1 is a high level), then the output signal POd1 of level shifter control circuit CN becomes low level.If the output signal QB1 of the bistable multivibrator SRFF1 after 2 grades becomes low level, then the output signal QBd1 with bistable multivibrator SRFFd1 resets to high level.

In addition, because the output signal QBd1 of bistable multivibrator SRFFd1 is imported into the 2nd grade bistable multivibrator SRFFd2, so if output signal QBd1 becomes low level, then the output signal POd2 of the level shifter control circuit CN of the 2nd grade of bistable multivibrator SRFFd2 becomes high level.Afterwards, if clock signal SCK becomes low level (clock signal SCKB is a high level), then will switch to low level from high level from the output signal QBd2 of QB terminal.In addition, thus, the output signal POd2 of level shifter control circuit CN becomes low level.Afterwards, if the output signal QB2 of the bistable multivibrator SRFF2 after 2 grades becomes low level, then the output signal QBd2 of bistable multivibrator SRFFd2 is reset to high level.

In addition, because the output signal QBd2 of bistable multivibrator SRFFd2 is imported into the bistable multivibrator SRFF1 of 3rd level, so if output signal QBd2 becomes low level, then the output signal PO1 from the PO terminal of 3rd level bistable multivibrator SRFF1 becomes high level.Afterwards, if clock signal SCK becomes high level from low level, then will switch to low level from high level from the output signal QB1 of QB terminal.In addition, thus, become low level from the output signal PO1 of PO terminal.Here, because the output signal QB1 of 3rd level bistable multivibrator SRFF1 is imported into the RB terminal of the 1st grade of bistable multivibrator SRFFd1, so if the output signal QB1 of 3rd level bistable multivibrator SRFF1 switches to low level, then the output signal QBd1 of the 1st grade of bistable multivibrator SRFFd1 is reset to high level.

Bistable multivibrator SRFF afterwards also carries out same action, after the output signal QB of bistable multivibrator SRFF at different levels becomes low level, the output signal QB of bistable multivibrator SR after its 2 grades becomes low level, thereby resets to high level.Bistable multivibrator SRFFd3, SRFFd4 are as the tseudo circuit of the timing of the output signal QBn-1, the QBn that export reset bistable multivibrator SRFFn-1, SRFFn.

Like this, in data-signal line drive 41, in direction of displacement is under the situation of forward (just scanning), uses the signal of own level among each bistable multivibrator SRFFk (k is the integer of 1-n), carries out the preparation charging corresponding to the data signal line and the pixel capacitance of this grade.In addition, use the output signal of 2 grades of bistable multivibrator SRFFk+2 afterwards, output signal Qk, the QBk of the bistable multivibrator SR-FFk that resets make between sampling period and finish.

Below, the situation of direction of displacement for reverse (inverse scan) is described.Figure 25 is the timing diagram of each the bistable multivibrator SRFF of direction of displacement when being reverse.

At this moment, because it is the low level of representing inverse scan that scanning is switched with signal SC, so the signal CINB2 that will be input to the CINB2 terminal from selector switch SELa is as output signal a output, will export as output signal b from the signal RB2 that selector switch SELb is input to the RB2 terminal.

Become low level if be input to the signal CINB2 of the CINB2 terminal of bistable multivibrator SRFF, then the output signal a of selector switch SELa becomes low level, and described in enforcement mode 1, the output signal of level shifter control circuit CN becomes high level.Therefore, the precharge from the output of PO terminal becomes high level with signal PO.

Afterwards, if clock signal SCK becomes high level, then the output signal LSO of level shifter LS1 becomes high level, and the output signal of bistable multivibrator SR-FF becomes activation level (signal Q is a high level, and signal QB is a low level).Here, the output signal Q of SR-FF is imported into the input terminal IN1 of level shifter control circuit CN, so if output signal Q becomes high level, then the output signal of level shifter control circuit CN (output signal PO) becomes low level, and the output signal LSO of level shifter LS1 becomes low level.

Afterwards, if be input to the signal RB2 of the RB2 terminal of bistable multivibrator SRFF, promptly the bistable multivibrator after 2 grades of direction of displacement (inverse scan direction) output signal QB (wherein, in bistable multivibrator SRFFd2, SRFFd1, be the output signal QBd1 of bistable multivibrator SRFFd1) become low level, then the output signal b of selector switch SELb becomes low level, output signal Q, the QB of bistable multivibrator SR-FF reset, become non-activation level (signal Q is a low level, and signal QB is a high level).

Figure 26 is the timing diagram of the data-signal line drive 41 of direction of displacement when being reverse.

As shown in the figure, in bistable multivibrator SRFFd4, from level shifter LS output, based on the signal SSPB ' of starting impulse SSPB if become low level, then the sampling from the output of PO terminal becomes high level with signal Pod4.Afterwards, if clock signal SCK becomes high level, then sampling becomes low level with output signal QBd4.In addition, because output signal Qd4 is fed back to level shifter control circuit CN, if output signal QBd4 becomes low level (output signal Qd4 is a high level), then the output signal Pod4 of level shifter control circuit CN becomes low level.If the output signal QBn of the bistable multivibrator SRFFn after 2 grades of direction of displacement becomes low level, then the output signal QBd4 with bistable multivibrator SRFFd4 resets to high level.

In addition, because the output signal QBd4 of bistable multivibrator SRFFd4 is imported into the bistable multivibrator SRFFd3 of subordinate's (along the 2nd grade of direction of displacement), so if output signal QBd4 becomes low level, then the output signal Pod3 of the level shifter control circuit CN of bistable multivibrator SRFFd3 becomes high level.Afterwards, if clock signal SCK becomes low level (clock signal SCKB is a high level), then will switch to low level from high level from the output signal QBd3 of QB terminal.In addition, thus, the output signal Pod3 of level shifter control circuit CN becomes low level.Afterwards, if the output signal QBn-1 of the bistable multivibrator SRFFn-1 of subordinate's (after 2 grades of direction of displacement) becomes low level again, then the output signal QBd3 of bistable multivibrator SRFFd3 is reset to high level.

In addition, because the output signal QBd3 of bistable multivibrator SRFFd3 is imported into the bistable multivibrator SRFFn of subordinate's (along 3rd level of direction of displacement), so if output signal QBd3 becomes low level, then the output signal POn from the PO terminal of bistable multivibrator SRFFn becomes high level.Afterwards, if clock signal SCK becomes high level from low level, then will switch to low level from high level from the output signal QBn of QB terminal.In addition, thus, become low level from the output signal POn of PO terminal.Here, because the output signal QBn of bistable multivibrator SRFFn is imported into the RB2 terminal of bistable multivibrator SRFFd4, so if the output signal QBn of bistable multivibrator SRFFn switches to low level, then the output signal QBd4 of bistable multivibrator SRFFd4 is reset to high level.

The bistable multivibrator SRFF along direction of displacement afterwards also carries out same action, after the output signal QB of bistable multivibrator SRFF at different levels becomes low level, the output signal QB of bistable multivibrator SR after 2 grades of direction of displacement becomes low level, thereby resets to high level.Bistable multivibrator SRFFd2, SRFFd2 are as the tseudo circuit of the timing of the output signal QB2, the QB1 that export reset bistable multivibrator SRFF2, SRFF1.

Like this, in data-signal line drive 41, be under the situation of reverse (inverse scan) in direction of displacement, use the signal of own level among each bistable multivibrator SRFFk, carry out preparation charging corresponding to the data signal line and the pixel capacitance of this grade.In addition, use the output signal of the bistable multivibrator SRFFk-2 after 2 grades of direction of displacement (inverse scan direction), output signal Qk, the QBk of the bistable multivibrator SR-FFk that resets make between sampling period and finish.

Therefore, in data-signal line drive 41, no matter which direction is direction of displacement be, all can use the signal of the own level among each bistable multivibrator SRFF, carries out the preparation charging corresponding to the data signal line and the pixel capacitance of this grade.In addition, can use the output signal of the bistable multivibrator SRFF after 2 grades of direction of displacement, output signal Q, the QB of the bistable multivibrator SR-FF that resets make between sampling period and finish.

As mentioned above, in data-signal line drive 41, use the signal of the own level among each bistable multivibrator SRFF, carry out preparation charging corresponding to the data signal line and the pixel capacitance of this grade.Therefore, needn't resemble the above-mentioned patent documentation 3, possess the precharging signal commutation circuit that is used for selecting the output stage of pre-charge circuit drive signal corresponding to the direction of displacement of bidirectional shift register.

In the technology of patent documentation 3, the pre-charge circuit drive signal of the output stage before the input of above-mentioned precharging signal commutation circuit is from 2 grades, with from 2 grades after the pre-charge circuit drive signal of output stage.Therefore, exist the cabling area of the occupied area of precharging signal commutation circuit and wiring to increase, cause the problem of the maximization of driving circuit.

On the contrary, in the data-signal line drive 41 of present embodiment, needn't this precharging signal commutation circuit and will be from the pre-charge circuit drive signal of the output stage before 2 grades and the wiring of importing above-mentioned precharging signal commutation circuit from the pre-charge circuit drive signal of the output stage after 2 grades.

Therefore, can be in the formation of reduced data signal line drive 41, the size in the size of miniaturization data-signal line drive 41 and its wiring zone on every side of winding.Thus, can when dwindling panel physical dimension, increase the ratio of the relative panel physical dimension of size of viewing area.

(variation)

(variation of bistable multivibrator SRFF)

In the present embodiment, illustrate that shift register 41a is made of the multistage restoration type bistable multivibrator SRFF that is provided with, but be not limited thereto.

For example, also can use shift-register circuit SRC shown in Figure 27 (SRCd1, SRCd2, SRC1, SRC2 ..., SRCd4), replace above-mentioned bistable multivibrator SRFF (SRFFd1, SRFFd2, SRFF1 ..., SRFFd4).

As shown in the figure, shift-register circuit SRC constitutes the level shifter LS1 among the bistable multivibrator SRFF is replaced into on-off circuit ASW, and the CKB terminal is made as disconnected (Non-connection).

On-off circuit ASW is directly inputted to grid by phase inverter Iasw, with input signal N-channel MOS is by transistor (TFT) NTasw, constitute with P channel MOS transistor (TFT) PTasw with the input of the signal behind inversion input signal grid.

The output signal (output signal PO) of phase inverter Iasw reverse turn control circuit CN makes it the ability that the limit has the electric capacity that the grid that can fully discharge and recharge P channel MOS transistor PTasw has, and the limit is input to grid.The formation of control circuit CN is the same with the formation of above-mentioned level shifter control circuit.

In addition, the output of phase inverter Iasw is input to the grid of N type MOS transistor N55.The source electrode of transistor N55 is connected on the power supply Vssd of downside, and drain electrode is connected on the input terminal of phase inverter I1.

The grid of each MOS transistor is capacitive control terminal, corresponding to the charging voltage of grid, and switched conductive and non-conduction.End to the channel path of MOS transistor is connected on the CK terminal.In addition, to level shifter circuit SRCd1, the SRC1 of odd level, SRC3 ... CK terminal input just changeing clock signal (clock signal) SCK, to level shifter circuit SRCd2, the SRC2 of even level, SRC4 ... CK terminal input counter-rotating clock signal (clock signal) SCKB.

The other end of the channel path of each MOS transistor is connected on the input terminal of phase inverter I1.Thus, the output signal ASW with on-off circuit ASW is input to phase inverter I1.

Figure 28 is that direction of displacement is a timing diagram under the situation of forward (just scanning), each shift-register circuit SRC.

At this moment, it is to represent the high level that just scanning that scanning is switched with signal SC, so will export as output signal a from the signal CINB1 that selector switch SELa is input to the CINB1 terminal, will export as output signal b from the signal RB1 that selector switch SELb is input to the RB1 terminal.

Become low level if be input to the signal CINB1 of the CINB1 terminal of level shifter circuit SRC, then the output signal a of selector switch SELa becomes low level, and the output signal of control circuit CN becomes high level.Therefore, the precharge from the output of PO terminal becomes high level with signal PO.

In addition, if the output signal of control circuit CN becomes high level, then each MOS transistor PTasw, the NTasw conducting among the on-off circuit ASW.

Therefore, afterwards, if clock signal SCK becomes high level, then the output signal ASW of on-off circuit ASW becomes high level, and the output signal of bistable multivibrator SR-FF becomes activation level (signal Q is a high level, and signal QB is a low level).Here, the output signal Q of SR-FF is imported into the input terminal IN1 of level shifter control circuit CN, so if output signal Q becomes high level, then the output signal of level shifter control circuit CN becomes low level, and each MOS transistor PTasw, NTasw among the on-off circuit ASW become non-conduction.At this moment, because phase inverter Iasw becomes low level, so transistor N55 is switched on, output signal ASW pulled down to low level.

Afterwards, if be input to the signal RB1 of the RB1 terminal of level shifter circuit SRC, promptly 2 grades of level shifter circuit SRC afterwards output signal QB (wherein, in level shifter circuit SRCd3, SRCd4, be the output signal QBd4 of bistable multivibrator SRCd4) become low level, then the output signal b of selector switch SELb becomes low level, output signal Q, the QB of reset level shifter circuit SRC, become non-activation level (signal Q is a low level, and signal QB is a high level).

Figure 29 is that direction of displacement is the reverse timing diagram of each the shift-register circuit SRC when (inverse scan).

At this moment, it is the low level of representing inverse scan that scanning is switched with signal SC, so will export as output signal a from the signal CINB2 that selector switch SELb is input to the CINB2 terminal, will export as output signal b from the signal RB2 that selector switch SELb is input to the RB2 terminal.

Become low level if be input to the signal CINB2 of the CINB2 terminal of level shifter circuit SRC, then the output signal a of selector switch SELa becomes low level, and the output signal of control circuit CN becomes high level.Therefore, the precharge from the output of PO terminal becomes high level with signal PO.

In addition, if the output signal of control circuit CN becomes high level, then each MOS transistor PTasw, the NTasw conducting among the on-off circuit ASW.

Therefore, afterwards, if clock signal SCK becomes high level, then the output signal ASW of on-off circuit ASW becomes high level, and the output signal of bistable multivibrator SR-FF becomes activation level (signal Q is a high level, and signal QB is a low level).Here, the output signal Q of SR-FF is imported into the input terminal IN1 of level shifter control circuit CN, so if output signal Q becomes high level, then the output signal of level shifter control circuit CN becomes low level, and each MOS transistor PTasw, NTasw among the on-off circuit ASW become non-conduction.At this moment, because phase inverter Iasw becomes low level, so transistor N55 is switched on, output signal ASW pulled down to low level.

Afterwards, if be input to the signal RB2 of the RB2 terminal of level shifter circuit SRC, promptly the level shifter circuit after 2 grades of direction of displacement (inverse scan direction) output signal QB (wherein, in level shifter circuit SRCd2, SRCd1, be the output signal QBd1 of level shifter circuit SRCd1) become low level, then the output signal b of selector switch SELb becomes low level, output signal Q, the QB of bistable multivibrator SR-FF reset, become non-activation level (signal Q is a low level, and signal QB is a high level).

Therefore, data-signal line drive 41 under the situation of using shift-register circuit SRC shown in Figure 27, also much the same action when using above-mentioned bistable multivibrator SRFF.

In addition, in the above-mentioned explanation, the situation that possesses shift-register circuit SRC among the bidirectional shift register 41a is described, but is not limited thereto, for example also can be provided among the shift register 31a of embodiment 1.At this moment, as long as omit selector switch SELa, connecting level shifter control circuit CN (at this moment, be not level shifter control circuit but control circuit, but that circuit constitutes is identical.) IN2 terminal and CINB1 terminal (CINB terminal), omit selector switch SELb, the input terminal and the RB1 terminal (RB terminal) that connect opposite device I2 get final product.

In addition, but display part 2 and data-signal line drive 41 and sweep signal line drive 4 also monolithic be formed on the same substrate, perhaps, be formed at respectively on the different substrates.

In addition, in the present embodiment, the situation that possesses data-signal line drive 41 in the liquid crystal indicator 1 is described, but is not limited thereto, for example so long as the display device of essential charging such as organic EL display wiring capacitance, then applicable to any display device.

As mentioned above, the driving circuit of display device of the present invention is provided with write circuit, for be arranged on a plurality of signals in the display device provide line each, possess the 1st switch, utilize the conducting of above-mentioned each the 1st switch, carry out the writing of write signal that above-mentioned each signal is provided line; Shift register possesses multistage generation and is used to make the pulse of the timing pip of above-mentioned the 1st switch conduction to generate parts, exports the timing pip that above-mentioned each signal is provided line successively; With the preparation charging circuit, to above-mentioned signal provide line each, possesses the 2nd switch, utilize the conducting of above-mentioned each the 2nd switch, execution provides the preparation charging of line to above-mentioned each signal, it is characterized in that: above-mentioned each pulse generates the parts input generates parts output from the above-mentioned pulse of each prime above-mentioned timing pip, after this timing pip becomes the activation level that makes above-mentioned the 1st switch conduction, in during before the above-mentioned timing pip of above-mentioned each pulse generation parts self output activation level, generate the timing pip of parts self output according to above-mentioned each pulse, make the above-mentioned signal that writes corresponding to execution that above-mentioned the 2nd switch conduction of line is provided, output is used to prepare the preparation charging pulse that this signal of charging provides line.

According to above-mentioned formation, above-mentioned each pulse generates parts according to the timing pip of self exporting, and makes the above-mentioned signal that writes corresponding to execution that above-mentioned the 2nd switch conduction of line is provided, and output is used to prepare the preparation charging pulse that this signal of charging provides line.Thus, essential tseudo circuit before needn't being provided with, this tseudo circuit generates the timing pip that parts or elementary and the 2nd grade of pulse generate parts output according to elementary above-mentioned pulse, and output is used to prepare charging and carries out the above-mentioned signal that writes and provide the preparation of line and charge and use pulse.Therefore, Miniaturizable inside possess the preparation charging circuit display device driving circuit area and be wrapped in the area of the wiring around the above-mentioned driving circuit.

In addition, also can constitute on each output line of above-mentioned timing pip, possess the overlapping parts that prevent, remove in the activation level of the above-mentioned timing pip offer this output line, be used to prepare charging and carry out the above-mentioned signal that writes with this timing pip and provide and state the activation level of pulse is used in the preparation charging with pulse and the above-mentioned preparation charging that makes above-mentioned the 2nd switch conduction lap on the line.

According to above-mentioned formation, be arranged on overlapping on each output line of above-mentioned timing pip prevent parts remove during the activation level of the above-mentioned timing pip that offers each output line in, with the lap that is used to prepare during the activation level of pulse is used in preparation charging that charging carries out the signal that writes and provide line with this timing pip.Therefore, for example, even if the output of the bistable multivibrator that the front end during utilizing the preparation charging with the activation level of rear end during the activation level of pulse and timing pip is synchronous, preparation charging with during the activation level of pulse with the activation level of timing pip during not overlapping yet, can prevent really that the paired sampling that provides line to be provided with to each signal respectively charges with the synchronous conducting of the 2nd switch with the 1st switch and preparation.Therefore, can avoid causing write signal to provide the state of affairs of conflicting on the line at signal really with the preparation charging potential.

In addition, also can constitute and also possess delay unit, make from above-mentioned each pulse and generate the preparation charging of parts output with after the pulse daley, output to above-mentioned each the 2nd switch and above-mentioned each overlapping parts that prevent, above-mentioned overlapping prevent parts remove in the activation level of above-mentioned timing pip, with the preparation charging of above-mentioned delay unit output lap with the activation level of pulse.

According to above-mentioned formation, above-mentioned overlapping prevent parts remove between the active period of above-mentioned timing pip in, and the preparation charging of above-mentioned delay unit output with the lap between the active period of pulse.Therefore, because the front end quantitative change of being cut down between the active period of above-mentioned timing pip is big, so can prevent each other overlapping of above-mentioned timing pip.In addition,, then in video signal cable, produce current potential and shake if timing pip overlaps each other, so show uniformity is low inferior, infringement image grade, but, can prevent that show uniformity is low by preventing that as mentioned above timing pip from overlapping each other.

In addition, also can constitute above-mentioned each pulse generation parts above-mentioned timing pip that back level pulse generation parts of regulation progression are exported after this each pulse generates parts becomes under the situation of activation level, the above-mentioned timing pip of self output is become and makes above-mentioned the 1st switch become non-conduction non-activation level, and the above-mentioned preparation charging that is postponed by above-mentioned delay unit generates above-mentioned timing pip that parts export and becomes after the activation level with time delay of pulse generating the back level pulse of regulation progression after parts than last each pulse, the time that the above-mentioned timing pip of above-mentioned each pulse generation parts output becomes before the non-activation level is long.

According to above-mentioned formation, can remove activation level that above-mentioned each pulse generates the timing pip of parts output really, generate the lap of the activation level of the timing pip that parts export with the back level pulse of after this each pulse generates parts, stipulating progression.Therefore, can prevent really that show uniformity is low.

In addition, what can constitute also that above-mentioned each pulse generates that parts possess above-mentioned each timing pip of output is provided with the restoration type bistable multivibrator, control assembly with the signalization of controlling above-mentioned bistable multivibrator, above-mentioned control assembly is an activation level at the above-mentioned timing pip that the pulse that possesses this control assembly generates the prime pulse generation parts output of parts, the timing pip that possesses the pulse generation parts output of this control assembly is under the situation of non-activation level, the signal of clock signal or transformation clock signal is made as the signalization of above-mentioned bistable multivibrator, and the pulse that above-mentioned bistable multivibrator will possess this bistable multivibrator generates the timing pip that the back level pulse of regulation progression after the parts generates parts output and is made as reset signal.

According to above-mentioned formation, the timing pip that the pulse that above-mentioned control assembly is activation level at the timing pip that the pulse that possesses this control assembly generates the prime signal-line choosing parts output of parts, possess this control assembly generates parts output is under the situation of non-activation level, the signal of clock signal or transformation clock signal is made as the signalization of above-mentioned bistable multivibrator.Therefore, write signal that the prime pulse that generates parts corresponding to above-mentioned each pulse generates parts provide line during, promptly begin to the signal that generates parts corresponding to above-mentioned each pulse provide line before writing during, can suitably prepare charging and provide line corresponding to the signal that above-mentioned each pulse generates parts.

In addition, the above-mentioned pulse that also can constitute odd level generates parts and uses the signal that is just changeing one of clock signal or counter-rotating clock signal as above-mentioned clock signal, and the above-mentioned pulse of even level generates parts and uses another signal as above-mentioned clock signal.

According to above-mentioned formation, even if the amplitude of above-mentioned clock signal is little, under the situation of essential level shift, also can uses and just change clock signal and counter-rotating clock signal, so level shift stably.

In addition, also can constitute above-mentioned shift register is that changeable above-mentioned multistage pulses generates the bidirectional shift register that parts are exported the direction of displacement of timing pip successively, above-mentioned each pulse generates parts and possesses the 1st selector part, the pulse of selecting relative these each pulse generation parts to constitute the prime of above-mentioned direction of displacement generates the timing pip of parts output, is input to above-mentioned control assembly; With the 2nd selector part, the timing pip that the pulse generation parts of the back level of progression above-mentioned direction of displacement are afterwards exported is stipulated in selection this each pulse generation parts formation relatively, as reset signal, is input to above-mentioned bistable multivibrator.

According to above-mentioned formation, in the driving circuit of the display device that possesses bidirectional shift register, the changeable direction that writes above-mentioned signal wire successively, the precharging signal commutation circuit that possesses in the driving circuit of electrooptical device of patent documentation 3, be used to select prepare the signal wire of charging needn't be set.Therefore, can reduce the size of the driving circuit of display device.

In addition, also can constitute the number of output lines of above-mentioned each timing pip, above-mentioned each preparation charging with the number of output lines of pulse, provide the quantity of line corresponding with above-mentioned signal, make above-mentioned each the 2nd switch successively in the conducting, make the conducting successively of above-mentioned the 1st switch, so that make the conduction period of above-mentioned each the 1st switch and carry out the signal that writes corresponding to the conducting that utilizes this each the 1st switch and provide conduction period of above-mentioned the 2nd switch of line not overlapping.

According to above-mentioned formation, essential tseudo circuit before needn't being provided with, this tseudo circuit generates the timing pip that parts or elementary and the 2nd grade of pulse generate parts output according to elementary above-mentioned pulse, and output is used to prepare charging and carries out the above-mentioned signal that writes and provide the preparation of line and charge and use pulse.Therefore, Miniaturizable inside possess the preparation charging circuit display device driving circuit area and be wrapped in the area of the wiring around the above-mentioned driving circuit.

In addition, also can constitute the number of output lines of above-mentioned each timing pip, above-mentioned each preparation charging with the number of output lines of pulse, to be made as the group quantity of 1 unit corresponding with the regulation bar number that above-mentioned signal is provided line, when in above-mentioned each group, making above-mentioned respectively the 2nd switch conduction successively simultaneously and to above-mentioned each group, in above-mentioned group, make above-mentioned each the 1st switch conduction successively simultaneously and to above-mentioned each group, so that make the conduction period of conduction period of above-mentioned the 1st switch and above-mentioned the 2nd switch not overlapping.

According to above-mentioned formation, the timing pip that utilizes above-mentioned each pulse to generate parts output once many successively signal is provided line to carry out multiple spot that write, so-called simultaneously in the driving circuit of the driving circuit of type of drive or phase demodulation mode, tseudo circuit needn't be set, this tseudo circuit generates the timing pip that parts or elementary and the 2nd grade of pulse generate parts output according to elementary above-mentioned pulse, and output is used to prepare charging and carries out the above-mentioned signal that writes and provide the preparation of line and charge and use pulse.Therefore, the size of the driving circuit of Miniaturizable display device.In addition, at multiple spot simultaneously in the driving circuit of the driving circuit of type of drive or phase demodulation mode, because the wiring quantity of twining around the driving circuit is many, so, can cut down the area of the non-display area in the display device that possesses this driving circuit especially effectively by reducing the size of driving circuit.

In addition, display device of the present invention possesses a plurality of pixels; The data signal line of line is provided and the scan signal line of line is provided as a plurality of signals corresponding to a plurality of signals of the conduct of above-mentioned pixel setting; To write the data-signal line drive of above-mentioned data signal line and above-mentioned pixel as the vision signal of write signal; With the sweep signal line drive, in order to select to write the pixel of above-mentioned vision signal, write sweep signal to above-mentioned scan signal line, it is characterized in that: possess the driving circuit of one of above-mentioned display device, as above-mentioned data-signal line drive as write signal.

According to above-mentioned formation owing to can reduce the size of the driving circuit of display device, so can reduce display part the housing area, be the area of non-display area, realize the display device of viewing area field width.

The invention is not restricted to the respective embodiments described above, can carry out various changes in scope shown in the claim, the resulting embodiment of disclosed respectively technological means also is contained in the technical scope of the present invention in the different embodiments of appropriate combination.Promptly, embodiment in the best mode item that carries out an invention or embodiment make technology contents of the present invention become clear, should not be limited to this concrete example and come narrow definition, in the scope of spirit of the present invention and patent request, can carry out various changes and implement.

Utilizability on the industry

The present invention is applicable to the data signal wire driving circuit in the display unit such as image display device Deng.

Claims (10)

1. the driving circuit of a display device is provided with:

Write circuit, a plurality of signals that are provided with in the display device line is provided each possess the 1st switch, and utilize the conducting of above-mentioned each the 1st switch, carry out the writing of write signal that above-mentioned each signal is provided line;

Shift register possesses multistage generation and is used to make the pulse of the timing pip of above-mentioned the 1st switch conduction to generate parts, exports the timing pip that above-mentioned each signal is provided line successively; With

Preparation charging circuit, above-mentioned signal line is provided each possess the 2nd switch, and utilize the conducting of above-mentioned each the 2nd switch, carry out the preparation charging that line is provided to above-mentioned each signal,

This driving circuit is characterised in that:

Above-mentioned each pulse generates the parts input generates parts output from the above-mentioned pulse of each prime above-mentioned timing pip, after this timing pip becomes the activation level that makes above-mentioned the 1st switch conduction, in during before the above-mentioned timing pip of above-mentioned each pulse generation parts self output activation level, generate the timing pip of parts self output according to above-mentioned each pulse, make the above-mentioned signal that writes corresponding to execution that above-mentioned the 2nd switch conduction of line is provided, output is used to prepare the preparation charging pulse that this signal of charging provides line.

2. the driving circuit of display device according to claim 1 is characterized in that:

On each output line of above-mentioned timing pip, possess the overlapping parts that prevent, remove in the activation level of the above-mentioned timing pip offer this output line, be used to prepare the activation level of pulse is used in above-mentioned preparation charging that charging carries out the above-mentioned signal that writes and provide line with this timing pip with pulse and the above-mentioned preparation charging that makes above-mentioned the 2nd switch conduction lap.

3. the driving circuit of display device according to claim 2 is characterized in that:

Also possess delay unit, make from the preparation of above-mentioned each pulse generation parts output and charge, output to above-mentioned each the 2nd switch and above-mentioned each overlapping preventing in the parts with after the pulse daley,

Above-mentioned overlapping prevent parts remove in the activation level of above-mentioned timing pip, with the preparation charging of above-mentioned delay unit output lap with the activation level of pulse.

4. the driving circuit of display device according to claim 3 is characterized in that:

The above-mentioned timing pip that above-mentioned each pulse generates parts back level pulse generation parts output of regulation progression after this each pulse generates parts becomes under the situation of activation level, the above-mentioned timing pip of self output is become and makes above-mentioned the 1st switch become non-conduction non-activation level

To become the non-activation level time before long with time delay of pulse generating above-mentioned timing pip that the back level pulse of regulation progression after parts generates parts output becomes after the activation level, above-mentioned each pulse generates parts output above-mentioned timing pip than above-mentioned each pulse in the above-mentioned preparation charging that is postponed by above-mentioned delay unit.

5. according to the driving circuit of one of claim 1-4 described display device, it is characterized in that:

Above-mentioned each pulse generates parts to be possessed: export the control assembly that the restoration type bistable multivibrator is set and controls the signalization of above-mentioned bistable multivibrator of above-mentioned timing pip,

The timing pip that the pulse that the above-mentioned timing pip that the prime pulse that above-mentioned control assembly generates parts in the pulse that possesses this control assembly generates parts output is activation level, possess this control assembly generates parts output is under the situation of non-activation level, the signal of clock signal or transformation clock signal is made as the signalization of above-mentioned bistable multivibrator

The pulse that above-mentioned bistable multivibrator will possess this bistable multivibrator generates the timing pip that the back level pulse of regulation progression after the parts generates parts output and is made as reset signal.

6. the driving circuit of display device according to claim 5 is characterized in that:

The above-mentioned pulse of odd level generates parts and uses the signal that is just changeing one of clock signal or counter-rotating clock signal as above-mentioned clock signal,

The above-mentioned pulse of even level generates parts and uses another signal as above-mentioned clock signal.

7. according to the driving circuit of one of claim 1-6 described display device, it is characterized in that:

Above-mentioned shift register is that changeable above-mentioned multistage pulses generates the bidirectional shift register that parts are exported the direction of displacement of timing pip successively,

Above-mentioned each pulse generates parts to be possessed: the 1st selector part, and the pulse of selecting relative these each pulse generation parts to become the prime of above-mentioned direction of displacement generates the timing pip of parts output, and is input to above-mentioned control assembly; With the 2nd selector part, the pulse of selecting relative these each pulse generation parts to become the back level of regulation progression above-mentioned direction of displacement afterwards generates the timing pip that parts are exported, and as reset signal, is input to above-mentioned bistable multivibrator.

8. according to the driving circuit of one of claim 1-7 described display device, it is characterized in that:

The number of output lines of above-mentioned each timing pip, above-mentioned each preparation charging provide the quantity of line to correspond to each other with the number of output lines of pulse, above-mentioned signal,

Make above-mentioned each the 2nd switch successively in the conducting, make above-mentioned each the 1st switch conducting successively, so that make the conduction period of above-mentioned each the 1st switch and carry out the signal that writes corresponding to the conducting that utilizes this each the 1st switch and provide conduction period of above-mentioned the 2nd switch of line not overlapping.

9. according to the driving circuit of one of claim 1-7 described display device, it is characterized in that:

The number of output lines of above-mentioned each timing pip, above-mentioned each preparation charging correspond to each other with the number of output lines of pulse, the group quantity that provides the regulation bar number of line to be made as 1 unit above-mentioned signal,

When in above-mentioned each group, making above-mentioned respectively the 2nd switch conduction successively simultaneously and to above-mentioned each group, in above-mentioned group, make above-mentioned each the 1st switch conduction successively simultaneously and to above-mentioned each group, so that make the conduction period of above-mentioned the 1st switch and carry out the signal that writes corresponding to the conducting that utilizes this each the 1st switch and provide conduction period of above-mentioned the 2nd switch of line not overlapping.

10. display device possesses:

A plurality of pixels;

The data signal line of line is provided and the scan signal line of line is provided as a plurality of signals corresponding to a plurality of signals of the conduct of above-mentioned pixel setting;

To write the data-signal line drive of above-mentioned data signal line and above-mentioned pixel as the vision signal of write signal; With

The sweep signal line drive, it is in order to select to write the pixel of above-mentioned vision signal, writes sweep signal as write signal to above-mentioned scan signal line,

This display device is characterised in that:

The driving circuit that possesses one of claim 1-9 described display device is as above-mentioned data-signal line drive.

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