CN112201577B - Method for preventing wafer back pollution and wafer back protection layer - Google Patents
Method for preventing wafer back pollution and wafer back protection layer Download PDFInfo
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- CN112201577B CN112201577B CN202010971579.1A CN202010971579A CN112201577B CN 112201577 B CN112201577 B CN 112201577B CN 202010971579 A CN202010971579 A CN 202010971579A CN 112201577 B CN112201577 B CN 112201577B
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- side wall
- crystal
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000011241 protective layer Substances 0.000 claims abstract description 62
- 238000005260 corrosion Methods 0.000 claims abstract description 23
- 230000007797 corrosion Effects 0.000 claims abstract description 22
- 230000003647 oxidation Effects 0.000 claims abstract description 21
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 21
- 239000013078 crystal Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 53
- 239000000463 material Substances 0.000 claims description 31
- 238000010438 heat treatment Methods 0.000 claims description 10
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 239000002253 acid Substances 0.000 claims description 4
- 238000011109 contamination Methods 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 230000000087 stabilizing effect Effects 0.000 abstract description 3
- 238000002161 passivation Methods 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000005554 pickling Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007669 thermal treatment Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- -1 silicon carbide nitride Chemical class 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Abstract
The invention relates to a method structure for preventing the pollution of a crystal back, which relates to the manufacturing technology of a semiconductor integrated circuit.A protective layer with strong oxidation resistance and corrosion resistance is newly added on the crystal back after a first side wall and a first protective layer of a semiconductor device are formed, so that in the subsequent process flow, the protective layer with strong oxidation resistance and corrosion resistance protects the crystal back from being corroded or oxidized, thereby achieving the purpose of stabilizing the state of the crystal back.
Description
Technical Field
The present invention relates to semiconductor integrated circuit manufacturing technology, and more particularly, to a method for preventing backside contamination.
Background
In the field of semiconductor integrated circuits, with the development of technology, the critical dimension of semiconductor devices is continuously shrinking, and the requirements on the manufacturing process of semiconductor devices are becoming stricter.
In the existing 28HKMG production process, when the first sidewall (spacer 1) of the gate structure is grown, a thin nitride layer, such as SICN, is also grown on the back surface of the wafer, i.e., the wafer back, so as to prevent the wafer back from being contaminated by corrosion and oxidation of the subsequent process flow. However, the stability of the nitride is not good enough, and the nitride still undergoes chemical reaction and is corroded or oxidized in the subsequent process flow, such as the pickling process, so that the height difference of the back of the wafer is large.
The wafer with the bad wafer back state seriously affects the subsequent process and the wafer yield, for example, when the wafer enters a photoetching exposure machine for height calibration, bad exposure can be caused due to the abnormal height of a local area, so that a larger error is generated in the registration precision, and the photoetching exposure machine is polluted due to the adhesion of particles on the photoetching exposure machine caused by the corrosion of the wafer back, so that a serious defect problem is generated.
Disclosure of Invention
The invention provides a method for preventing the pollution of a wafer back, which comprises the following steps: s1: providing a wafer, wherein the wafer comprises a first surface and a wafer back opposite to the first surface; s2: forming a grid structure of a semiconductor device on a first surface of a wafer, then forming a first side wall of the grid structure, and simultaneously forming a first protective layer on a wafer back while forming the first side wall, wherein the material of the first protective layer is the same as that of the first side wall; and S3: and after the step S2, forming a second protective layer on the first protective layer on the crystal back, wherein the second protective layer is made of corrosion-resistant and oxidation-resistant materials.
Furthermore, the first side wall and the first protective layer are made of nitride.
Furthermore, the first side wall and the first protective layer are made of silicon carbonitride.
Furthermore, the second passivation layer is DUO.
Furthermore, the thickness of the second protective layer is between 100nm and 200 nm.
Further, step S3 is to uniformly laminate a film on the first protective layer by using a film lamination process to form a uniform material that can be used as the second protective layer, and then perform a heat treatment process through a heat treatment process to form a dense surface material with an oxidation-resistant and acid-corrosion-resistant surface layer.
Further, the temperature of the heat treatment is between 200 and 250 ℃.
The present invention further provides a back of wafer protection layer, wherein the back of wafer is a surface of a wafer, the wafer further includes a first surface opposite to the back of wafer, a gate structure of a semiconductor device is formed on the first surface, and first sidewalls are formed on two sides of the gate structure, and the back of wafer protection layer is characterized in that: the crystal back protective layer is including being located the first layer protective layer on the crystal back and being located the second layer protective layer on the first layer protective layer, the material of first layer protective layer with the material of first side wall is the same, second layer protective layer is corrosion-resistant, anti-oxidation material.
Furthermore, the second passivation layer is DUO.
Furthermore, the thickness of the second protective layer is between 100nm and 200 nm.
Therefore, after the first side wall and the first protective layer of the semiconductor device are formed, a protective layer with strong oxidation resistance and corrosion resistance is additionally arranged on the crystal back, so that in the subsequent process flow, the protective layer with strong oxidation resistance and corrosion resistance protects the crystal back from being corroded or oxidized, such as DUO, and only a few chemical solvents can be removed, so that the material of the crystal back cannot be damaged even after multiple times of crystal back pickling, the purpose of stabilizing the state of the crystal back is achieved, the characteristic that the first protective layer (such as SiCN) on the surface layer of the crystal back is easy to oxidize and then corroded by acid is changed, the smooth crystal back is obtained, the stability of a product during the running of a photoetching machine is improved, and the yield of the semiconductor device is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor integrated circuit manufacturing process according to an embodiment of the present invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on …," "adjacent …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent …," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "under …", "over …", "over" and the like may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In an embodiment of the present invention, a method for preventing backside contamination includes: s1: providing a wafer, wherein the wafer comprises a first surface and a wafer back opposite to the first surface; s2: forming a grid structure of a semiconductor device on a first surface of a wafer, then forming a first side wall of the grid structure, and simultaneously forming a first protective layer on a wafer back while forming the first side wall, wherein the material of the first protective layer is the same as that of the first side wall; and S3: after step S2, a second protective layer is formed over the first protective layer on the back of the wafer, wherein the second protective layer is a corrosion-resistant, oxidation-resistant material.
Specifically, referring to fig. 1, fig. 1 is a schematic diagram of a semiconductor integrated circuit manufacturing process according to an embodiment of the invention. The method for preventing the back contamination of the wafer according to an embodiment of the present invention includes:
s1: providing a wafer 100, wherein the wafer 100 includes a first surface 110 and a back side 120 opposite to the first surface 110;
s2: forming a gate structure 111 of a semiconductor device on a first surface 110 of a wafer, then forming a first side wall (spacer 1) 112 of the gate structure 111, and simultaneously forming a first protective layer 121 on a wafer back 120 while forming the first side wall 112, wherein the material of the first protective layer 121 is the same as that of the first side wall 112;
in one embodiment, the gate structure 111 includes a gate dielectric layer 1111 and a gate conductive material layer 1112 stacked in sequence. Typically, the gate dielectric layer 1111 is silicon dioxide or a high dielectric constant material; the gate conductive material layer 1112 is a polysilicon gate.
In one embodiment, the first sidewall 112 is formed in a self-aligned manner on both sides of the gate structure 111.
In an embodiment, the first sidewall spacers 112 and the first protection layer 121 are made of nitride. Specifically, the first sidewall 112 and the first protection layer 121 are made of silicon carbide nitride (SICN).
S3: after step S2, a second protective layer 122 is further formed on the first protective layer 121 on the back side 120, wherein the second protective layer 122 is a corrosion-resistant and oxidation-resistant material.
Wherein, the corrosion-resistant and oxidation-resistant material is a material with infinite corrosion resistance and oxidation resistance. In one embodiment, the second passivation layer 122 is made of DUO.
In one embodiment, the thickness of the second protection layer 122 is between 100nm and 200 nm.
In one embodiment, the second protective layer 122 is formed by first spin-coating a material that can be used as the second protective layer 122 on the first protective layer 121, and then heating.
In one embodiment, a film is uniformly laminated on the first passivation layer 121 by a film lamination process to form a uniform material that can be used as the second passivation layer 122, and then a thermal treatment process is performed through a thermal treatment process to form a dense surface material with oxidation resistance and acid corrosion resistance on the surface layer, thereby achieving the purpose of protecting the back side 120. In an embodiment, the temperature of the heat treatment is between 200 degrees celsius and 250 degrees celsius, and specifically about 225 degrees celsius.
In one embodiment, a layer of amorphous silicon (a-Si) is included between the back side 120 and the first protective layer 121.
As described above, after the first sidewall and the first protective layer of the semiconductor device are formed, a protective layer with strong oxidation resistance and corrosion resistance is newly added on the back of the wafer, so that in the subsequent process flow, the protective layer with strong oxidation resistance and corrosion resistance protects the back of the wafer from corrosion or oxidation, such as DUO, which can be removed only by a few chemical solvents, so that the back of the wafer is not damaged even after multiple times of back of the wafer pickling, thereby achieving the purpose of stabilizing the state of the back of the wafer.
In an embodiment, referring to fig. 1, a back side protection layer is provided, wherein the back side 120 is a side of a wafer 100, the wafer 100 further includes a first side 110 opposite to the back side 120, a gate structure 111 of a semiconductor device is formed on the first side 110, first side walls (spacer 1) 112 are formed on two sides of the gate structure 111, the back side protection layer includes a first protection layer 121 located on the back side 120 and a second protection layer 122 located on the first protection layer 121, the first protection layer 121 is made of the same material as the first side wall (spacer 1) 112, and the second protection layer 122 is made of a corrosion-resistant and oxidation-resistant material.
Wherein the corrosion-resistant and oxidation-resistant material is a material with infinite corrosion resistance and oxidation resistance. In one embodiment, the second passivation layer 122 is made of DUO.
In one embodiment, the thickness of the second protection layer 122 is between 100nm and 200 nm.
In one embodiment, a layer of amorphous silicon (a-Si) is included between the back side 120 and the first protective layer 121.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not depart from the spirit of the corresponding technical solutions of the embodiments of the present invention.
Claims (7)
1. A method for preventing backside contamination, comprising:
s1: providing a wafer, wherein the wafer comprises a first surface and a wafer back opposite to the first surface;
s2: forming a grid structure of a semiconductor device on a first surface of a wafer, then forming a first side wall of the grid structure, and simultaneously forming a first protective layer on a wafer back while forming the first side wall, wherein the material of the first protective layer is the same as that of the first side wall; and
s3: after step S2, forming a second protective layer on the first protective layer on the back of the wafer, wherein the second protective layer is a corrosion-resistant and oxidation-resistant material;
and S3, uniformly laminating a film on the first protective layer by using a film laminating process to form a layer of uniform material which can be used as the second protective layer, and then performing a heat treatment process through a heat treatment process to form a layer of compact surface material with oxidation resistance, acid corrosion resistance and a compact surface layer, wherein the second protective layer is made of DUO.
2. The method according to claim 1, wherein the first sidewall spacers and the first protective layer are made of nitride.
3. The method according to any one of claims 1 or 2, wherein the first sidewall spacer and the first protective layer are made of silicon carbonitride.
4. The method according to claim 1, wherein the thickness of the second protective layer is between 100nm and 200 nm.
5. The method according to claim 1, wherein the temperature of the heat treatment is between 200 ℃ and 250 ℃.
6. The utility model provides a crystal back protective layer, wherein the crystal back is the one side of wafer, the wafer still include with the crystal back is first face relatively the grid structure that is formed with semiconductor device on the first face is formed with first side wall, its characterized in that in the both sides of grid structure: the back of crystal protective layer is including being located the first layer protective layer on the back of crystal and being located the second floor protective layer on the first layer protective layer, the material of first layer protective layer with the material of first side wall is the same, the material of second floor protective layer is DUO, utilizes the press mold technology to be in uniformly press mold formation one deck is even can be used to do on the first layer protective layer the material of second floor protective layer, then carries out the heat treatment process through the heat treatment flow, forms the surface course material that the oxidation resistance of one deck is dense and acid corrosion resistance.
7. The backside protection layer of claim 6, wherein the thickness of the second protection layer is between 100nm and 200 nm.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010971579.1A CN112201577B (en) | 2020-09-16 | 2020-09-16 | Method for preventing wafer back pollution and wafer back protection layer |
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| CN202010971579.1A CN112201577B (en) | 2020-09-16 | 2020-09-16 | Method for preventing wafer back pollution and wafer back protection layer |
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| CN112201577A CN112201577A (en) | 2021-01-08 |
| CN112201577B true CN112201577B (en) | 2023-02-03 |
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| JP3811697B2 (en) * | 2003-11-19 | 2006-08-23 | 松下電器産業株式会社 | Manufacturing method of semiconductor device |
| CN102800699B (en) * | 2011-05-25 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| KR102099712B1 (en) * | 2013-01-15 | 2020-04-10 | 삼성전자주식회사 | Method of forming a pattern and method of manufacturing a semiconductor device using the same |
| US20150079739A1 (en) * | 2013-09-16 | 2015-03-19 | United Microelectronics Corp. | Method for manufacturing semiconductor substrate |
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