CN112199317A - Bridging system and bridging method for RISCV processor to access Flash memory - Google Patents
Bridging system and bridging method for RISCV processor to access Flash memory Download PDFInfo
- Publication number
- CN112199317A CN112199317A CN202011163715.0A CN202011163715A CN112199317A CN 112199317 A CN112199317 A CN 112199317A CN 202011163715 A CN202011163715 A CN 202011163715A CN 112199317 A CN112199317 A CN 112199317A
- Authority
- CN
- China
- Prior art keywords
- icb
- spi
- flash memory
- signal
- riscv
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 13
- 230000003993 interaction Effects 0.000 claims abstract description 21
- 238000012545 processing Methods 0.000 claims abstract description 16
- 230000000977 initiatory effect Effects 0.000 claims abstract description 4
- 230000002452 interceptive effect Effects 0.000 claims description 16
- 238000006243 chemical reaction Methods 0.000 claims description 10
- 238000005070 sampling Methods 0.000 claims description 6
- 238000013507 mapping Methods 0.000 claims description 3
- 230000004044 response Effects 0.000 claims description 2
- 238000013461 design Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 9
- 230000001360 synchronised effect Effects 0.000 description 6
- 230000007704 transition Effects 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 2
- 238000012952 Resampling Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 238000013475 authorization Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Information Transfer Systems (AREA)
Abstract
The invention provides a bridging system and a bridging method for accessing a Flash memory by an RISCV processor, which can realize the high-speed reading of the Flash memory data by the RISCV processor. The bridging system includes: the RISCV processor adopts a self-defined ICB bus protocol; a Flash memory bus interface, wherein the Flash memory adopts an SPI bus protocol; the ICB control module is used for processing bus transactions initiated by the RISCV processor; the SPI bus module is used for initiating a bus transaction request to the Flash memory; and the ICB-SPI interaction module is used for realizing the signal interaction of the ICB control module and the SPI control module. Due to the design of the asynchronous circuit, the RISCV processor and the Flash memory can work under respective highest frequency, and the working efficiency of the whole system is ensured. Compared with the traditional bridge module, the invention does not need asynchronous FIFO to complete the cross-clock domain signal processing, and can reduce the area consumption of the bridge module.
Description
Technical Field
The invention relates to a bridge system and a bridge method for a RISCV processor to access a Flash memory, relating to the field of system on chip (SoC) data transmission.
Background
After the processor is powered on, a fixed initialization program called a BIOS (basic input output system) program needs to be read, and the BIOS program can help the processor to complete power-on self-test and most basic configuration. The BIOS program is usually fixed in a Read Only Memory (ROM), but a high-speed parallel bus is usually adopted in the processor, a low-speed serial bus is usually adopted in the memory, different bus protocols are incompatible, and the processor cannot be directly connected with the memory to complete reading of memory data. Therefore, a bridge module is required to be added in the processor to realize the conversion between the processor bus protocol and the memory bus protocol.
In the prior art, the RISCV processor and the Flash memory cannot be interconnected, the traditional bridge module needs to finish cross-clock domain signal processing by means of asynchronous FIFO, and the area consumption of the bridge module is large.
Disclosure of Invention
The purpose of the invention is as follows: it is an object to provide a bridge system for RISCV processor to access Flash memory to solve the above problems of the prior art. A further object is to propose a bridging method based on the above system.
The technical scheme is as follows: a RISCV processor access Flash memory bridge system comprising a RISCV processor interface: the bridge module is used as a slave device of the RISCV processor and is connected with the ICB bus; flash memory interface: the bridging module is used as a main device of the Flash memory and is connected with the SPI bus; an ICB control module: the RISCV processor is used for processing read transactions initiated by the RISCV processor, responding to the RISCV processor according to an ICB bus protocol, and registering read control information and read address information; an SPI control module: the system is used for initiating a read transaction to the Flash memory and analyzing and storing data returned by the Flash memory according to an SPI protocol; ICB-SPI interactive module: and processing the control signal and the address signal of the ICB control module and then sending the processed signals to the SPI control module, and processing the control signal and the data signal of the SPI control module and then sending the processed signals to the ICB control module.
In a further embodiment, the bridge module is used as a slave device of the ICB bus, and the ICB control module analyzes a read control signal and an address signal of the ICB bus under the control of the ICB state machine, and returns data to the RISCV processor after receiving a read data valid signal sent by the ICB-SPI interaction module.
In a further embodiment, the bridge module is used as a master device of the SPI bus, and the SPI control module initiates a read control signal and an address signal to the SPI and receives data returned by the memory after receiving a start signal sent by the ICB-SPI interaction module under the control of the SPI state machine.
In a further embodiment, the bridge module is designed by adopting an asynchronous circuit, the ICB control module works under a clock domain of the RISCV processor (high clock frequency), and the SPI control module works under a clock domain of the Flash memory (low clock frequency), so that the RISCV processor and the Flash memory can respectively work under respective highest working frequencies, and the running efficiency of the whole SoC system can be ensured.
In a further embodiment, clock domain crossing processing of asynchronous signals is performed on an ICB start signal and an SPI end signal; the address signal is updated only when the ICB starting signal is effective, and the address signal is in a stable state when the SPI clock domain samples; the data signal is updated only when the SPI end signal is active, and the data signal is in a steady state when sampled in the ICB clock domain.
In a further embodiment, the ICB-SPI interaction module implements mapping of control signals: converting a read enable signal of the ICB bus into an 8-bit read operation code of the SPI bus; serial-to-parallel conversion of control signals and address signals: inputting 8-bit control signals and 24-bit address signals of a Flash memory in parallel and outputting the signals in series; parallel-to-serial conversion of data signals: receiving 32bit data serial input and parallel output returned by a Flash memory; asynchronous signal clock domain crossing processing: the start signal is synchronized from the ICB clock domain to the SPI clock domain, and the end signal is synchronized from the SPI signal to the ICB clock domain.
A bridge method for accessing Flash memory by RISCV processor includes the following steps:
and 5, converting the control signals, the address signals and the data signals of the ICB control module and the SPI control module through the ICB-SPI interactive module.
The bridge module for accessing the Flash memory by the RISCV processor is further designed in that the ICB control module comprises 3 working states: when a reading request initiated by the RISCV processor is received, registering a reading address signal of an ICB bus and generating an ICB starting signal; when an ICB ending signal of the ICB-SPI interactive module is sampled, sampling the read data of the interactive module, and assembling the read data on a read data bus of an ICB bus; and after receiving the read response signal sent by the RISCV processing, the ICB control module completes one read operation and waits for the RISCV processor to initiate the next read request.
The bridge module for the RISCV processor to access the Flash memory is further designed in that the SPI control module comprises 3 working states: after an SPI starting signal of the ICB-SPI interactive module is sampled, the control operation code and the address signal are sent within 32 clock cycles; after the control signal and the address signal are sent, a register sent by a Flash memory is received, 32 clock cycles are continued, and 32bit data are received; and after the data reading and sampling are finished, the SPI control module finishes one-time access to the Flash memory and waits for the next SPI starting signal of the ICB-SPI interaction module.
The bridge module for the Flash memory between the RISCV processor is further designed in that the ICB-SPI interaction module can synchronize an ICB starting signal to an SPI clock domain to obtain an SPI starting signal and synchronize an SPI ending signal to an ICB clock domain to obtain an ICB ending signal; the interactive module realizes the parallel input and serial output of the address signals through the shift register; the interaction module realizes serial input and parallel output of the read data signals through the shift register.
Has the advantages that: the high-efficiency protocol conversion bridge module provided by the invention can greatly reduce the development difficulty of the RISCV processor and realize the high-speed reading of the RISCV processor to the Flash memory. Due to the design of the asynchronous circuit, the RISCV processor and the Flash memory can work under respective highest frequency, and the working efficiency of the whole system is ensured. Compared with the traditional bridge module, the invention does not need asynchronous FIFO to complete the cross-clock domain signal processing, and can reduce the area consumption of the bridge module.
Drawings
FIG. 1 is a timing diagram of an ICB bus protocol read operation of the RISCV processor.
Fig. 2 is a timing diagram of an SPI bus protocol read operation of the Flash memory.
FIG. 3 is a diagram of the interconnection structure of the RISCV processor and the Flash memory.
FIG. 4 is a schematic diagram of the overall structure of the ICB-SPI bus bridge module.
FIG. 5 is an ICB control module state transition diagram.
FIG. 6 is a SPI control module state transition diagram.
FIG. 7 is a schematic diagram of the SPI-ICB end signal synchronization circuit.
FIG. 8 is a schematic diagram of an ICB-SPI enable signal synchronization circuit.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
The RISCV processor has the characteristics of low cost and automatic controllability (without various authorizations), and compared with the processor with the traditional architecture, the RISCV architecture is simpler, and the open source characteristic enables us to modify the hardware architecture of the processor, so that the RISCV processor can adapt to the rapid development in the fields of Internet of things, cloud computing and artificial intelligence. The RISCV processor uses an ICB bus, the ICB bus is a self-defined high-speed bus and is provided with two independent channels, a command channel is used for sending address and control information, a return channel is used for returning a read-write operation result, and each channel is subjected to handshake control through valid and ready signals; separate address and data phases are used; addressing by adopting an address interval, and supporting any number of master-slave numbers; address non-aligned data access is supported.
The first embodiment is as follows:
the read timing diagram for the ICB bus is shown in fig. 1.
The Flash memory usually adopts an SPI bus interface, and the SPI is a serial peripheral interface, so that the Flash memory has the characteristics of synchronous transmission, high transmission rate, full duplex support and simple communication mode. The SPI bus is only composed of 1 clock line, 1 chip selection line and 2 data lines, so that the pin requirement of the processor can be greatly reduced, and the area of the processor is reduced. The SPI bus master and slave devices all transmit data on the falling edge, the rising edge completes data sampling, and the read sequence of the Flash memory is as shown in fig. 2. The RISCV processor accesses the bridge module of the Flash memory, is connected with the ICB bus of the RISCV processor through the ICB bus interface and is connected with the external Flash memory through the SPI bus interface, and the bridge module is used as a module of the RISCV processor SoC to realize the chip-to-chip interconnection of the RISCV processor and the Flash memory. The interconnect structure is shown in fig. 3.
The hardware implementation of the bridge module for accessing the Flash memory by the RISCV processor of the embodiment includes: a RISCV processor interface; a Flash memory interface; an ICB control module; an SPI control module; ICB-SPI interactive module. The overall structure of the bridge module is shown in fig. 4.
The bridge system is used as a slave device of the ICB bus, the ICB control module analyzes a reading control signal and an address signal of the ICB bus under the control of the ICB state machine, and returns data to the RISCV processor after receiving a valid reading data signal sent by the ICB-SPI interactive module. The bridge module is used as a main device of the SPI bus, and the SPI control module initiates a read control signal and an address signal to the SPI and receives data returned by the memory after receiving a starting signal sent by the ICB-SPI interaction module under the control of the SPI state machine.
The bridge module is designed by adopting an asynchronous circuit, the ICB control module works under the clock domain of the RISCV processor (the clock frequency is high), and the SPI control module works under the clock domain of the Flash memory (the clock frequency is low), so that the RISCV processor and the Flash memory can respectively work under the respective highest working frequency, and the running efficiency of the whole SoC system can be ensured. Performing clock domain crossing processing on asynchronous signals on an ICB starting signal and an SPI ending signal; the address signal is updated only when the ICB starting signal is effective, and the address signal is in a stable state when the SPI clock domain samples; the data signal is updated only when the SPI end signal is active, and the data signal is in a steady state when sampled in the ICB clock domain. The ICB-SPI interactive module realizes the mapping of control signals: converting a read enable signal of the ICB bus into an 8-bit read operation code of the SPI bus; serial-to-parallel conversion of control signals and address signals: inputting 8-bit control signals and 24-bit address signals of a Flash memory in parallel and outputting the signals in series; parallel-to-serial conversion of data signals: receiving 32bit data serial input and parallel output returned by a Flash memory; asynchronous signal clock domain crossing processing: the start signal is synchronized from the ICB clock domain to the SPI clock domain, and the end signal is synchronized from the SPI signal to the ICB clock domain.
Example two:
the ICB control module mainly works under the drive of an ICB state machine, and the ICB state machine comprises three states of ICB _ IDLE, ICB _ REQ and ICB _ WAIT: the ICB _ IDLE state is an initial state, when the RISCV processor initiates a read request, the state machine is converted into ICB _ REQ from ICB _ IDLE, the module registers a control signal and a read address signal and generates an ICB starting signal with 1 beat; when the ICB ending signal is effective, the state machine is converted into an ICB _ WAIT state from the ICB _ REQ, and the module returns read data on the ICB bus; when the RISCV processor samples the read data, the state machine transitions from ICB _ WAIT state to ICB _ IDLE state, waiting for the RISCV processor to initiate the next read request. The state transitions of the ICB state machine are shown in fig. 5.
The SPI control module mainly works under the drive of an SPI state machine, and the SPI state machine comprises three states of SPI _ IDLE, SPI _ SEND and SPI _ REC: the SPI _ IDLE state is an initial state, when an SPI starting signal is sampled, the state machine is converted into an SPI _ SEND state from the SPI _ IDLE state, and the module enables a control information and address information sending module; after the control information and the address information are sent, the state machine is changed from the SPI _ SEND state to the SPI _ REC state, and the module enables the data receiving module; after receiving 32bit (4 byte) data, the SPI state machine transitions from SPI _ REC to SPI _ IDLE state, waits for the next SPI start signal, and generates a beat of SPI end signal. The state transitions of the SPI state machine are shown in fig. 6.
And after the ICB control module is started, the ICB-SPI interaction module synchronizes a starting signal of the ICB clock domain to the SPI clock domain. Because the ICB bus clock frequency is higher than the SPI bus clock frequency, and the effective signal duration of the ICB clock domain is less than the SPI clock period, the phenomenon that the SPI clock cannot sample the ICB start signal may occur, resulting in data loss. Therefore, the ICB starting signal needs to be subjected to broadening processing, in an ICB clock domain, after the ICB starting signal is sampled to be effective, a signal 1 starts to be effective, a signal 2 is obtained by performing two-stage register synchronization on the signal 1 in an SPI clock domain, a signal 3 is obtained by synchronizing the signal 2 in the ICB clock domain, after the signal 3 is sampled to be effective, the signal 1 returns to an invalid state, and the ICB starting signal is synchronized to the SPI clock domain in a handshake mode of the signal 1 and the signal 3. The synchronization circuit for the ICB enable signal is shown in fig. 7.
The ICB-SPI interaction module synchronizes an ending signal of the SPI clock domain to the ICB clock domain after the SPI control module finishes working, and because the ICB clock frequency is higher than the SPI bus clock frequency, the effective signal duration of the SPI clock domain is more than the ICB clock period, the ICB clock can sample the SPI ending signal twice (or more than twice), and the problem of data resampling occurs. In order to avoid the generation of a metastable state phenomenon of an asynchronous circuit, a two-stage register is adopted to complete synchronization of signals to obtain a signal 1, the signal 1 is registered to obtain a signal 2, and the signal 1 and the signal 2 are subjected to combinational logic operation to generate a pulse signal with the duration of 1 ICB clock period. The synchronization circuit for the SPI end signal is shown in fig. 8.
Example three:
based on the first embodiment and the second embodiment, the specific working process of the invention is as follows: the interconnection between the RISCV processor and the bridge module is realized through the RISCV processor bus interface. And the interconnection between the Flash memory and the bridging module is realized through a Flash memory bus interface. And the ICB control module receives and responds to a read request initiated by the RISCV processor according to the ICB bus protocol requirement and returns data of a corresponding address of the Flash memory.
After a read request initiated by the RISCV processor, the ICB control module is started to analyze and register the address and control signal of the ICB bus, the generated ICB start signal is processed asynchronously by the ICB-SPI interaction module to obtain an SPI start signal, the SPI start signal can start the SPI control module, the SPI control module sends a read operation code and a read address to the Flash memory and receives data returned by the Flash memory, an SPI end signal is generated after 32-bit data are sampled, the SPI end signal is processed asynchronously by the ICB-SPI interaction module to obtain an ICB end signal, the ICB control module loads read data onto the ICB bus, and one-time read operation is finished after the RISCV processor reads the data on the bus.
And the SPI control module initiates a read request to the Flash memory according to the requirements of the SPI bus protocol and acquires data of the address corresponding to the Flash memory.
The conversion of control signals, address signals and data signals of the ICB control module and the SPI control module is realized through the ICB-SPI interaction module. And after the SPI starting signal of the ICB-SPI interactive module is sampled, the control operation code and the address signal are sent within 32 clock cycles. After the control signal and the address signal are sent, a register sent by a Flash memory is received, 32 clock cycles are continued, and 32bit data are received; and after the data reading and sampling are finished, the SPI control module finishes one-time access to the Flash memory and waits for the next SPI starting signal of the ICB-SPI interaction module.
In a word, the invention introduces a bridge system and a bridge method for accessing a Flash memory by a RISCV processor, and the high-efficiency protocol conversion bridge module provided by the invention can greatly reduce the development difficulty of the RISCV processor, realize the high-speed reading of the Flash memory by the RISCV processor and achieve the time of completing one 32-bit data reading of 6.74 us. Due to the design of the asynchronous circuit, the RISCV processor and the Flash memory can work under respective highest frequencies, the working frequency of the RISCV processor can reach 50MHz and the working frequency of the Flash memory can reach 10MHz under the FPGA, and the working efficiency of the whole system is ensured. Compared with the traditional bridge module, the invention does not need asynchronous FIFO to complete the cross-clock domain signal processing, can reduce the area consumption of the bridge module, and the area is only 133.7 after the integration under the TSMC28nm process library
。
As noted above, while the present invention has been shown and described with reference to certain preferred embodiments, it is not to be construed as limited thereto. Various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A bridge system for accessing Flash memory by RISCV processor is characterized by comprising the following modules:
the RISCV processor bus interface realizes the interconnection of the RISCV processor and the bridge module;
a Flash memory bus interface for realizing the interconnection of the Flash memory and the bridging module;
the ICB control module receives and responds to a read request initiated by the RISCV processor according to the requirements of an ICB bus protocol and returns data of a corresponding address of the Flash memory;
the SPI control module initiates a read request to the Flash memory according to the requirements of the SPI bus protocol and acquires data of the address corresponding to the Flash memory;
and the ICB-SPI interaction module is used for converting control signals, address signals and data signals of the ICB control module and the SPI control module.
2. The bridge system for RISCV processor to access Flash memory of claim 1, wherein said bridge system is a slave device of ICB bus, and the ICB control module analyzes the read control signal and address signal of ICB bus under the control of ICB state machine, and returns the data to RISCV processor after receiving the valid signal of read data sent by ICB-SPI interactive module.
3. The bridge system for RISCV processor to access Flash memory according to claim 1, wherein said bridge system is used as a master device of SPI bus, and SPI control module initiates read control signal and address signal to SPI and receives data returned from memory after receiving start signal sent by ICB-SPI interactive module under control of SPI state machine.
4. The RISCV processor Flash memory bridge system of claim 1, wherein the ICB control module operates under the RISCV processor clock domain and the SPI control module operates under the Flash memory clock domain.
5. The bridge system for RISCV processor to access Flash memory of claim 4, wherein the ICB start signal and SPI end signal are processed asynchronously across clock domains; the address signal is updated only when the ICB starting signal is effective, and the address signal is in a stable state when the SPI clock domain samples; the data signal is updated only when the SPI end signal is active, and the data signal is in a steady state when sampled in the ICB clock domain.
6. The bridge system for RISCV processor to access Flash memory of claim 1 or 5, wherein said ICB-SPI interaction module implements control signal mapping, converting ICB bus read enable signal into SPI bus 8-bit read operation code;
the serial-parallel conversion of the control signal and the address signal inputs and outputs the 8-bit control signal and the 24-bit address signal of the Flash memory in parallel and in serial;
the parallel-serial conversion of the data signals further comprises receiving 32bit data serial input and parallel output returned by the Flash memory;
the asynchronous signal cross-clock domain processing further includes synchronizing the start signal from the ICB clock domain to the SPI clock domain and synchronizing the end signal from the SPI signal to the ICB clock domain.
7. A bridge method for accessing Flash memory by RISCV processor is characterized by comprising the following steps:
step 1, realizing the interconnection of an RISCV processor and the bridge module through an RISCV processor bus interface;
step 2, realizing the interconnection between the Flash memory and the bridging module through a Flash memory bus interface;
step 3, receiving and responding to a read request initiated by the RISCV processor according to the ICB bus protocol requirement, and returning to the ICB control module of the data of the corresponding address of the Flash memory;
step 4, initiating a read request to the Flash memory according to the requirements of the SPI bus protocol, and acquiring the data of the address corresponding to the Flash memory;
and 5, converting the control signals, the address signals and the data signals of the ICB control module and the SPI control module through the ICB-SPI interactive module.
8. The bridge method for RISCV processor to access Flash memory of claim 7, wherein said ICB control module includes 3 working states:
when a reading request initiated by the RISCV processor is received, registering a reading address signal of an ICB bus and generating an ICB starting signal;
when an ICB ending signal of the ICB-SPI interactive module is sampled, sampling the read data of the interactive module, and assembling the read data on a read data bus of an ICB bus;
and after receiving the read response signal sent by the RISCV processing, the ICB control module completes one read operation and waits for the RISCV processor to initiate the next read request.
9. The bridge method for RISCV processor to access Flash memory of claim 7, wherein said SPI control module comprises 3 working states:
after an SPI starting signal of the ICB-SPI interactive module is sampled, the control operation code and the address signal are sent within 32 clock cycles;
after the control signal and the address signal are sent, a register sent by a Flash memory is received, 32 clock cycles are continued, and 32bit data are received;
and after the data reading and sampling are finished, the SPI control module finishes one-time access to the Flash memory and waits for the next SPI starting signal of the ICB-SPI interaction module.
10. The bridge method for RISCV processor to access Flash memory of claim 7, wherein said ICB-SPI interaction module synchronizes ICB start signal to SPI clock domain to get SPI start signal, synchronizes SPI end signal to ICB clock domain to get ICB end signal; the interaction module realizes parallel input and serial output of address signals through a shift register; the interaction module realizes serial input and parallel output of the read data signals through the shift register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011163715.0A CN112199317B (en) | 2020-10-27 | 2020-10-27 | Bridging system and bridging method for RISCV processor to access Flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011163715.0A CN112199317B (en) | 2020-10-27 | 2020-10-27 | Bridging system and bridging method for RISCV processor to access Flash memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112199317A true CN112199317A (en) | 2021-01-08 |
| CN112199317B CN112199317B (en) | 2022-10-18 |
Family
ID=74011632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011163715.0A Active CN112199317B (en) | 2020-10-27 | 2020-10-27 | Bridging system and bridging method for RISCV processor to access Flash memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112199317B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114115443A (en) * | 2021-10-26 | 2022-03-01 | 山东云海国创云计算装备产业创新中心有限公司 | Clock domain-crossing data signal synchronization method, system, equipment and medium |
| CN116259347A (en) * | 2023-05-16 | 2023-06-13 | 上海灵动微电子股份有限公司 | Programming device of embedded flash memory based on SPI protocol |
| CN117312210A (en) * | 2023-11-29 | 2023-12-29 | 沐曦集成电路(南京)有限公司 | Method for expanding performance of RISC-V processor |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101145140A (en) * | 2007-07-11 | 2008-03-19 | 南京大学 | Dynamic self-adaptive bus arbiter based on microprocessor-on-chip |
| US20090228224A1 (en) * | 2005-01-27 | 2009-09-10 | Electro Industries/Gauge Tech. | Intelligent electronic device with enhanced power quality monitoring and communications capabilities |
| CN101819560A (en) * | 2009-02-27 | 2010-09-01 | 杭州晟元芯片技术有限公司 | Method and device for executing program of SPI interface memory |
| CN101901202A (en) * | 2010-07-29 | 2010-12-01 | 东莞市泰斗微电子科技有限公司 | Circuit and method for cross clock domain accessing of AHB bus equipment to APB bus equipment |
| US20190370205A1 (en) * | 2018-06-01 | 2019-12-05 | Hewlett Packard Enterprise Development Lp | Low speed bus interface |
| CN111666242A (en) * | 2020-06-09 | 2020-09-15 | 湖南泽天智航电子技术有限公司 | Multi-channel communication system based on FT platform LPC bus |
-
2020
- 2020-10-27 CN CN202011163715.0A patent/CN112199317B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090228224A1 (en) * | 2005-01-27 | 2009-09-10 | Electro Industries/Gauge Tech. | Intelligent electronic device with enhanced power quality monitoring and communications capabilities |
| CN101145140A (en) * | 2007-07-11 | 2008-03-19 | 南京大学 | Dynamic self-adaptive bus arbiter based on microprocessor-on-chip |
| CN101819560A (en) * | 2009-02-27 | 2010-09-01 | 杭州晟元芯片技术有限公司 | Method and device for executing program of SPI interface memory |
| CN101901202A (en) * | 2010-07-29 | 2010-12-01 | 东莞市泰斗微电子科技有限公司 | Circuit and method for cross clock domain accessing of AHB bus equipment to APB bus equipment |
| US20190370205A1 (en) * | 2018-06-01 | 2019-12-05 | Hewlett Packard Enterprise Development Lp | Low speed bus interface |
| CN111666242A (en) * | 2020-06-09 | 2020-09-15 | 湖南泽天智航电子技术有限公司 | Multi-channel communication system based on FT platform LPC bus |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114115443A (en) * | 2021-10-26 | 2022-03-01 | 山东云海国创云计算装备产业创新中心有限公司 | Clock domain-crossing data signal synchronization method, system, equipment and medium |
| CN116259347A (en) * | 2023-05-16 | 2023-06-13 | 上海灵动微电子股份有限公司 | Programming device of embedded flash memory based on SPI protocol |
| CN117312210A (en) * | 2023-11-29 | 2023-12-29 | 沐曦集成电路(南京)有限公司 | Method for expanding performance of RISC-V processor |
| CN117312210B (en) * | 2023-11-29 | 2024-03-12 | 沐曦集成电路(南京)有限公司 | Method for expanding performance of RISC-V processor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112199317B (en) | 2022-10-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112199317B (en) | Bridging system and bridging method for RISCV processor to access Flash memory | |
| US5265216A (en) | High performance asynchronous bus interface | |
| CN109032973B (en) | ICB bus system | |
| WO2016192217A1 (en) | Apb bus bridge | |
| CN111290986A (en) | Bus interconnection system based on neural network | |
| US7590146B2 (en) | Information processing unit | |
| JP2003143117A (en) | Data synchronization circuit and communication interface circuit | |
| CN112398877B (en) | Control signal conversion circuit, intellectual property core and system-level chip | |
| US6170027B1 (en) | LPC/ISA bridge and its bridging method | |
| WO2020087276A1 (en) | Big data operation acceleration system and chip | |
| CN117194289A (en) | Multi-channel reconfigurable data transmission device based on FMQL | |
| CN115220528B (en) | Clock obtaining method, device, chip, electronic equipment and storage medium | |
| CN113918497B (en) | System, method and server for optimizing AHB bus data transmission performance | |
| CN218068843U (en) | Bridging circuit structure for converting AXI master port into APB slave port and SOC system | |
| CN116429259A (en) | Spectral processing system of fiber bragg grating | |
| CN115168264A (en) | Clock domain-crossing APB bus bridge and method thereof | |
| CN108228517A (en) | I3C circuit arrangements, system and communication means | |
| US20060018185A1 (en) | Memory control apparatus and electronic apparatus | |
| CN107562673B (en) | Bus protocol conversion bridging device applied to embedded processor | |
| CN111143269A (en) | Boundary clock window determining method, circuit, terminal equipment and storage medium | |
| CN219916336U (en) | LPC interface to AXI bus protocol bridge | |
| CN111339012B (en) | Processor system bus structure and system | |
| Herlev et al. | Open core protocol (OCP) clock domain crossing interfaces | |
| JPH07182274A (en) | Bus for information processor | |
| JPH09218846A (en) | Bus converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |