CN112185807B - Method for forming multi-wafer stacking structure - Google Patents
Method for forming multi-wafer stacking structure Download PDFInfo
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- CN112185807B CN112185807B CN202011065998.5A CN202011065998A CN112185807B CN 112185807 B CN112185807 B CN 112185807B CN 202011065998 A CN202011065998 A CN 202011065998A CN 112185807 B CN112185807 B CN 112185807B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02016—Backside treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02021—Edge treatment, chamfering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02035—Shaping
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Abstract
According to the method for forming the multi-wafer stacking structure, disclosed by the invention, the trimming process after the previous bonding is shifted to the step of filling the metal layer in the bonding hole before the next bonding, so that the edge clearance area caused by the previous bonding and the possible bad area formed between the filling metal layers in the bonding hole after the previous bonding and before the next bonding are not on the same plane, and the projection parts of the edge clearance area and the possible bad area are overlapped, the trimming width of the trimming process after shifting can be reduced, the effective area of the multi-wafer stacking structure is increased, the possible bad area is removed, and the bad generation (the formation of a copper ring in the forming process of the bonding pad) is avoided.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a method for forming a multi-wafer stacking structure.
Background
In some existing semiconductor processes, such as 3D-IC wafer bonding and subsequent wafer thinning processes, trimming (Trim) of the wafer is required to ensure the integrity and smoothness of the wafer edge.
And before bonding two adjacent wafers, performing primary trimming treatment on one of the wafers, bonding the two adjacent wafers, grinding and thinning the one wafer, and then adopting acid etching and a secondary trimming process to obtain an ideal edge.
In the process of stacking the polycrystalline wafers, the previous steps are repeated, and the bottom of each wafer added later needs to be completely supported when being ground, otherwise, the edges of two adjacent wafers in the grinding process are easy to break, so that each newly added wafer needs to be trimmed, the trimming width is wider, and the effective area of a chip is necessarily reduced. Meanwhile, as the trimming width of the wafer is continuously increased, the requirement on the control capability of the machine is higher. The traditional trimming process cannot meet the trimming requirement of bonding a plurality of wafers in terms of economic cost and process difficulty.
Disclosure of Invention
The invention aims to provide a method for forming a multi-wafer stacking structure, which reduces the trimming width of a wafer and improves the effective area of the wafer.
In order to achieve the above object, the present invention provides a method for forming a multi-wafer stack structure, comprising the steps of:
Step S1: bonding a first wafer with a front edge area subjected to trimming treatment with a bearing wafer, grinding and thinning the first wafer from the back surface of the first wafer to reserve the first wafer with partial thickness and form a first stacking structure, wherein the first stacking structure is in a boss shape,
wherein, the first stacking structure has an edge clearance area at the edge of the bonding surface of the bearing wafer and the first wafer;
step S2: forming a first bonding hole on the front surface of the first stacking structure, filling a first metal layer in the first bonding hole, covering the front surface of the first stacking structure with the first metal layer, trimming the edge area of the front surface of the first stacking structure to remove the edge clearance area of the first stacking structure, and flattening the first metal layer to form a first bonding pad;
step S3: bonding the second wafer with the front edge area subjected to trimming treatment with the first stacking structure, grinding and thinning the second wafer from the back surface of the second wafer to reserve the second wafer with partial thickness and form a second stacking structure, wherein the second stacking structure is in a boss shape,
The second stacking structure is electrically connected with the second wafer through the first bonding pad, and an edge clearance area exists at the edge of the bonding surface of the first stacking structure and the second wafer;
step S4: and trimming the front edge area of the second stacking structure, and removing the edge clearance area of the second stacking structure.
Optionally, step S1 includes:
providing a first wafer, trimming a front edge area of the first wafer, wherein the trimmed first wafer comprises a first base part and a first protruding part positioned on the first base part, and the edge trimming width of the first wafer is a first width;
providing a bearing wafer, bonding the first protruding part towards the front surface of the bearing wafer, wherein the projection of the first protruding part is completely located on the front surface of the bearing wafer;
thinning the first wafer from the back side grinding of the first wafer, removing the first base portion, and retaining a portion of the thickness of the first protruding portion.
Further, step S2 includes:
forming a photoresist layer on the front surface of the first stacking structure;
performing edge washing treatment on the photoresist layer to remove the photoresist layer at the edge of the first stacking structure, and performing patterning treatment on the photoresist layer, wherein the edge washing width of the photoresist layer is larger than the first width;
Etching the first stacking structure by taking the patterned photoresist layer as a mask to form a first bonding hole, and forming a concave region at the edge of the first stacking structure;
forming a first metal layer in the first bonding hole, wherein the first metal layer also covers the concave region;
performing edge washing treatment on the first metal layer;
trimming the front edge region of the first stacked structure to remove the edge gap region and the recessed region of the first stacked structure;
cleaning the first stacked structure through a cleaning process;
and flattening the first metal layer to form a first bonding pad.
Further, the recessed region includes a first recessed region and a second recessed region, the first recessed region is located in an edge region of the back surface of the first wafer, and the second recessed region is located in the front surface of the exposed carrier wafer of the first wafer.
Further, the width of the first recess region is smaller than the width of the edge gap region of the first stack structure, and the trimming width of the first stack structure is larger than the sum of the edge trimming width of the first wafer and the width of the edge gap region of the first stack structure.
Further, the edge washing width of the photoresist layer is the sum of the first width and the process deviation.
Further, the edge washing width of the first metal layer is larger than the edge washing width of the photoresist layer.
Further, the edge washing width of the first metal layer is the sum of the edge washing width of the photoresist layer and the process deviation.
Optionally, step S3 includes:
providing a second wafer, trimming the front edge area of the second wafer, wherein the trimming width of the second wafer is larger than that of the first stacking structure, and the trimmed second wafer comprises a second base part and a second protruding part positioned on the second base part;
bonding the second protruding part towards the front surface of the first stacking structure, and projecting the whole part of the second protruding part to the front surface of the first stacking structure;
thinning the second wafer from the backside grinding of the second wafer, removing the second base portion, and retaining a portion of the thickness of the second bump.
The invention also provides a method for forming the multi-wafer stacking structure, which comprises a bearing wafer and N wafers sequentially stacked on the bearing wafer, wherein N is more than or equal to 3, and N is a positive integer;
The forming method comprises the following steps:
step S1: bonding a first wafer with a front edge area subjected to trimming treatment with a bearing wafer, grinding and thinning the first wafer from the back surface of the first wafer to reserve the first wafer with partial thickness and form a first stacking structure, wherein the first stacking structure is in a boss shape,
wherein, the first stacking structure has an edge clearance area at the edge of the bonding surface of the bearing wafer and the first wafer;
step S2: forming a first bonding hole on the front surface of the first stacking structure, filling a first metal layer in the first bonding hole, covering the front surface of the first stacking structure with the first metal layer, trimming the edge area of the front surface of the first stacking structure to remove the edge clearance area of the first stacking structure, and flattening the first metal layer to form a first bonding pad;
step S3: bonding the second wafer with the front edge area subjected to trimming treatment with the first stacking structure, grinding and thinning the second wafer from the back surface of the second wafer to reserve the second wafer with partial thickness and form a second stacking structure, wherein the second stacking structure is in a boss shape,
The second stacking structure is electrically connected with the second wafer through the first bonding pad, and an edge clearance area exists at the edge of the bonding surface of the first stacking structure and the second wafer;
step S4: forming an (i-1) th bonding hole on the front surface of the (i-1) th stacking structure, filling an (i-1) th metal layer in the (i-1) th bonding hole, covering the front surface of the (i-1) th stacking structure with the (i-1) th metal layer, trimming the front surface edge area of the (i-1) th stacking structure to remove the edge gap area of the (i-1) th stacking structure, and flattening the (i-1) th metal layer to form an (i-1) th bonding pad;
step S5: bonding an ith wafer with a front edge area subjected to trimming treatment with the (i-1) stacking structure, grinding and thinning the ith wafer from the back surface of the ith wafer so as to keep part of the thickness of the ith wafer and form an ith stacking structure, wherein the ith stacking structure is in a boss shape,
the ith stacking structure is electrically connected with the ith wafer through the (i-1) bonding pad, an edge clearance area exists at the edges of bonding surfaces of the (i-1) stacking structure and the ith wafer, i is more than 2 and less than N-1, and i is a positive integer;
Step S6: forming an (N-2) th bonding hole on the front surface of the (N-2) th stacked structure, filling an (N-2) th metal layer in the (N-2) th bonding hole, covering the front surface of the (N-2) th stacked structure with the (N-2) th metal layer, trimming the front surface edge region of the (N-2) th stacked structure to remove the edge gap region of the (N-2) th stacked structure, and flattening the (N-2) th metal layer to form an (N-2) th bonding pad;
step S7: bonding the (N-1) th wafer with the front edge area subjected to trimming treatment with the (N-2) th stacking structure, grinding and thinning the (N-1) th wafer from the back surface of the (N-1) th wafer to reserve part of the thickness of the (N-1) th wafer and form the (N-1) th stacking structure, wherein the (N-1) th stacking structure is in a boss shape,
wherein the (N-1) th stacking structure is electrically connected with the (N-1) th wafer through the (N-2) th bonding pad, and an edge clearance area exists at the edges of bonding surfaces of the (N-2) th stacking structure and the (N-1) th wafer;
step S8: bonding an N-th wafer with a front edge area subjected to trimming treatment with an (N-1) -th stacking structure, grinding and thinning the N-th wafer from the back surface of the N-th wafer so as to keep the N-th wafer with partial thickness and form an N-th stacking structure, wherein the N-th stacking structure is in a boss shape, trimming the front edge area of the N-th stacking structure, and removing an edge clearance area of the N-th stacking structure.
Compared with the prior art, the invention has the following beneficial effects:
in the method for forming the multi-wafer stacking structure provided by the invention, the method comprises the following steps: step S1: bonding a first wafer with a front edge area subjected to trimming treatment with a bearing wafer, and grinding and thinning the first wafer from the back surface of the first wafer to reserve the first wafer with partial thickness and form a first stacking structure, wherein the first stacking structure is in a boss shape, and an edge clearance area exists at the edge of a bonding surface of the bearing wafer and the first wafer; step S2: forming a first bonding hole on the front surface of the first stacking structure, filling a first metal layer in the first bonding hole, covering the front surface of the first stacking structure with the first metal layer, trimming the edge area of the front surface of the first stacking structure to remove the edge clearance area of the first stacking structure, and flattening the first metal layer to form a first bonding pad; step S3: bonding a second wafer with a front edge area subjected to trimming treatment with the first stacking structure, and grinding and thinning the second wafer from the back surface of the second wafer to reserve the second wafer with partial thickness and form a second stacking structure, wherein the second stacking structure is in a boss shape and is electrically connected with the second wafer through the first bonding pad, and an edge clearance area exists at the edge of the bonding surface of the first stacking structure and the second wafer; step S4: and trimming the front edge area of the second stacking structure, and removing the edge clearance area of the second stacking structure. According to the invention, the edge clearance area is removed by trimming the first stacked structure between the step S1 and the step S2, and after the edge clearance area is pushed to the first metal layer filling in the step S2, as the edge clearance area is positioned on the bonding surface of the first wafer and the bearing wafer, the processes of forming the bonding hole of the first stacked structure, filling the first metal layer and the like are performed on the front surface of the first stacked structure, namely the thinned back surface of the first wafer, so that the bonding hole of the first stacked structure, the process of filling the first metal layer and the like are performed on the front surface edge area of the first stacked structure, and a possibly defective area is formed, wherein the area overlaps with the projection part of the edge clearance area of the first stacked structure, the trimming width of the trimming process can be reduced, the effective area of the polycrystalline wafer stacked structure is increased, the possibly defective area is also removed, and the generation of defects (the formation of a copper ring in the forming process of the bonding pad) is avoided.
Further, forming a photoresist layer on the front surface of the first stacking structure; performing edge washing treatment on the photoresist layer to remove the photoresist layer at the edge of the first stacking structure, and performing patterning treatment on the photoresist layer, wherein the edge washing width of the photoresist layer is larger than the first width; etching the first stacking structure by taking the patterned photoresist layer as a mask to form a first bonding hole, and forming a concave region at the edge of the first stacking structure; forming a first metal layer in the first bonding hole, wherein the first metal layer also covers the concave region; performing edge washing treatment on the first metal layer, wherein the edge washing width of the first metal layer is larger than that of the photoresist layer; trimming the front edge region of the first stacked structure to remove the edge gap region and the recessed region of the first stacked structure; cleaning the first stacked structure through a cleaning process; the first metal layer is planarized to form a first bond pad (claim 3). And trimming the first stacked structure between the step S1 and the step S2 to remove an edge clearance area, and pushing the first stacked structure to the edge cleaning treatment of the first metal layer to enable a concave area caused by the edge cleaning of the photoresist to overlap with a projection part of the edge clearance area, so that the trimming width of a trimming process is reduced.
Drawings
FIGS. 1a-1e are schematic diagrams illustrating steps of a method for forming a multi-wafer stack structure;
FIG. 2 is a flow chart illustrating a method for forming a multi-wafer stack structure according to an embodiment of the invention;
FIGS. 3a-3d are schematic cross-sectional views illustrating steps of a method for forming a multi-wafer stack structure according to a first embodiment of the present invention;
fig. 4a-4f are schematic cross-sectional views of the sub-steps in step S2 of fig. 3a after enlargement of the partial area a.
Reference numerals illustrate:
in fig. 1a-1 e:
10-bonding the wafer; 20-a photoresist layer; 11. 12-a recessed region; 31-a bonding hole; 32-bonding pads; an m-copper ring; w2-a second width;
in fig. 3a-4 f:
m1-an edge gap region of the first stack structure; w1-a first width;
100-a first stacked structure; 100 a-a front side of the first stack structure; 101-a first bonding hole; 102-a first metal layer; 103-a first bond pad;
110-carrying a wafer; 110 a-front side of the carrier wafer; 120-a first wafer; 120a—front side of the first wafer; 120 b-the back side of the first wafer; 121-a first boss; 122-metal interconnect structures; 123-a first recessed region; 111-a second recessed region; 124-dielectric layer;
200-photoresist layer;
300-a second stacked structure; 310-a second wafer; 310 a-the front side of the second wafer; 310 b-the backside of the second wafer; 311-second boss.
Detailed Description
In the current method for forming a stacked structure of multiple wafers, two adjacent wafers are trimmed after bonding to trim and remove an edge gap region occurring during bonding, and then bonding holes are formed in the front surfaces of the bonded wafers, so as to form bonding pads. The first wafer of the two wafers needs to be subjected to a trimming process before bonding, so that the trimming width of the front edge of the first wafer is a first width W1, and the trimming width of the bonded two wafers is a second width W2, (W1 < W2).
The bonding pad is formed as follows:
as shown in fig. 1a, first, the front surface of the bonded wafer 10 is coated with the photoresist layer 20, and since the surface of the photoresist layer 20 is affected by its own tension, the photoresist layer 20 has a hump near the position of the second width W2 from the edge of the wafer, the thickness of the photoresist at the hump is thicker, and a longer time is required in the subsequent photoresist layer 20 cleaning process, so that the photoresist layer 20 needs to be subjected to an edge cleaning process to remove the hump.
As shown in fig. 1b, the photoresist layer 20 is then subjected to an edge-washing process, and the photoresist layer 20 is patterned. The photoresist layer 20 has a width of the edge-washing greater than the second width W2, and the surface of the bonded wafer 10 in the width of the edge-washing is etched in the subsequent etching process for forming the bonding hole, and a recess region is formed, and the recess region may be defective (e.g., copper ring) in the subsequent process. Therefore, the recessed area needs to be removed in the subsequent trimming process, which causes waste of the edge position of the wafer, so that the effective area of the wafer is smaller.
As shown in fig. 1c, the photoresist layer 20 is patterned as a mask, and bonding holes 31 are etched to remove the photoresist layer 20. During etching, two recessed areas 11, 12 are present at the edge of the bonded wafer 10, wherein a first recessed area 11 is located at the edge area of the first wafer and a second recessed area 12 is located on the surface of the second wafer outside the first wafer.
As shown in fig. 1d and 1e, the bonding holes 31 are then filled with copper metal, and the copper on the edge of the bonded wafer 10 is washed away by a copper-edge process, and then the bonding pads 32 are formed by a CMP process. Since the metal copper also covers at least the first concave region 11, copper in the concave region will form a copper ring after planarization, and in order to avoid the formation of copper ring, a copper edge cleaning process must be performed to remove copper in the first concave region 11, in this process, the width of the exposed wafer edge is larger and larger, resulting in waste of the wafer edge position, and the copper edge cleaning process window is insufficient, which increases the process difficulty, and meanwhile, the copper at the edge position is missing due to the insufficient process window, resulting in waste of the wafer edge position.
Therefore, in the multi-wafer stacking process, the steps of stacking two adjacent wafers are repeated, and since the bottom of each new wafer needs to be fully supported in the subsequent wafer polishing process, otherwise, the edges of the polishing process are broken, and therefore, the edge gap area formed by the loss caused by the defect of the bonded wafer 10 and the loss caused by the trimming of the new wafer is further enlarged, so that the trimming width is wider and wider, and the effective area of the chip is necessarily reduced.
Based on the analysis, the invention provides a method for forming a multi-wafer stacking structure.
A method of forming a multi-wafer stack structure according to the present invention will be described in further detail. The present invention will be described in more detail below with reference to the attached drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It should be appreciated that in the development of any such actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as compliance with system-related or business-related constraints, which will vary from one implementation to another. In addition, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments accompanied with figures are described in detail below. It is noted that the drawings are in a very simplified form and utilize non-precise ratios, and are intended to facilitate a convenient, clear, description of the embodiments of the invention.
Fig. 2 is a flow chart of a method for forming a multi-wafer stack structure according to the present embodiment. As shown in fig. 2, the method for forming a multi-wafer stack structure according to the present embodiment includes the following steps:
step S1: bonding a first wafer with a front edge area subjected to trimming treatment with a bearing wafer, grinding and thinning the first wafer from the back surface of the first wafer to reserve the first wafer with partial thickness and form a first stacking structure, wherein the first stacking structure is in a boss shape,
wherein, the first stacking structure has an edge clearance area at the edge of the bonding surface of the bearing wafer and the first wafer;
step S2: forming a first bonding hole on the front surface of the first stacking structure, filling a first metal layer in the first bonding hole, covering the front surface of the first stacking structure with the first metal layer, trimming the edge area of the front surface of the first stacking structure to remove the edge clearance area of the first stacking structure, and flattening the first metal layer to form a first bonding pad;
Step S3: bonding the second wafer with the front edge area subjected to trimming treatment with the first stacking structure, grinding and thinning the second wafer from the back surface of the second wafer to reserve the second wafer with partial thickness and form a second stacking structure, wherein the second stacking structure is in a boss shape,
the second stacking structure is electrically connected with the second wafer through the first bonding pad, and an edge clearance area is formed at the edge of the bonding surface of the first stacking structure and the second wafer;
step S4: and trimming the front edge area of the second stacking structure, and removing the edge clearance area of the second stacking structure.
Example 1
The following describes in detail a method for forming a multi-wafer stack structure according to an embodiment of the present invention with reference to fig. 2, 3a to 3d, and 4a to 4 f.
The multi-wafer stacking structure of the present embodiment includes a carrier wafer 110 and 2 wafers sequentially stacked on the carrier wafer 110.
Fig. 3a is a schematic cross-sectional view of a first stacked structure according to the present embodiment. As shown in fig. 3a, step S1 is first performed, a first wafer 120 with a front edge area trimmed is bonded to a carrier wafer 110, and then the first wafer 120 is ground and thinned from a back surface 120b of the first wafer 120, so as to retain a part of the thickness of the first wafer 120, and form a first stacked structure 100, where the first stacked structure is in a boss shape,
The first stacking structure 100 has an edge gap area M1 at the edge of the bonding surface of the carrier wafer 110 and the first wafer 120.
The method specifically comprises the following steps:
first, the first wafer 120 is provided, and the edge area of the front surface 120a of the first wafer 120 is trimmed, so as to avoid the phenomenon of bonding damage at the edge of the bonding surface due to the trimming of the edges of the first wafer 120 and the carrier wafer 110 in the subsequent bonding process of the first wafer 120 and the carrier wafer 110. The first wafer 120 further includes a back surface 120b disposed opposite to the front surface 120a, where the front surface 120a is a bonding surface during bonding, and forms a bonding pad (not shown) before the bonding process, and is electrically connected to the carrier wafer through the bonding pad after bonding. The trimmed first wafer 120 is in a boss shape, so that the trimmed first wafer 120 includes a first base portion (not shown) and a first protrusion 121 on the first base portion. The edge trimming width of the first wafer 120 is a first width W1; in the thickness direction of the first wafer 120, the edge area of a part of the thickness of the first wafer 120 is trimmed, and after the trimming process is performed on the first wafer 120 by using a trimming machine, the edge area of the first wafer 120 forms a chamfer, for example, a right-angle step.
Next, a carrier wafer 110 is provided, and the carrier wafer 110 is used as the bottom layer of the subsequently formed multi-wafer stack structure. Bonding the first protruding portion 121 of the first wafer 120 toward the front surface 110a of the carrier wafer, where the projection of the first protruding portion 121 is located on the front surface 110a of the carrier wafer. The first wafer 120 and the carrier wafer 110 may be bonded using a single material, or a hybrid metal-to-metal, dielectric layer-to-dielectric layer bond.
Next, the first wafer 120 is thinned by polishing from the back surface 120b of the first wafer. Specifically, the polishing and thinning process may remove the first base portion and a portion of the thickness of the first protruding portion 121 (i.e., a portion of the thickness of the first wafer is retained), so that the first stacked structure 100 is still in a boss shape. Specifically, the thinning may be performed by first performing rough grinding, which is performed rapidly by a rough grinding machine, and then performing fine grinding, which is performed by a Chemical Mechanical Polishing (CMP) process, for example. Since the first wafer 120 is subjected to trimming treatment before bonding, the edge portion thereof is not sufficiently flat, so that the first stacked structure has an edge gap area M1 at the edge of the bonding surface of the carrier wafer and the first wafer 1. Next, a dielectric layer 124 and a metal interconnect structure 122 embedded in the dielectric layer 124 are formed on the back surface 120b of the first wafer. The material of the dielectric layer 124 may be any one or a combination of two or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.
Fig. 3b is a schematic cross-sectional view of the first stacked structure after trimming in the present embodiment. As shown in fig. 3b, step S2 is performed, in which a first bonding hole is formed in the front surface 100a of the first stacked structure, and a first metal layer is filled in the first bonding hole, wherein the first metal layer also covers the front surface 100a of the first stacked structure, and then edge regions of the front surface 100a of the first stacked structure are trimmed to remove the edge gap region M1 of the first stacked structure, and then the first metal layer is planarized to form a first bonding pad. The front surface 100a of the first stacked structure includes a thinned back surface of the first wafer and an exposed front surface of the carrier wafer of the first wafer.
For clarity, this step is described in detail below in connection with fig. 4a-4f, wherein fig. 4a-4f are schematic cross-sectional views of the partial area a of fig. 3a after enlargement of the sub-steps in this step.
The method specifically comprises the following steps:
fig. 4a is a schematic structural diagram of the photoresist layer after formation in this embodiment. As shown in fig. 4a, first, a photoresist layer 200 is formed on the dielectric layer 124 on the front surface 100a of the first stacked structure, where the photoresist layer 200 covers the thinned back surface 120b of the first wafer, and also covers the front surface 110a of the carrier wafer exposed by the first wafer 120, the sidewalls of the dielectric layer 124, and the sidewalls of the thinned first wafer. The photoresist layer 200 has a hump near a first width W1 from the edge of the handle wafer 110. In this way, compared to the hump in the prior art, which occurs near the second width W2 (W2 > W1) of the edge of the carrier wafer, the hump in this embodiment is shifted outwards (i.e. closer to the edge of the carrier wafer), which is beneficial to reducing the edge-washing width of the subsequent photoresist layer.
Fig. 4b is a schematic cross-sectional structure of the photoresist after edge washing in this embodiment. As shown in fig. 4b, next, in order to remove the hump, the photoresist layer 200 is subjected to an edge-washing process to remove the photoresist layer 200 at the edge of the front surface 100a of the first stacked structure, and the photoresist layer 200 is patterned. Due to the outward movement of the hump, the width of the photoresist layer 200 at the edge of the first stacked structure 100 is smaller during the edge washing process of the photoresist layer 200, the width of the photoresist layer 200 at the edge washing is greater than the first width W1, and further, the width of the photoresist layer 200 at the edge washing is between W1 and W2. Preferably, the width of the photoresist layer 200 at the edge of the wafer is the sum of the first width W1 and the process deviation, after the photoresist layer 200 is at the edge of the wafer, the photoresist layer 200 exposes the dielectric layer 124 exposed by the first wafer 120 and bearing the front surface 110a of the wafer, the sidewall of the thinned first wafer 120, the sidewall of the dielectric layer 124, and the edge region of the thinned back surface 120b of the first wafer having the width of the process deviation length. At this time, the width of the photoresist layer 200 is smaller than the width of the photoresist layer (greater than the second width W2) in the prior art, which increases the effective area of the first stacking structure on the premise of solving the hump, thereby increasing the effective area of the multi-wafer stacking structure.
Fig. 4c is a schematic structural diagram of the bonding hole formed in this embodiment. As shown in fig. 4c, the patterned photoresist layer 200 is used as a mask to etch the front surface 100a of the first stacked structure, specifically, the dielectric layer 124 on the back surface 120b of the first wafer is etched, so as to form the first bonding hole 101, where the first bonding hole 101 exposes the surface of the metal interconnection structure 122, and the remaining photoresist layer 200 is removed. Since the photoresist layer 200 exposes the dielectric layer 124 at the edge region of the back surface 120b of the first wafer, the portion is also etched during the etching process, so as to form an arc-shaped first recess region 123 in the region; the dielectric layer 124 of the photoresist layer 200, which exposes the front surface 110a of the carrier wafer of the first wafer, is also etched in the etching process, so as to form an arc-shaped second recess region 111. The two recessed areas facilitate formation of a copper ring upon subsequent formation of the first metal layer.
Fig. 4d is a schematic cross-sectional structure of the first metal layer filled in the present embodiment. As shown in fig. 4d, a first metal layer 102 is then formed in the first bonding hole 101. Specifically, first, a first barrier layer and a first seed layer are sequentially formed on the inner wall of the first bonding hole 101, where the first barrier layer and the first seed layer cover the thinned dielectric layer 124 on the back surface 120b of the first wafer. The material of the barrier layer can be tantalum, tantalum nitride or tungsten nitride, and the material of the seed layer can be copper. Next, a filling metal filling layer is formed in the first bonding hole 101 through an electrochemical plating ECP process, and the filled metal filling layer also covers the first barrier layer and the first seed layer over the first bonding hole 101, the first recess region 111 and the second recess region 123. The material of the metal filling layer includes but is not limited to copper. Next, the first metal layer 102 is subjected to a side-washing process, where the side-washing width of the first metal layer 102 is, for example, greater than the side-washing width of the photoresist layer 200, and preferably, the side-washing width of the first metal layer 102 is the sum of the side-washing width of the photoresist layer 200 and the process deviation, that is, the first metal layer 102 exposes the second recess region 111 and the first recess region 123 with a partial width. The width of the first metal layer 102 is smaller than that of the first metal layer in the prior art, so that a process window of the first metal layer edge washing process is increased, the process difficulty is reduced, and the formation of copper rings is avoided. The trimmed first stacked structure 100 is in a boss shape, and the first recess area 123 and the second recess area 123 are removed, so that the edge area of the first stacked structure 100 forms a chamfer, for example, a right-angle step.
Fig. 4e is a schematic structural diagram of the trimming process provided in the present embodiment. As shown in fig. 4e, referring to fig. 4d, the edge area of the front surface 100a of the first stack structure is trimmed to remove the area where the defect occurs in the edge gap area M1 of the first stack structure 100, and the defective area where the defect may occur in the first recess area 123, and the first recess area 123 and the edge gap area M1 of the first stack structure are located on different planes, and the projection of the first recess area 123 and the edge gap area M1 of the first stack structure have overlapping areas, so that the width of the trimming is greater than or equal to the width of the edge gap area M1 of the first stack structure or the width of the first recess area 123. In this embodiment, the width of the edge gap area M1 of the first stacking structure is greater than the width of the first recess 123, so that the trimming width of the first stacking structure is greater than the sum of the edge trimming width of the first wafer and the width of the edge gap area M1 of the first stacking structure, thereby increasing the effective area of the wafer and reducing the difficulty of integrating the edges of the wafer with the increasing number of stacks of hybrid bonding. Meanwhile, the first concave region is removed, so that no copper ring is formed in the subsequent planarization treatment.
Then, the particle residues generated during the trimming are removed by a cleaning process.
Next, fig. 4f is a schematic structural diagram of the first bonding pad formed in this embodiment. As shown in fig. 4f, the first bonding pad 103 is formed by planarizing the first metal layer 102 by a polishing process, for example, a CMP (chemical mechanical planarization) process.
Fig. 3c is a schematic cross-sectional view of the second stacked structure according to the present embodiment. As shown in fig. 3c, step S3 is performed, bonding the trimmed second wafer 310 with the first stacked structure 100 at the front edge region, grinding and thinning the second wafer 310 from the back surface 310b of the second wafer to reserve a part of the thickness of the second wafer 310, and forming a second stacked structure 300, wherein the second stacked structure 300 is in a boss shape,
the second stacked structure 300 is electrically connected to the second wafer 310 through the first bonding pad, and an edge gap area M2 exists at an edge of the bonding surface of the first stacked structure 100 and the second wafer 310 in the second stacked structure 300.
The method specifically comprises the following steps:
first, a second wafer 310 is provided, and an edge area of a front surface 310a of the second wafer is trimmed, the trimming width of the second wafer 310 is a third width, and the trimming width of the second wafer 310 is greater than the trimming width of the first stacked structure 100. The second wafer 310 is in a boss shape, and the trimmed second wafer 310 includes a second base portion (not shown) and a second protruding portion 311 located on the second base portion.
Next, the second protruding portion 311 is bonded toward the front surface 100a of the first stacked structure, and the second protruding portion 311 projects the full land on the front surface 100a of the first stacked structure, specifically, the second protruding portion 311 projects the full land on the first protruding portion 121. Likewise, the second wafer 310 and the first stacked structure 100 may be bonded using a single material, or a hybrid metal-to-metal, dielectric-to-dielectric bonding. The second stacked structure 300 is electrically connected to the second wafer 310 through the first bonding pad 103, and the second stacked structure 300 has an edge gap region M2 at an edge of a bonding surface of the first stacked structure 100 and the second wafer 310.
Next, the second wafer 310 is thinned by grinding from the back surface 310b of the second wafer to leave a portion of the thickness of the second wafer 310 and form a second stacked structure 300. Specifically, the second wafer 310 is thinned by grinding from the back surface 310b of the second wafer to remove the second base portion, and the second bump 311 is partially thick.
Fig. 3d is a schematic cross-sectional view of the stacked structure of the present embodiment after forming a multi-wafer structure. As shown in fig. 3d, step S41 is performed to trim the front edge region of the second stack structure, and remove the edge gap region of the second stack structure. The trimming width of the second stacking structure is a fourth width, and the fourth width is larger than the third width, so as to complete the preparation of the multi-wafer stacking structure.
Example two
Compared with the first embodiment, the multi-wafer stacking structure of the present embodiment includes a carrier wafer 110 and N wafers stacked on the carrier wafer 110 in sequence, where N is greater than or equal to 3, and N is a positive integer. And after the second stacked structure of the step S3 is formed, step S42 is performed, forming an (i-1) th bonding hole in the front surface of the (i-1) th stacked structure, filling an (i-1) th metal layer in the (i-1) th bonding hole, wherein the (i-1) th metal layer also covers the front surface of the (i-1) th stacked structure, trimming the front surface edge region of the (i-1) th stacked structure to remove the edge gap region of the (i-1) th stacked structure, and flattening the (i-1) th metal layer to form an (i-1) th bonding pad.
Step S5 is executed, the ith wafer with the front edge area subjected to trimming treatment is bonded with the (i-1) stacking structure, the ith wafer is thinned from the back surface of the ith wafer in a grinding way, so that the ith wafer with partial thickness is reserved, an ith stacking structure is formed, the ith stacking structure is in a boss shape,
the ith stacking structure is electrically connected with the ith wafer through the (i-1) bonding pad, an edge clearance area exists at the edge of the bonding surface of the (i-1) stacking structure and the ith wafer, i is more than 2 and less than N-1, and i is a positive integer.
Step S6 is then executed, an (N-2) th bonding hole is formed in the front surface of the (N-2) th stacked structure, an (N-2) th metal layer is filled in the (N-2) th bonding hole, the (N-2) th metal layer also covers the front surface of the (N-2) th stacked structure, the front surface edge area of the (N-2) th stacked structure is trimmed to remove the edge clearance area of the (N-2) th stacked structure, and the (N-2) th metal layer is subjected to planarization treatment to form an (N-2) th bonding pad;
step S7 is executed, the (N-1) th wafer with the front edge area subjected to trimming treatment is bonded with the (N-2) th stacking structure, the (N-1) th wafer is thinned from the back surface of the (N-1) th wafer by grinding, so that the (N-1) th wafer with partial thickness is reserved, the (N-1) th stacking structure is formed, the (N-1) th stacking structure is in a boss shape,
wherein the (N-1) th stacking structure is electrically connected with the (N-1) th wafer through the (N-2) th bonding pad, and an edge clearance area exists at the edges of bonding surfaces of the (N-2) th stacking structure and the (N-1) th wafer;
in step S42 to step S7, the photoresist layer is removed when the bonding hole is formed each time, that is, the edge washing width of the photoresist layer is reduced, and during each time of trimming, the edge of the stacking structure may have a bad area and the projection of the edge clearance area when the stacking structure is formed has an overlapping area, so that the trimming width is reduced, the effective area of the stacking structure is increased, the formation of copper rings is avoided, and the difficulty of integrating the edges of the wafer along with the continuous increase of the stacking number of hybrid bonding is reduced.
And step S8, bonding an N-th wafer with the front edge area subjected to trimming treatment with the (N-1) -th stacking structure, grinding and thinning the N-th wafer from the back surface of the N-th wafer so as to keep the N-th wafer with partial thickness and form an N-th stacking structure, wherein the N-th stacking structure is in a boss shape, trimming the front edge area of the N-th stacking structure, and removing the edge clearance area of the N-th stacking structure.
In summary, according to the method for forming the multi-wafer stacking structure provided by the invention, the trimming process after the previous bonding is pushed to the step of filling the metal layer in the bonding hole before the next bonding, so that the edge clearance area caused by the previous bonding and the possible bad area formed between the filling metal layers in the bonding hole after the previous bonding and before the next bonding are not on the same plane, and the projection parts of the edge clearance area and the possible bad area overlap, the trimming width of the pushed trimming process can be reduced, thereby the effective area of the multi-wafer stacking structure is increased, the possible bad area is removed, and the bad generation (the formation of copper ring in the bonding pad forming process) is avoided.
Furthermore, unless specifically stated or indicated otherwise, the description of the terms "first," "second," and the like in the specification merely serve to distinguish between various components, elements, steps, etc. in the specification, and do not necessarily represent a logical or sequential relationship between various components, elements, steps, etc.
It will be appreciated that although the invention has been described above in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Claims (10)
1. The method for forming the multi-wafer stacking structure is characterized by comprising the following steps of:
step S1: bonding a first wafer with a front edge area subjected to trimming treatment with a bearing wafer, grinding and thinning the first wafer from the back surface of the first wafer to reserve the first wafer with partial thickness and form a first stacking structure, wherein the first stacking structure is in a boss shape,
Wherein, the first stacking structure has an edge clearance area at the edge of the bonding surface of the bearing wafer and the first wafer;
step S2: forming a first bonding hole on the front surface of the first stacking structure, filling a first metal layer in the first bonding hole, covering the front surface of the first stacking structure with the first metal layer, trimming the edge area of the front surface of the first stacking structure to remove the edge clearance area of the first stacking structure, flattening the first metal layer to form a first bonding pad,
the process of forming and filling the bonding holes of the first stacked structure and the process of filling the first metal layer generate a possibly-occurring bad area in the front edge area of the first stacked structure, and the possibly-occurring bad area is overlapped with the projection part of the edge clearance area;
step S3: bonding the second wafer with the front edge area subjected to trimming treatment with the first stacking structure, grinding and thinning the second wafer from the back surface of the second wafer to reserve the second wafer with partial thickness and form a second stacking structure, wherein the second stacking structure is in a boss shape,
The second stacking structure is electrically connected with the second wafer through the first bonding pad, and an edge clearance area exists at the edge of the bonding surface of the first stacking structure and the second wafer;
step S41: and trimming the front edge area of the second stacking structure, and removing the edge clearance area of the second stacking structure.
2. The method of forming of claim 1, wherein step S1 comprises:
providing a first wafer, trimming a front edge area of the first wafer, wherein the trimmed first wafer comprises a first base part and a first protruding part positioned on the first base part, and the edge trimming width of the first wafer is a first width;
providing a bearing wafer, bonding the first protruding part towards the front surface of the bearing wafer, wherein the projection of the first protruding part is completely located on the front surface of the bearing wafer;
thinning the first wafer from the back side of the first wafer, removing the first base portion, and retaining a first protruding portion of a partial thickness;
and forming a dielectric layer and a metal interconnection structure embedded in the dielectric layer on the back surface of the first wafer.
3. The method of forming of claim 1, wherein step S2 includes:
forming a photoresist layer on the front surface of the first stacking structure;
performing edge washing treatment on the photoresist layer to remove the photoresist layer at the edge of the first stacking structure, and performing patterning treatment on the photoresist layer, wherein the edge washing width of the photoresist layer is larger than the first width;
etching the first stacking structure by taking the patterned photoresist layer as a mask to form a first bonding hole, and forming a concave region at the edge of the first stacking structure;
forming a first metal layer in the first bonding hole, wherein the first metal layer also covers the concave region;
performing edge washing treatment on the first metal layer;
trimming the front edge region of the first stacked structure to remove the edge gap region and the recessed region of the first stacked structure;
cleaning the first stacked structure through a cleaning process;
and flattening the first metal layer to form a first bonding pad.
4. The method of claim 3, wherein the recessed region comprises a first recessed region and a second recessed region, the first recessed region being located at an edge region of the back side of the first wafer, the second recessed region being located at the exposed front side of the carrier wafer of the first wafer.
5. The method of claim 4, wherein a width of the first recessed region is less than a width of an edge gap region of the first stack, and wherein a trimming width of the first stack is greater than a sum of an edge trimming width of the first wafer and a width of the edge gap region of the first stack.
6. The method of claim 3, wherein the photoresist layer has a bead width that is the sum of the first width and the process bias.
7. The method of forming of claim 3, wherein a bead width of the first metal layer is greater than a bead width of the photoresist layer.
8. The method of claim 7, wherein the first metal layer has a bead width that is a sum of a bead width of the photoresist layer and a process bias.
9. The method of forming of claim 1, wherein step S3 includes:
providing a second wafer, trimming the front edge area of the second wafer, wherein the trimming width of the second wafer is larger than that of the first stacking structure, and the trimmed second wafer comprises a second base part and a second protruding part positioned on the second base part;
Bonding the second protruding part towards the front surface of the first stacking structure, and projecting the whole part of the second protruding part to the front surface of the first stacking structure;
thinning the second wafer from the backside grinding of the second wafer, removing the second base portion, and retaining a portion of the thickness of the second bump.
10. A method for forming a polycrystalline wafer stacking structure is characterized by comprising a bearing wafer and N wafers sequentially stacked on the bearing wafer, wherein N is more than or equal to 3, and N is a positive integer;
the forming method comprises the following steps:
step S1: bonding a first wafer with a front edge area subjected to trimming treatment with a bearing wafer, grinding and thinning the first wafer from the back surface of the first wafer to reserve the first wafer with partial thickness and form a first stacking structure, wherein the first stacking structure is in a boss shape,
wherein, the first stacking structure has an edge clearance area at the edge of the bonding surface of the bearing wafer and the first wafer;
step S2: forming a first bonding hole on the front surface of the first stacking structure, filling a first metal layer in the first bonding hole, covering the front surface of the first stacking structure with the first metal layer, trimming the edge area of the front surface of the first stacking structure to remove the edge clearance area of the first stacking structure, flattening the first metal layer to form a first bonding pad,
The process of forming and filling the bonding holes of the first stacked structure and the process of filling the first metal layer generate a possibly-occurring bad area in the front edge area of the first stacked structure, wherein the possibly-occurring bad area in the front edge area of the first stacked structure is overlapped with the projection part of the edge clearance area;
step S3: bonding the second wafer with the front edge area subjected to trimming treatment with the first stacking structure, grinding and thinning the second wafer from the back surface of the second wafer to reserve the second wafer with partial thickness and form a second stacking structure, wherein the second stacking structure is in a boss shape,
the second stacking structure is electrically connected with the second wafer through the first bonding pad, and an edge clearance area exists at the edge of the bonding surface of the first stacking structure and the second wafer;
step S42: forming an (i-1) th bonding hole on the front surface of the (i-1) th stacked structure, filling an (i-1) th metal layer in the (i-1) th bonding hole, covering the front surface of the (i-1) th stacked structure with the (i-1) th metal layer, trimming the front surface edge region of the (i-1) th stacked structure to remove the edge gap region of the (i-1) th stacked structure, flattening the (i-1) th metal layer to form an (i-1) th bonding pad,
Wherein the process of forming the bonding hole of the (i-1) th stacked structure and filling the (i-1) th metal layer generates a possibly defective area in the front edge area of the (i-1) th stacked structure, and the possibly defective area in the front edge area of the (i-1) th stacked structure overlaps with the projection part of the edge gap area;
step S5: bonding an ith wafer with a front edge area subjected to trimming treatment with the (i-1) stacking structure, grinding and thinning the ith wafer from the back surface of the ith wafer so as to keep part of the thickness of the ith wafer and form an ith stacking structure, wherein the ith stacking structure is in a boss shape,
the ith stacking structure is electrically connected with the ith wafer through the (i-1) bonding pad, an edge clearance area exists at the edges of bonding surfaces of the (i-1) stacking structure and the ith wafer, i is more than 2 and less than N-1, and i is a positive integer;
step S6: forming an (N-2) -th bonding hole on the front surface of the (N-2) -th stacked structure, filling an (N-2) -th metal layer in the (N-2) -th bonding hole, covering the front surface of the (N-2) -th stacked structure with the (N-2) -th metal layer, trimming the front surface edge region of the (N-2) -th stacked structure to remove the edge gap region of the (N-2) -th stacked structure, flattening the (N-2) -th metal layer to form an (N-2) -th bonding pad,
Wherein the process of forming the bonding hole of the (N-2) -th stacked structure and filling the (N-2) -th metal layer generates a possibly defective area in a front edge area of the (N-2) -th stacked structure, and the possibly defective area in the front edge area of the (N-2) -th stacked structure overlaps with a projection part of the edge gap area;
step S7: bonding the (N-1) th wafer with the front edge area subjected to trimming treatment with the (N-2) th stacking structure, grinding and thinning the (N-1) th wafer from the back surface of the (N-1) th wafer to reserve part of the thickness of the (N-1) th wafer and form the (N-1) th stacking structure, wherein the (N-1) th stacking structure is in a boss shape,
wherein the (N-1) th stacking structure is electrically connected with the (N-1) th wafer through the (N-2) th bonding pad, and an edge clearance area exists at the edges of bonding surfaces of the (N-2) th stacking structure and the (N-1) th wafer;
step S8: bonding an N-th wafer with a front edge area subjected to trimming treatment with an (N-1) -th stacking structure, grinding and thinning the N-th wafer from the back surface of the N-th wafer so as to keep the N-th wafer with partial thickness and form an N-th stacking structure, wherein the N-th stacking structure is in a boss shape, trimming the front edge area of the N-th stacking structure, and removing an edge clearance area of the N-th stacking structure.
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| CN110854039A (en) * | 2019-09-30 | 2020-02-28 | 芯盟科技有限公司 | Stack bonding wafer processing apparatus |
| CN111430276A (en) * | 2020-04-24 | 2020-07-17 | 武汉新芯集成电路制造有限公司 | Multi-wafer stacking trimming method |
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| US8119500B2 (en) * | 2007-04-25 | 2012-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer bonding |
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| CN110854039A (en) * | 2019-09-30 | 2020-02-28 | 芯盟科技有限公司 | Stack bonding wafer processing apparatus |
| CN111430276A (en) * | 2020-04-24 | 2020-07-17 | 武汉新芯集成电路制造有限公司 | Multi-wafer stacking trimming method |
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