CN112181037A - Multi-path power supply current equalizing circuit and control method - Google Patents
Multi-path power supply current equalizing circuit and control method Download PDFInfo
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
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- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Abstract
The invention relates to the technical field of server power supplies, in particular to a multi-path power supply current equalizing circuit and a control method. In the circuit: the source electrode of the NMOS transistor is connected with the merging output end; the drain electrode of the NMOS transistor is connected with the output end of the power supply corresponding to the current equalizing module in the at least two power supplies; the input end of the gate leakage circuit and the driving end of the gate driving circuit are both connected with the gate of the NMOS transistor; the gate control processor is connected with the control end of the gate driving circuit; the gate control processor is also connected with the merging output end and the output end of the power supply corresponding to the current equalizing module in a sampling mode respectively. The current-sharing module can adjust the switch state and the on-resistance of the NMOS transistor according to the power supply voltage and the voltage of the combined output end, avoids potential safety hazards caused by power supply short circuit, overhigh voltage of the combined output end and fluctuation of output current, and accordingly realizes safe current-sharing control of power supply of multiple paths of power supplies.
Description
Technical Field
The invention relates to the technical field of server power supplies, in particular to a multi-path power supply current equalizing circuit and a control method.
Background
Along with the development of novel internet technologies such as cloud computing, AI intelligence, big data, the performance of the server is also stronger and stronger, and each high-precision chip is also higher and higher to the size of electric current and the stability of power. The demand for current is increasing to achieve higher power and higher performance.
When the current demand is large, the performance and the cost of a single power supply source can be increased, a plurality of power supplies can be combined for power supply, the pressure of the single power supply source is relieved, the redundant quantity is increased when the power supply fails, and the power supply reliability is enhanced. Power supply stability is generally manifested as voltage and current stabilization, line path temperature stabilization. The line temperature is closely related to the current on the path, and when the current on the line path is too large, more heat is generated on the path, and when the heat is too high, the damage such as board burning or fire hazard is easily generated.
Therefore, how to implement the safe current sharing control of the power supply of the multiple power supplies is a technical problem which needs to be solved urgently at present.
Disclosure of Invention
The invention aims to provide a multi-path power supply current-sharing circuit and a control method, which are used for carrying out safe current-sharing control on power supply of a plurality of paths of power supplies.
In order to achieve the above object, the embodiments of the present invention provide the following solutions:
in a first aspect, an embodiment of the present invention provides a multi-channel power supply current equalizing circuit, including: combining the output and at least two power supplies; any one of the at least two power supplies is correspondingly provided with a current equalizing module;
the current equalizing module comprises an NMOS transistor, a gate pole bleeder circuit, a gate pole driving circuit and a gate pole control processor;
the source electrode of the NMOS transistor is connected with the merging output end; the drain electrode of the NMOS transistor is connected with the output end of the power supply corresponding to the current equalizing module in the at least two power supplies;
the input end of the gate leakage circuit and the driving end of the gate driving circuit are both connected with the gate of the NMOS transistor;
the gate control processor is connected with the control end of the gate driving circuit; and the gate control processor is also respectively connected with the merging output end and the output end of the power supply corresponding to the current equalizing module in a sampling manner.
In one possible embodiment, the gate bleed circuit includes: the circuit comprises a first diode, a first resistor, a first capacitor and a first triode;
the anode of the first diode is connected with the gate electrode of the NMOS transistor; the cathode of the first diode is grounded through the first capacitor;
one end of the first resistor is connected with the gate electrode of the NMOS transistor, and the other opposite end of the first resistor is connected with the base electrode of the first triode;
an emitter of the first triode is connected with a cathode of the first diode; and the collector electrode of the first triode is grounded.
In one possible embodiment, the gate bleed circuit includes: the voltage comparator, a second resistor, a second capacitor and a second triode;
the positive input end of the voltage comparator is connected with a reference voltage end; the reverse input end of the voltage comparator is connected with the gate electrode of the NMOS transistor; the output end of the voltage comparator is connected with the base electrode of the second triode;
the emitter of the second triode is connected with the gate of the NMOS transistor; and the collector of the second triode is grounded through a parallel circuit formed by the second capacitor and the second resistor.
In a possible embodiment, the current equalizing module further includes: a third resistor, a fourth resistor, a fifth resistor and a sixth resistor;
the third resistor and the fourth resistor are connected in series between the output end of the power supply corresponding to the current equalizing module and the ground;
the first sampling input end of the gate control processor is connected between the third resistor and the fourth resistor so as to realize that the gate control processor is connected with the output end of the power supply corresponding to the current equalizing module in a sampling manner;
the fifth resistor and the sixth resistor are connected in series between the combined output end and the ground;
and the second sampling input end of the gate control processor is connected between the fifth resistor and the sixth resistor so as to realize that the gate control processor is connected with the merging output end in a sampling manner.
In one possible embodiment, the gate driving circuit is a charge pump module.
In one possible embodiment, the voltage comparator is an LM393 dual voltage comparator.
In a second aspect, an embodiment of the present invention provides a multi-power-supply current-sharing control method, which is applied to the multi-power-supply current-sharing circuit according to any one of the first aspects, and includes:
acquiring a merging end sampling voltage of a merging output end and a power supply end sampling voltage of an output end of a power supply corresponding to the current equalizing module;
acquiring equivalent load current output by the current equalizing module according to the power supply end sampling voltage and the merging end sampling voltage;
adjusting the on-resistance of the NMOS transistor according to the magnitude relation between the equivalent load current and the set current average value;
judging whether the difference value of the power supply end sampling voltage and the merging end sampling voltage is larger than a set upper limit threshold or smaller than 0;
and if so, turning off the NMOS transistor.
In a possible embodiment, the obtaining an equivalent load current output by the current equalizing module according to the power source terminal sampling voltage and the merging terminal sampling voltage includes:
setting an equivalent internal resistance r according to the third resistor, the fourth resistor, the fifth resistor and the sixth resistor;
calculating the equivalent load current I output by the current equalizing module, wherein the specific calculation formula is as follows:
wherein, U1Sampling voltage, U, for said power supply terminal2And sampling the voltage for the merging end.
In a possible embodiment, the adjusting the on-resistance of the NMOS transistor according to the magnitude relationship between the equivalent load current and the set current average value includes:
if the equivalent load current is larger than the set current average value, increasing the on-resistance of the NMOS transistor;
and if the equivalent load current is smaller than the set current average value, reducing the on-resistance of the NMOS transistor.
In a possible embodiment, after the turning off the NMOS transistor, the method further includes:
and discharging the electric energy at the driving end of the gate driving circuit by using the gate discharging circuit.
Compared with the prior art, the invention has the following advantages and beneficial effects:
according to the invention, the current-sharing modules are arranged for the multi-path power supply, each current-sharing module can adjust the switch state and the on-resistance of the NMOS transistor according to the power supply voltage and the voltage of the combined output end so as to realize the current-sharing control of the current output by the power supply to the combined output end, avoid potential safety hazards caused by power supply short circuit, overhigh voltage of the combined output end and fluctuation of the output current, and further realize the safe current-sharing control of the power supply of the multi-path power supply.
Drawings
In order to more clearly illustrate the embodiments of the present specification or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present specification, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic connection diagram of a multi-path power supply current equalizing circuit according to an embodiment of the present invention;
fig. 2 is a schematic connection diagram of a gate bleed circuit according to an embodiment of the present invention;
fig. 3 is a schematic connection diagram of a gate bleed circuit according to an embodiment of the present invention;
FIG. 4 is a schematic connection diagram of a multi-power supply current equalizing circuit with a sampling circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a gate driving circuit according to an embodiment of the present invention;
fig. 6 is a flowchart of a method for controlling current sharing in power supply of multiple power supplies according to an embodiment of the present invention.
Description of reference numerals: the power supply is 1, the module is 11, the NMOS transistor is 12, the gate leakage circuit is 13, the gate drive circuit is 14, the gate control processor is 15, and the power supply merging end is 2.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by those skilled in the art based on the embodiments of the present invention belong to the scope of protection of the embodiments of the present invention.
Referring to fig. 1, fig. 1 is a schematic connection diagram of a multi-channel power supply current sharing circuit, which specifically includes: combining the output 2 and at least two power supplies 1; wherein, any one of the at least two power supplies 1 is correspondingly provided with a current equalizing module 11; the current equalizing module 11 comprises an NMOS transistor 12, a gate bleeder circuit 13, a gate drive circuit 14 and a gate control processor 15; the source electrode of the NMOS transistor 12 is connected with the merging output end 2; the drain electrode of the NMOS transistor 12 is connected with the output end of the power supply 1 corresponding to the current equalizing module 11 in the at least two power supplies; the input end of the gate leakage circuit 13 and the driving end of the gate driving circuit 14 are both connected with the gate of the NMOS transistor 12; the gate control processor 15 is connected with the control end of the gate driving circuit 14; the gate control processor 15 is also connected with the merging output end 2 and the output end of the power supply 1 corresponding to the current equalizing module 11 in a sampling mode respectively.
In this embodiment, the NMOS transistor 12 is used as a conduction channel between the power supply 1 and the merged output terminal 2, so that the conduction loss can be reduced, and the opening degree of the channel can be conveniently controlled.
In this embodiment, can set up a plurality of modules of flow equalizing simultaneously, realize the current-sharing control of multichannel power supply.
In this embodiment, the gate bleeder circuit 13 can rapidly bleed off the voltage at the driving terminal of the gate driving circuit 14, so as to rapidly turn off the NMOS transistor, thereby protecting the preceding stage circuit by rapid bleed-off when the conditions such as short circuit and the like require rapid turn-off of the driving.
Fig. 2 is a schematic connection diagram of a gate bleeder circuit provided in this embodiment, including: a first diode D1, a first resistor R1, a first capacitor C1 and a first triode Q1; the anode of the first diode D1 is connected to the gate of the NMOS transistor 12; the cathode of the first diode D1 is grounded through a first capacitor C1; one end of the first resistor R1 is connected with the gate of the NMOS transistor 12, and the other opposite end is connected with the base of the first triode Q1; an emitter of the first triode Q1 is connected with a cathode of a first diode D1; the collector of the first transistor Q1 is connected to ground.
When the value of the first capacitor C1 is small, and the gate leakage circuit 13 rapidly acts due to the drop of the driving voltage when the gate driving circuit 14 cuts off the driving voltage of the MOS, the electric charge of the driving electrode is leaked, and the function of rapidly turning off and turning on the MOS is realized; when the value of the first capacitor C1 is large, the circuit can also realize a slow-start function, and when the gate driving circuit 14 outputs the MOS driving voltage, the voltage of the driving electrode is slowly increased, so that the impact of the driving voltage on the gate electrode is reduced.
Fig. 3 is a schematic connection diagram of a gate bleeder circuit provided in this embodiment, including: the voltage comparator A1, a second resistor R2, a second capacitor C2 and a second triode Q2; the positive input end of the voltage comparator A1 is connected with a reference voltage end; the inverting input end of the voltage comparator A1 is connected with the gate electrode of the NMOS transistor; the output end of the voltage comparator A1 is connected with the base of the second triode Q2; the emitter of the second triode Q2 is connected with the gate of the NMOS transistor; the collector of the second transistor Q2 is grounded through a parallel circuit formed by a second capacitor C2 and a second resistor R2.
When the gate driving circuit 14 cuts off the driving voltage of the MOS, the voltage at the driving terminal of the gate bleeder circuit 13 drops rapidly, and when the voltage is less than the voltage at the reference voltage terminal, the voltage comparator a1 outputs a high level, so that the second transistor Q2 is turned on, and the voltage of the driving voltage is rapidly discharged by using a parallel circuit formed by the second capacitor C2 and the second resistor R2. Preferably, the voltage comparator is an LM393 dual voltage comparator.
The gate control processor 15 can collect the voltage at the power supply 1 and combine the voltage at the output terminal 2, as shown in fig. 4, which is a schematic connection diagram of a multi-channel power supply current-sharing circuit with a sampling circuit provided in this embodiment, and includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6; the third resistor R3 and the fourth resistor R4 are connected in series between the output end of the power supply 1 corresponding to the current equalizing module 11 and the ground; the first sampling input end of the gate control processor 15 is connected between the third resistor R3 and the fourth resistor R4, so that the gate control processor 15 is connected with the output end of the power supply 1 corresponding to the current sharing module 11 in a sampling manner; the fifth resistor R5 and the sixth resistor R6 are connected in series between the combined output end 2 and the ground; the second sampling input terminal of the gate control processor 15 is connected between the fifth resistor R5 and the sixth resistor R6 to realize the sampling connection of the gate control processor 15 to the merge output terminal 2.
The third resistor R3 and the fourth resistor R4 form a voltage divider circuit, and the gate control processor 15 can acquire the voltage at the output terminal of the power supply 1 corresponding to the current equalizing module 11 by acquiring the voltage between the third resistor R3 and the fourth resistor R4.
The fifth resistor R5 and the sixth resistor R6 form a voltage divider circuit, and the gate control processor 15 can acquire the voltage of the combined output terminal 2 corresponding to the current equalizing module 11 by acquiring the voltage between the fifth resistor R5 and the sixth resistor R6.
The gate control processor 15 configures an equivalent internal resistance according to the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6, then calculates a current load current output by the current sharing module 11 according to the sampling voltage, and performs on-resistance control and on-off control on the NMOS transistor 12 according to the magnitude of the load current.
Specifically, the gate control processor 15 may be implemented by an electronic chip with sampling and control functions, such as an MCU and a single chip microcomputer.
The gate driving circuit 14 is used to drive the NMOS transistor 12 to operate according to the control signal output by the gate control processor 15, and the gate driving circuit may adopt a charge pump module, where the charge pump is a DC/DC converter, and is formed by using the principle of charge transfer by charging and discharging of a capacitor, and can convert an input positive voltage into a corresponding negative voltage, and can also convert an input voltage into an integral multiple of an output voltage. When the gate driving circuit 14 receives a gate control command from the gate control processor 15, the charge pump in the gate driving circuit 14 generates a corresponding driving voltage, and outputs the driving voltage to the gate from the driving end of the charge pump to control the on/off state and the on-resistance of the NMOS transistor.
Of course, other forms of driving circuits can be used to implement the gate driving function, and fig. 5 is a schematic connection diagram of a gate driving circuit according to an embodiment of the present invention, which includes: a second diode D2, a first zener diode D3, a second zener diode D4, a seventh resistor R7, and an eighth resistor R8; the anode of the second diode D2 is connected to the driving end of the gate driving circuit 14; the cathode of the second diode D2 is connected to the source of the NMOS transistor 12 and the control terminal of the gate driver circuit 14, respectively; the seventh resistor R7 is connected in parallel with the second diode D2; the first zener diode D3 and the second zener diode D4 are connected in series in reverse between the driving terminal of the gate driving circuit 14 and the source of the NMOS transistor 12; the eighth resistor R8 is connected in series between the driving terminal of the gate driving circuit 14 and the source of the NMOS transistor 12; the source of the NMOS transistor 12 is grounded.
The seventh resistor R7 is used to limit current and suppress parasitic oscillation, the eighth resistor R8 is used to provide a discharge loop when the NMOS transistor 12 is turned off, the zener diodes D3 and D4 are used to protect the gate and source of the NMOS transistor 12, and the second diode D2 is used to speed up the turn-off of the NMOS transistor 12.
Fig. 6 is a flowchart of a multi-power supply current-sharing control method according to an embodiment of the present invention, where the method is applied to the multi-power supply current-sharing circuit described above, and the method includes:
and 11, acquiring a merging end sampling voltage of a merging output end and a power supply end sampling voltage of an output end of a power supply corresponding to the current equalizing module.
Specifically, the merging end sampling voltage and the power end sampling voltage can be collected through the voltage division circuit, and voltage collection of different power end (such as 5V, 12V, 48V, 54V and the like) can be realized through reasonable collocation of the voltage division resistors.
It is of course also possible to use a voltage sensor to directly measure and acquire the merging terminal sampled voltage and the power source terminal sampled voltage.
And step 12, acquiring the equivalent load current output by the current-sharing module according to the power end sampling voltage and the merging end sampling voltage.
Here, the present invention further provides a better scheme for obtaining an equivalent load current, specifically:
and step 21, setting the equivalent internal resistance r according to the third resistor, the fourth resistor, the fifth resistor and the sixth resistor.
Specifically, the equivalent internal resistance is reasonably set, so that the power supply end sampling voltage and the merging end sampling voltage can be reduced to bus voltage, and the equivalent load current is calculated. Of course, the resistance accuracy of the equivalent internal resistance is different, and the accuracy of the current sharing control is also different.
Step 22, calculating an equivalent load current I output by the current equalizing module, wherein a specific calculation formula is as follows:
wherein, U1Sampling voltage, U, for said power supply terminal2And sampling the voltage for the merging end.
And step 13, adjusting the on-resistance of the NMOS transistor according to the magnitude relation between the equivalent load current and the set current average value.
Here, the present invention also provides a better control scheme, specifically:
and step 31, if the equivalent load current is greater than the set current average value, increasing the on-resistance of the NMOS transistor.
Specifically, when the equivalent load current is large, current sharing control needs to be performed, and the magnitude of the equivalent load current is reduced.
And step 32, if the equivalent load current is smaller than the set current average value, reducing the on-resistance of the NMOS transistor.
Specifically, when the equivalent load current is small, current sharing control needs to be performed, and the magnitude of the equivalent load current is increased.
And step 14, judging whether the difference value of the power supply end sampling voltage and the merging end sampling voltage is larger than a set upper limit threshold or smaller than 0.
Specifically, when a short-circuit fault occurs, the difference between the power supply end sampling voltage and the merging end sampling voltage is rapidly increased and exceeds a set upper limit threshold, and at the moment, the NMOS transistor is turned off in time by cutting off the output driving voltage of the gate driving circuit, so that the front-end circuit is protected.
Specifically, when the circuit is abnormal, the merging terminal sampling voltage is greater than the power terminal sampling voltage, so that the difference between the power terminal sampling voltage and the merging terminal sampling voltage is less than 0, at this time, the output driving voltage of the gate driving circuit needs to be cut off rapidly, the NMOS transistor needs to be turned off in time, and the protection of the front-end circuit is realized.
And step 15, if yes, turning off the NMOS transistor.
Specifically, after the NMOS transistor is turned off, the method further includes:
and step 41, discharging the electric energy at the driving end of the gate driving circuit by using the gate discharging circuit.
The technical scheme provided by the embodiment of the invention at least has the following technical effects or advantages:
in the embodiment of the invention, the current-sharing modules are arranged for the multi-path power supply, each current-sharing module can adjust the switch state and the on-resistance of the NMOS transistor according to the voltage of the power supply and the voltage of the combined output end so as to realize the current-sharing control of the current output by the power supply to the combined output end, avoid potential safety hazards caused by short circuit of the power supply, overhigh voltage of the combined output end and fluctuation of the output current, and further realize the safe current-sharing control of power supply of the multi-path power supply.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A multi-power supply current equalizing circuit is characterized by comprising: combining the output and at least two power supplies; any one of the at least two power supplies is correspondingly provided with a current equalizing module;
the current equalizing module comprises an NMOS transistor, a gate pole bleeder circuit, a gate pole driving circuit and a gate pole control processor;
the source electrode of the NMOS transistor is connected with the merging output end; the drain electrode of the NMOS transistor is connected with the output end of the power supply corresponding to the current equalizing module in the at least two power supplies;
the input end of the gate leakage circuit and the driving end of the gate driving circuit are both connected with the gate of the NMOS transistor;
the gate control processor is connected with the control end of the gate driving circuit; and the gate control processor is also respectively connected with the merging output end and the output end of the power supply corresponding to the current equalizing module in a sampling manner.
2. The multi-power-supply current sharing circuit of claim 1, wherein the gate bleed circuit comprises: the circuit comprises a first diode, a first resistor, a first capacitor and a first triode;
the anode of the first diode is connected with the gate electrode of the NMOS transistor; the cathode of the first diode is grounded through the first capacitor;
one end of the first resistor is connected with the gate electrode of the NMOS transistor, and the other opposite end of the first resistor is connected with the base electrode of the first triode;
an emitter of the first triode is connected with a cathode of the first diode; and the collector electrode of the first triode is grounded.
3. The multi-power-supply current sharing circuit of claim 1, wherein the gate bleed circuit comprises: the voltage comparator, a second resistor, a second capacitor and a second triode;
the positive input end of the voltage comparator is connected with a reference voltage end; the reverse input end of the voltage comparator is connected with the gate electrode of the NMOS transistor; the output end of the voltage comparator is connected with the base electrode of the second triode;
the emitter of the second triode is connected with the gate of the NMOS transistor; and the collector of the second triode is grounded through a parallel circuit formed by the second capacitor and the second resistor.
4. The multi-channel power supply current-sharing circuit of claim 1, wherein the current-sharing module further comprises: a third resistor, a fourth resistor, a fifth resistor and a sixth resistor;
the third resistor and the fourth resistor are connected in series between the output end of the power supply corresponding to the current equalizing module and the ground;
the first sampling input end of the gate control processor is connected between the third resistor and the fourth resistor so as to realize that the gate control processor is connected with the output end of the power supply corresponding to the current equalizing module in a sampling manner;
the fifth resistor and the sixth resistor are connected in series between the combined output end and the ground;
and the second sampling input end of the gate control processor is connected between the fifth resistor and the sixth resistor so as to realize that the gate control processor is connected with the merging output end in a sampling manner.
5. The multi-power supply current sharing circuit of claim 4 wherein the gate driver circuit is a charge pump module.
6. The multi-power-supply current-sharing circuit of claim 3, wherein the voltage comparator is an LM393 dual voltage comparator.
7. A multi-power-supply current-sharing control method applied to the multi-power-supply current-sharing circuit of any one of claims 1 to 6 comprises the following steps:
acquiring a merging end sampling voltage of a merging output end and a power supply end sampling voltage of an output end of a power supply corresponding to the current equalizing module;
acquiring equivalent load current output by the current equalizing module according to the power supply end sampling voltage and the merging end sampling voltage;
adjusting the on-resistance of the NMOS transistor according to the magnitude relation between the equivalent load current and the set current average value;
judging whether the difference value of the power supply end sampling voltage and the merging end sampling voltage is larger than a set upper limit threshold or smaller than 0;
and if so, turning off the NMOS transistor.
8. The method according to claim 7, wherein the obtaining the equivalent load current output by the current-sharing module according to the power source terminal sampling voltage and the merging terminal sampling voltage comprises:
setting an equivalent internal resistance r according to the third resistor, the fourth resistor, the fifth resistor and the sixth resistor;
calculating the equivalent load current I output by the current equalizing module, wherein the specific calculation formula is as follows:
wherein, U1Sampling voltage, U, for said power supply terminal2And sampling the voltage for the merging end.
9. The method according to claim 7, wherein the adjusting the on-resistance of the NMOS transistor according to the magnitude relationship between the equivalent load current and the set current-sharing value comprises:
if the equivalent load current is larger than the set current average value, increasing the on-resistance of the NMOS transistor;
and if the equivalent load current is smaller than the set current average value, reducing the on-resistance of the NMOS transistor.
10. The method of claim 7, wherein after the NMOS transistor is turned off, the method further comprises:
and discharging the electric energy at the driving end of the gate driving circuit by using the gate discharging circuit.
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| CN202010928255.XA CN112181037B (en) | 2020-09-07 | 2020-09-07 | Multi-path power supply current equalizing circuit and control method |
| PCT/CN2021/103370 WO2022048282A1 (en) | 2020-09-07 | 2021-06-30 | Current sharing circuit and current sharing control method for power supply of multiple power sources |
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| CN113242035A (en) * | 2021-05-08 | 2021-08-10 | 上海数明半导体有限公司 | Driver circuit based on capacitive isolation and electronic device |
| WO2022048282A1 (en) * | 2020-09-07 | 2022-03-10 | 苏州浪潮智能科技有限公司 | Current sharing circuit and current sharing control method for power supply of multiple power sources |
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2020
- 2020-09-07 CN CN202010928255.XA patent/CN112181037B/en active Active
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2021
- 2021-06-30 WO PCT/CN2021/103370 patent/WO2022048282A1/en active Application Filing
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| US20050275372A1 (en) * | 2004-06-14 | 2005-12-15 | Crowell Jonathan C | Power controller for managing arrays of smart battery packs |
| CN103731016A (en) * | 2013-12-18 | 2014-04-16 | 国网上海市电力公司 | Current equalizing circuit for power output and application thereof |
| CN106233598A (en) * | 2014-05-30 | 2016-12-14 | 松下知识产权经营株式会社 | Supply unit |
| CN110768649A (en) * | 2018-07-26 | 2020-02-07 | 台达电子工业股份有限公司 | Gate circuit and gate drive circuit of power semiconductor switch |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022048282A1 (en) * | 2020-09-07 | 2022-03-10 | 苏州浪潮智能科技有限公司 | Current sharing circuit and current sharing control method for power supply of multiple power sources |
| CN113242035A (en) * | 2021-05-08 | 2021-08-10 | 上海数明半导体有限公司 | Driver circuit based on capacitive isolation and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112181037B (en) | 2023-02-28 |
| WO2022048282A1 (en) | 2022-03-10 |
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