CN112164749A - Bipolar resistive random access memory and preparation method thereof - Google Patents
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- 238000002360 preparation method Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 230000015654 memory Effects 0.000 claims abstract description 42
- 230000008859 change Effects 0.000 claims abstract description 19
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 15
- 238000006243 chemical reaction Methods 0.000 claims description 13
- 238000004544 sputter deposition Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 10
- 229910052681 coesite Inorganic materials 0.000 claims description 9
- 229910052906 cristobalite Inorganic materials 0.000 claims description 9
- 229910052682 stishovite Inorganic materials 0.000 claims description 9
- 229910052905 tridymite Inorganic materials 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 8
- 230000008020 evaporation Effects 0.000 claims description 8
- 238000001704 evaporation Methods 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 7
- 229910052697 platinum Inorganic materials 0.000 claims description 7
- 239000000376 reactant Substances 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 229910052741 iridium Inorganic materials 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 229910052763 palladium Inorganic materials 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000012159 carrier gas Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 96
- 230000002829 reductive effect Effects 0.000 description 12
- 230000008901 benefit Effects 0.000 description 11
- 239000010408 film Substances 0.000 description 11
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 11
- 230000008569 process Effects 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000007772 electrode material Substances 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000003860 storage Methods 0.000 description 6
- 230000009471 action Effects 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000007667 floating Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 230000014759 maintenance of location Effects 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- RYTYSMSQNNBZDP-UHFFFAOYSA-N cobalt copper Chemical compound [Co].[Cu] RYTYSMSQNNBZDP-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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Abstract
The invention provides a bipolar resistive random access memory and a preparation method thereof, wherein the preparation method comprises the following steps: forming a bottom electrode on a substrate; forming a resistance change dielectric layer on the bottom electrode by adjusting radio frequency power and/or chamber pressure intensity by adopting a plasma enhanced chemical vapor deposition method; and forming an active electrode on the resistive switching medium layer to form the bipolar resistive switching memory. According to the preparation method of the bipolar resistive random access memory, the density of the resistive random access dielectric layer can be controlled by adjusting the radio frequency power and/or the pressure of the cavity, and the thickness of the resistive random access dielectric layer and the thickness of the active electrode are further adjusted by means of the change of the film deposition time, so that the bipolar resistive random access memory can integrate lower operating voltage, higher programming speed and higher stability, and the application of the device in the fields of Internet of things, embedding and the like is greatly promoted.
Description
Technical Field
The invention belongs to the field of semiconductor devices and integrated circuits, and particularly relates to a bipolar resistive random access memory device with low operating voltage, high speed and high reliability and a preparation method thereof.
Background
With the continuous advance of technical nodes, the channel length of a transistor is reduced, the quantity of stored charges is reduced, data stored in memories such as an SRAM, a DRAM and a FLASH based on charge storage is easy to lose, the performance of the device is poor, the reliability is reduced, and the prospect of the traditional memory is limited. Therefore, there is a need to further develop new types of memories based on non-charge storage. In addition, the current computer system adopts a von neumann architecture, in which a computing unit is separated from a storage unit, and a large amount of data is transported between the computing unit and the storage unit during each operation, so that the energy utilization rate is reduced, and the von neumann architecture has higher operating energy consumption and lower access speed, and further development of the computer is restricted. In order to solve the above problems, a memory-computing integrated architecture needs to be considered, and thus a new device having a memory computing function needs to be developed. Therefore, the development direction of the current memory application is to research a new device based on new materials and new storage mechanisms and having a function of integrating storage.
The resistive random access memory has the advantages of simple structure, strong area reducible property, compatibility of a preparation process and the current CMOS process, low operation energy consumption and the like, has a nonvolatile characteristic, can keep a better state after external voltage is removed, and has memory computing capability. Therefore, the metal oxide-based resistance change memory has attracted attention as a new device having a function of integrating memory, and is expected to be a new-generation memory. However, in the prior art, the operation voltage of the resistive random access memory is generally high and is difficult to match with the clock voltage of the current peripheral circuit; in addition, different types of resistive random access memories have advantages and disadvantages, and cannot integrate advantages of low operating voltage, high speed, strong stability and the like, so that the application of the resistive random access memories is limited.
Disclosure of Invention
Technical problem to be solved
The invention provides a bipolar resistive random access memory and a preparation method thereof, and aims to solve the technical problems that in the prior art, the resistive random access memory cannot be matched with a clock voltage of a peripheral circuit due to high operating voltage, and cannot integrate the advantages of low operating voltage, high speed, strong stability and the like.
(II) technical scheme
One aspect of the present invention provides a bipolar resistive random access memory, including: the resistive random access memory comprises a substrate, a bottom electrode, a resistive medium layer and an active electrode, wherein the bottom electrode is positioned on the substrate; the resistance change dielectric layer is positioned on the bottom electrode and is formed by adjusting radio frequency power and/or cavity pressure by adopting a plasma enhanced chemical vapor deposition method; the active electrode is positioned on the resistive switching medium layer to form the bipolar resistive switching memory.
Optionally, the bipolar resistive random access memory further comprises: an adhesive layer and a top electrode. The adhesion layer is positioned between the substrate and the bottom electrode; and the top electrode is positioned on the active electrode.
Optionally, the refractive index of the resistive switching medium layer is 1.488-1.545.
Optionally, the substrate is a silicon wafer with a thickness of 40nm-100 nm; the resistive switching medium layer is made of HfO2、Ta2O5And SiO2In one, the thickness is 5-20 nm; the active electrode is made of Ag, Ni, Co or Cu and has a thickness of 3-10 nm.
Optionally, the material of the adhesion layer is titanium Ti, and the thickness is 10nm-30 nm.
Optionally, the bottom electrode and the top electrode are made of conductive metal or conductive metal alloy, and the thickness of each conductive metal or conductive metal alloy is 40-100nm, wherein the conductive metal is one of Au, Pt, Pd, Ru, Ir and W, and the metal alloy is one of TiN and TaN.
The invention also discloses a preparation method of the bipolar resistive random access memory, which comprises the following steps: forming a bottom electrode on a substrate; forming a resistance change dielectric layer on the bottom electrode by adjusting radio frequency power and/or chamber pressure intensity by adopting a plasma enhanced chemical vapor deposition method; and forming an active electrode on the resistive switching medium layer to form the bipolar resistive switching memory.
Optionally, before forming the bottom electrode on the substrate, the method further includes: and carrying out thermal oxidation treatment on the substrate, and forming an adhesion layer on the substrate subjected to the thermal oxidation treatment by adopting a radio frequency magnetron sputtering method.
Optionally, forming a bottom electrode on the substrate comprises: and forming a bottom electrode on the adhesion layer by adopting a direct current sputtering method, a magnetron sputtering method or an evaporation coating method.
Optionally, forming an active electrode on the resistive switching medium layer includes: and forming an active electrode on the resistance change dielectric layer by adopting a direct current sputtering method.
Optionally, after forming the active electrode on the resistive switching medium layer, the method further includes: and forming a top electrode on the active electrode by adopting a direct current sputtering method, a magnetron sputtering method or an evaporation coating method.
Optionally, forming a resistive medium layer on the bottom electrode by adjusting the radio frequency power and/or the chamber pressure by using a plasma enhanced chemical vapor deposition method, including: SiH with a gas flow of 12sccm4And N with a gas flow rate of 1420sccm2O is reactant, the temperature of the substrate is 200-400 ℃ as reaction condition, a plasma enhanced chemical vapor deposition method is adopted, and SiO is formed on the bottom electrode by adjusting the radio frequency power and/or the chamber pressure2The resistance change medium layer, wherein the adjusting range of the cavity pressure is 400mT-600mT, and the adjusting range of the radio frequency power is 20W-90W.
Alternatively, the reactant SiH4The carrier gas of (a) is N2.
(III) advantageous effects
The invention provides a bipolar resistive random access memory and a preparation method thereof, wherein the preparation method comprises the following steps: forming a bottom electrode on a substrate; forming a resistance change dielectric layer on the bottom electrode by adjusting radio frequency power and/or chamber pressure intensity by adopting a plasma enhanced chemical vapor deposition method; and forming an active electrode on the resistive switching medium layer to form the bipolar resistive switching memory. According to the preparation method of the bipolar resistive random access memory, the density of the resistive random access dielectric layer can be controlled by adjusting the radio frequency power and/or the pressure of the cavity, and the conditions of the resistive random access dielectric layer and the thickness are further realized by means of the change of the film deposition time, so that the bipolar resistive random access memory can adjust the operating voltage. In addition, by the preparation method, the thickness of the active electrode can be adjusted at the same time, so that the stability of a conductive channel of the bipolar resistive random access memory can be improved. Therefore, the bipolar memory can integrate lower operating voltage, higher programming speed and higher stability, and greatly promotes the application of the device in the fields of Internet of things, embedding and the like.
Drawings
Fig. 1 schematically shows a flow chart of a method for manufacturing a bipolar resistive random access memory according to an embodiment of the present invention;
fig. 2 schematically shows a structural composition diagram of a bipolar resistive random access memory according to an embodiment of the present invention;
fig. 3 schematically illustrates a current-voltage characteristic diagram of a bipolar resistive random access memory according to an embodiment of the present invention;
fig. 4 schematically shows an endurance characteristic diagram of a bipolar resistance change memory according to an embodiment of the present invention;
fig. 5 schematically shows a retention characteristic diagram of a bipolar resistive random access memory according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.
It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure.
And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
The use of ordinal numbers such as "first," "second," "third," etc., in the specification and in the claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element from another or the order of manufacture, and the use of the ordinal numbers is only used to distinguish one element having a certain name from another element having a same name.
Those skilled in the art will appreciate that the modules in the device of an embodiment may be adaptively changed and placed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.
Memories are memory devices used in modern information technology for storing information, the main function of which is to store various data and programs, and the memory function is usually implemented by using physical devices (memory cells) having two stable states (respectively denoted as "0" and "1").
Currently, the mainstream nonvolatile semiconductor memory mainly adopts a flash memory with a floating gate structure. The structure of floating gate flash memories has not changed much in the last 30 years, and its main development direction is the reduction of feature size. However, the memory of the floating gate structure has some other problems such as deterioration of stability and the like in succession along with the reduction in size.
A Resistive Random Access Memory (RRAM) using a resistance transformation effect as a working principle is one of the most promising next-generation nonvolatile memories. Compared with the traditional floating gate flash memory, the floating gate flash memory has obvious advantages in the aspects of device structure, speed, scalability, three-dimensional integration potential and the like. The resistive random access memory is of a sandwich structure consisting of an upper electrode layer, a lower electrode layer and a resistance conversion layer between the upper electrode layer and the lower electrode layer, wherein the resistance conversion layer can perform reversible conversion between different resistance states under the action of different external voltage and current signals, and the resistance conversion layer is usually in a high resistance state and a low resistance state.
However, in the prior art, the operation voltage of the resistive random access memory is generally high and is difficult to match with the clock voltage of the current peripheral circuit; in addition, different types of resistive random access memories have advantages and disadvantages, and cannot integrate advantages of low operating voltage, high speed, strong stability and the like, so that the application of the resistive random access memories is limited.
The invention provides a bipolar resistive random access memory and a preparation method thereof, and aims to solve the technical problems that in the prior art, the resistive random access memory cannot be matched with a clock voltage of a peripheral circuit due to high operating voltage, and cannot integrate the advantages of low operating voltage, high speed, strong stability and the like.
As shown in fig. 1, an aspect of the present invention provides a method for manufacturing the bipolar resistive random access memory, including:
step S101, forming a bottom electrode on a substrate;
step S102, forming a resistance change medium layer on the bottom electrode by adjusting radio frequency power and/or chamber pressure through a plasma enhanced chemical vapor deposition method;
and S103, forming an active electrode on the resistive switching medium layer to form the bipolar resistive switching memory.
As shown in fig. 2, the bipolar resistive random access memory according to the embodiment of the present invention includes: the resistive random access memory comprises a substrate 210, a bottom electrode 220, a resistive random access dielectric layer 230, an active electrode 240 and a top electrode 250 from bottom to top in sequence. The resistive medium layer 230 is positioned between the active electrode 240 and the bottom electrode 220, the resistive medium layer 230 forms a conductive channel communicating the upper electrode and the lower electrode under the action of an electric field, when a forward voltage is applied to the device, the conductive channel is maintained, the memory device is in a low-resistance state, the corresponding stored data of the device is '0', and conversely, when a reverse voltage is applied to the memory device, the conductive channel is disconnected, the device is in a high-resistance state, and the corresponding stored data of the device is '1'.
As shown in fig. 1 and 2, according to an embodiment of the present invention, at step S102: forming a resistance change medium layer on the bottom electrode by adjusting radio frequency power and/or chamber pressure by adopting a plasma enhanced chemical vapor deposition method, wherein the method comprises the following steps: SiH with a gas flow of 12sccm4And N with a gas flow rate of 1420sccm2O is a reactant, and the reaction is carried out,the temperature of the substrate is 200-400 ℃ as the reaction condition, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method is adopted, and SiO is formed on the bottom electrode by adjusting the radio frequency power and/or the chamber pressure2The resistance change medium layer, wherein the adjusting range of the cavity pressure is 400mT-600mT, and the adjusting range of the radio frequency power is 20W-90W.
According to an embodiment of the invention, the reactant SiH4The carrier gas is nitrogen N2And nitrogen gas N2The gas flow rate of (2) may be 392 sccm.
According to the embodiment of the invention, the refractive index of the resistive switching medium layer is 1.488-1.545, so that the compactness effect of the resistive switching medium layer is better.
According to the embodiment of the invention, the resistive switching medium layer is made of materials except the SiO2In addition, HfO may be used2Or Ta2O5The thickness is 5-20 nm.
In the embodiment of the present invention, the substrate temperature of the reaction condition for preparing the resistive switching medium layer 230 may be 200 ℃ to 400 ℃, and specifically may be 300 ℃. The substrate is used for arranging a plate-shaped object with a substrate structure (such as a silicon wafer) of the bottom electrode 220 in the process of preparing the resistive switching medium layer 230. Therefore, the preparation process of the bipolar resistive random access memory can adopt a low-temperature process compatible with a CMOS (complementary metal oxide semiconductor) process, so that the preparation of the bipolar resistive random access memory is easier for industrial production.
In the embodiment of the invention, the adjustment of the film density of the resistive dielectric layer 230 can be realized by adjusting the radio frequency power in the plasma enhanced chemical vapor deposition method. Specifically, when the radio frequency power is enhanced, the energy obtained by the plasma is increased, the migration capability of ions on the surface of the substrate is enhanced, and the products are easier to migrate to the position with the lowest energy for uniform arrangement, so that the generated film structure is more compact; of course, as the rf power continues to increase, the reaction rate further increases, and the particles reaching the substrate surface may not have enough time to be regularly arranged and may be covered by the particles subsequently reaching the substrate, thereby forming a dense and uniform film layer. Therefore, the adjustment range of the radio frequency power in the embodiment of the invention is 20W-90W, and specifically, 30W-70W may be selected, for example, 30W, 35W, 40W, 45W, 50W, 55W, 60W, 65W and 70W, for example, 40W, so as to ensure that the compactness of the resistive switching medium layer 230 film achieves the best effect.
In the embodiment of the present invention, the adjustment of the density of the thin film of the resistive switching medium layer 230 can be realized by adjusting the chamber pressure in the plasma enhanced chemical vapor deposition method. Specifically, when the pressure of the cavity is increased, the mean free path of reactants is reduced, the acceleration of ions is limited, the migration capability on the surface of the substrate is weakened, the reaction rate is increased, and the particles reaching the surface of the substrate are covered by the particles which subsequently reach the substrate without enough time for regular arrangement, so that the density of the film is lowered; conversely, when the chamber pressure is reduced, the densification of the film is enhanced. For this reason, the chamber pressure of the embodiment of the invention is adjusted within a range of 400mT to 600mT, for example, one of 400mT, 450mT, 500mT, 550mT, 600mT, and the like, for example, 550mT, so as to achieve the best compactness of the thin film of the resistive switching medium layer 230. The adjustment of the radio frequency power and the chamber pressure can affect the density of the film, so that the radio frequency power and the chamber pressure can be adjusted respectively and independently or simultaneously, the two actions are restricted mutually, the density of the film is affected jointly, and the density of the film is optimal. For this purpose, RF power of 40W may be selected, and chamber pressure of 550mT is used as a reaction condition when RF power and chamber pressure are adjusted simultaneously.
The film density (or called density) of the resistive dielectric layer 230 affects the operation speed of the device, and specifically, the density of the resistive dielectric layer 230 is reduced, and the diffusion barrier for Ag ions to move in the resistive dielectric layer 230 is reduced, so that the Ag ions can more easily move in the dielectric layer under the action of an external electric field, thereby accelerating the formation or disconnection of a conductive channel, and improving the operation speed of the device.
In addition, the thickness of the resistive switching medium layer 230 may also directly affect the operating voltage, and specifically, for the newly prepared memory device, the resistive switching medium layer 230 is not yet formedForming a channel, and dividing the initial voltage applied to the device by the resistance of the resistive switching medium layer 230, so as to drive the Ag ions to enter the resistive switching medium layer 230 and migrate in the medium layer. Therefore, the thickness of the resistive switching medium layer 230 is reduced, the resistance value of the resistive switching medium layer 230 can be reduced, and the partial voltage on the resistive switching medium layer 230 is reduced, so that the initial operating voltage for forming a channel of the device is reduced. In the embodiment of the invention, the thickness of the resistive switching medium layer 230 is between 5nm and 20nm, and 20nm is preferred. Further, the forming material of the resistive switching medium layer 230 may be selected from hafnium oxide HfO2Tantalum oxide Ta2O5And silica SiO2One of the layers is selected to ensure the stable performance of the resistance change medium layer. In the embodiment of the invention, the resistive switching medium layer 230 may be silicon dioxide SiO2To prepare the material.
Therefore, the preparation method of the bipolar resistive random access memory provided by the embodiment of the invention can realize the conditions of density and thickness of the resistive random access dielectric layer by adjusting the radio frequency power and/or the pressure of the cavity, so that the bipolar resistive random access memory provided by the invention can realize the adjustment of the operating voltage. In addition, by the preparation method, the thickness of the active electrode can be adjusted at the same time, so that the stability of a conductive channel of the bipolar resistive random access memory can be improved. Therefore, the bipolar memory can integrate lower operating voltage, higher programming speed and higher stability, and greatly promotes the application of the device in the fields of Internet of things, embedding and the like.
As shown in fig. 1 and 2, according to an embodiment of the present invention, at step S101: before forming the bottom electrode 220 on the substrate 210, the preparation method further includes: the substrate 210 is subjected to thermal oxidation, and an adhesion layer is formed on the substrate 210 subjected to the thermal oxidation by a radio frequency magnetron sputtering method.
According to the embodiment of the invention, the substrate is a silicon wafer, and the thickness is 40nm-100 nm; the material of the adhesion layer is titanium Ti, and the thickness is 10nm-30 nm.
In the embodiment of the present invention, when the substrate 210 is a silicon wafer, an ultra-thin dense silicon dioxide layer may be formed on the surface of the substrate 210 after the substrate 210 is thermally oxidized. The adhesion layer may better form a stable structure with the surface of the substrate 210 on the one hand and with the lower surface of the bottom electrode 220 on the other hand. Specifically, the material for forming the adhesion layer may be titanium Ti, and the thickness may be in a range of 10nm to 30nm, and may be specifically selected to be a thickness of 20 nm.
It should be noted that the adhesion layer is located between the dense silicon dioxide layer of the substrate 210 and the bottom electrode 220, which is not explicitly shown in fig. 2. In fact, the substrate 210 (including the dense silicon dioxide layer formed on the surface thereof) and the above-mentioned adhesion layer structure as a whole function as the device substrate of the embodiment of the present invention, and are used for supporting the main structure of the device, such as the bottom electrode 220, the resistive switching medium layer 230 and the active electrode 240.
As shown in fig. 1 and 2, according to an embodiment of the present invention, at step S101: in forming the bottom electrode 220 on the substrate 210, there are included: the bottom electrode 220 is formed on the adhesion layer by a direct current sputtering method, a magnetron sputtering method, or an evaporation coating method.
The bottom electrode 220 is used to lead out the lower electrode of the device as a port for connecting the device. The bottom electrode 220 is formed on the surface of the adhesive layer on the upper surface of the substrate 210. The bottom electrode material can be conductive metal or conductive metal alloy with the thickness of 40-100nm, wherein the conductive metal is one of Au, Pt, Pd, Ru, Ir and W, and the metal alloy is one of TiN and TaN. Specifically, in the embodiment of the invention, a platinum Pt layer can be directly sputtered on the adhesion layer by direct current as a bottom electrode, and the thickness can be 100 nm. The method for sputtering the bottom electrode can be one of a direct current sputtering method, a magnetron sputtering method, an evaporation coating method and the like, and the specific preparation method is different according to the difference of the bottom electrode material and the difference of the preparation process, and is not described again here.
As shown in fig. 1 and 2, according to an embodiment of the present invention, at step S103: the forming of the active electrode on the resistive switching medium layer comprises the following steps: an active electrode 240 is formed on the resistive switching medium layer 230 by a direct current sputtering method.
The active electrode is used for providing metal ions for the formation of the conductive channel in the resistive switching medium layer 230, so that the metal ions entering the resistive switching medium layer 230 form a robust and stable conductive channel under the condition that an external field voltage is applied to the resistive switching medium layer 230, and the resistive switching memory device structure provided by the invention has higher operation stability so as to meet the requirements of a nonvolatile memory. The forming material of the active electrode can be silver Ag, nickel Ni, cobalt Co or copper Cu, so as to ensure good conductive effect. In addition, the active electrode needs to maintain a certain thickness, taking the active electrode 240 as a silver Ag layer as an example, if the thickness is too thin, the amount of Ag ions provided by the active electrode is small, and under the action of an external electric field, the Ag ions entering the resistive switching medium layer 230 are not enough to form a robust and stable conductive channel, after the voltage is removed, at a high temperature, the Ag atoms forming the conductive channel diffuse to the surroundings, the channel gradually dissolves, and the low resistance state cannot be maintained, so that the requirement of the nonvolatile memory cannot be met. Specifically, the thickness of the active electrode material can be 3nm-10nm, and a silver Ag layer of 5nm can be selected as the active electrode in the embodiment of the invention.
According to an embodiment of the present invention, in step S103: after the active electrode 240 is formed on the resistive switching medium layer 230, the method further includes: the top electrode 250 is formed on the active electrode 240 by a direct current sputtering method, a magnetron sputtering method, or an evaporation coating method.
The top electrode 250 is mainly used as a protective layer of the active electrode 240 to further form a probe contact layer, which is used as an upper electrode of the device to form another port for device connection. The top electrode 250 is formed on the upper surface of the active electrode 240. The top electrode material can be conductive metal or conductive metal alloy, the thickness of the top electrode material is 40-100nm, wherein the conductive metal is one of Au, Pt, Pd, Ru, Ir and W, and the metal alloy is one of TiN and TaN. Specifically, in an embodiment of the present invention, a Pt layer may be dc sputtered on the upper surface of the active electrode 240 as a top electrode, and the thickness may be 100 nm. The method for sputtering the top electrode can be one of a direct current sputtering method, a magnetron sputtering method, an evaporation coating method and the like, and the specific preparation method is different according to the difference of the bottom electrode material and the difference of the preparation process, and is not described again here.
According to the bookIn the embodiment of the invention, the material of the resistive switching medium layer is SiO2The thickness is 5-20 nm; the active electrode is made of Ag, Ni, Co or Cu with a thickness of 3-10 nm; the bottom electrode and the top electrode are made of conductive metal or conductive metal alloy, the thickness of the bottom electrode and the thickness of the top electrode are 40-100nm, the conductive metal is one of gold Au, platinum Pt, palladium Pd, ruthenium Ru, iridium Ir and tungsten W, and the metal alloy is one of titanium nitride TiN and tantalum nitride TaN.
It should be noted that the active electrode 240 and the top electrode 250 need to be further subjected to photolithography for patterning. Specifically, patterns of the active electrode 240 and the top electrode 250 are prepared through photoetching, the active electrode 240 and the top electrode 250 are patterned through stripping operation, and the photoresist is removed after the resistive switching medium layer 230 is etched, so that the device structure of the bipolar resistive switching memory in the embodiment of the invention is obtained.
Further, the bipolar resistive random access memory according to the embodiment of the invention shown in fig. 2 is actually a specific memory cell structure, and a memory cell array and a peripheral circuit composed of a plurality of the memory cell structures can form a specific bipolar resistive random access memory device to realize specific commercial applications.
As shown in fig. 2, an aspect of the present invention provides a bipolar resistive random access memory, including: the resistive random access memory comprises a substrate 210, a bottom electrode 220, a resistive dielectric layer 230 and an active electrode 240, wherein the bottom electrode 220 is positioned on the substrate 210; the resistive medium layer 230 is positioned on the bottom electrode 220, and the resistive medium layer 230 is formed by adjusting the radio frequency power and/or the pressure intensity of the cavity by adopting a plasma enhanced chemical vapor deposition method; the active electrode 240 is located on the resistive switching medium layer 230 to form a bipolar resistive switching memory.
According to an embodiment of the present invention, the bipolar resistive random access memory further includes: an adhesive layer, and a top electrode 250. The adhesion layer is located between the substrate 210 and the bottom electrode 220; the top electrode 250 is positioned on the active electrode 240.
According to the embodiment of the invention, the refractive index of the resistive switching medium layer 230 is 1.488-1.545.
According to an embodiment of the present invention, the substrate 210 is a silicon wafer with a thickness of 40nm-100 nm; resistance deviceThe material of the variable dielectric layer 230 is HfO2、Ta2O5And SiO2In one, the thickness is 5-20 nm; the active electrode 240 is made of Ag, Ni, Co or Cu and has a thickness of 3-10 nm.
According to the embodiment of the invention, the material of the adhesion layer is titanium Ti, and the thickness is 10nm-30 nm.
According to the embodiment of the present invention, the bottom electrode 220 and the top electrode 250 are made of conductive metal or conductive metal alloy, and the thickness of each conductive metal or conductive metal alloy is 40-100nm, wherein the conductive metal is one of Au, Pt, Pd, Ru, Ir, and W, and the metal alloy is one of TiN and TaN.
The structure of the bipolar resistive random access memory is shown in fig. 2, and is obtained by the preparation method shown in fig. 1. Therefore, for the specific content of the bipolar resistive random access memory, reference may be made to the above description on the manufacturing method of the device, and details are not repeated here.
As shown in fig. 3, according to the current-voltage characteristic curve of the bipolar resistive random access memory of the embodiment of the invention, it can be seen that when a positive voltage is applied to the bipolar resistive random access memory of the embodiment of the invention, the device is programmed to "0", and the device is in a low resistance state; conversely, when a negative voltage is applied thereto, the device is reset to "1", and the device is in a high resistance state. As shown in fig. 3, when a positive voltage is applied to reach about 0.23V, the device is turned on, and the current reaches the current limit of 1 mA; when negative voltage is applied to reach about-0.21V, the device starts to be turned off, the current drops along with the increase of the voltage, and the device is in a set high-resistance state after the negative voltage reaches-1.0V of cutoff voltage. Therefore, by the preparation method of the bipolar resistive random access memory provided by the embodiment of the invention, the bipolar resistive random access memory can have a stable high-resistance state and low-resistance state conversion process.
As shown in fig. 4, according to the endurance characteristic diagram of the bipolar resistive random access memory of the embodiment of the invention, when the operation mode of the device is "program-read resistance-erase-read resistance", the device is programmed and erased by using the pulse voltage, the pulse width is fixed to 50ns, the program pulse uses a positive voltage and the amplitude is 0.79V, and the erase pulse uses a negative voltage and the amplitude is 0.49V. Wherein the number of erasingNumber more than 106Next, the ratio between the high resistance state and the low resistance state is kept around 10. Therefore, by the preparation method of the bipolar resistive random access memory, the bipolar resistive random access memory can be erased and written by adopting pulse voltage, the operation voltage is low, the operation speed is high, the erasable times are many, the states of 0 and 1 are kept to be obviously distinguishable, and the method has better erasable characteristics.
As shown in fig. 5, according to the retention characteristic diagram of the bipolar resistive random access memory according to the embodiment of the invention, it can be seen that in an environment of 125 ℃, the high resistance state and the low resistance state of the bipolar resistive random access memory are respectively read every 100s, wherein the ratio between the high resistance state and the low resistance state exceeds 10, and the two resistance states are clearly distinguishable. That is, the bipolar resistive random access memory still has good retention characteristics at high temperature.
In summary, by the above method for manufacturing the bipolar resistive random access memory according to the embodiment of the invention, the absolute value of the operating voltage (for example, the turn-on voltage and the turn-off voltage) of the bipolar resistive random access memory can be less than 0.5V, and the retention characteristic exceeds 10 in an environment at 125 ℃4Second, in pulse operation mode, programming time is 50ns, and the repeatable erasing times are more than 106Next, the process is carried out. Therefore, the preparation method provided by the embodiment of the invention can integrate the advantages of the bipolar resistive random access memory such as lower operating voltage, higher programming speed and higher stability, so that the bipolar resistive random access memory provided by the embodiment of the invention can be applied to the fields of Internet of things, embedding and the like, and has higher commercial utilization value and scientific research value.
So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (13)
1. A bipolar resistive random access memory, comprising:
a bottom electrode on the substrate;
the resistance change dielectric layer is positioned on the bottom electrode and is formed by adjusting radio frequency power and/or cavity pressure by adopting a plasma enhanced chemical vapor deposition method;
and the active electrode is positioned on the resistive switching medium layer to form the bipolar resistive switching memory.
2. The bipolar resistive-switching memory according to claim 1,
the resistive switching medium layer is made of HfO2、Ta2O5And SiO2In one, the thickness is 5-20 nm;
the refractive index of the resistance change medium layer is 1.488-1.545.
3. The bipolar resistive-switching memory according to claim 1,
the substrate is a silicon wafer, and the thickness of the substrate is 40nm-100 nm;
the active electrode is made of Ag, Ni, Co or Cu and has a thickness of 3-10 nm.
4. The bipolar resistive-switching memory according to claim 1, further comprising:
an adhesion layer between the substrate and the bottom electrode;
a top electrode on the active electrode.
5. The bipolar resistive-switching memory according to claim 4,
the material of the adhesion layer is titanium Ti, and the thickness of the adhesion layer is 10nm-30 nm.
6. The bipolar resistive random access memory according to claim 4, wherein the bottom electrode and the top electrode are made of conductive metal or conductive metal alloy, and the thickness of the conductive metal or conductive metal alloy is 40-100nm, wherein the conductive metal is one of Au, Pt, Pd, Ru, Ir and W, and the metal alloy is one of TiN and TaN.
7. The preparation method of the bipolar resistive random access memory according to any one of claims 1 to 6, comprising the following steps:
forming a bottom electrode on a substrate;
forming a resistance change dielectric layer on the bottom electrode by adjusting radio frequency power and/or chamber pressure by adopting a plasma enhanced chemical vapor deposition method;
and forming an active electrode on the resistive switching medium layer to form the bipolar resistive switching memory.
8. The method of claim 7, wherein before forming the bottom electrode on the substrate, further comprising:
performing thermal oxidation treatment on the substrate,
and forming an adhesion layer on the substrate subjected to the thermal oxidation treatment by adopting a radio frequency magnetron sputtering method.
9. The method of claim 8, wherein the forming a bottom electrode on a substrate comprises:
and forming the bottom electrode on the adhesion layer by adopting a direct-current sputtering method, a magnetron sputtering method or an evaporation coating method.
10. The preparation method according to claim 7, wherein the forming of the active electrode on the resistive switching medium layer comprises:
and forming an active electrode on the resistance change dielectric layer by adopting a direct current sputtering method.
11. The preparation method according to claim 7, wherein after the forming of the active electrode on the resistive switching medium layer, the method further comprises:
and forming a top electrode on the active electrode by adopting a direct current sputtering method, a magnetron sputtering method or an evaporation coating method.
12. The preparation method according to claim 7, wherein forming a resistive medium layer on the bottom electrode by adjusting radio frequency power and/or chamber pressure by using a plasma enhanced chemical vapor deposition method comprises:
SiH with a gas flow of 12sccm4And N with a gas flow rate of 1420sccm2O is a reactant, the temperature of the substrate is 200-400 ℃ as a reaction condition, a plasma enhanced chemical vapor deposition method is adopted, and SiO is formed on the bottom electrode by adjusting the radio frequency power and/or the chamber pressure2The resistance change medium layer, wherein the adjusting range of the cavity pressure is 400mT-600mT, and the adjusting range of the radio frequency power is 20W-90W.
13. The production method according to claim 12,
the reactant SiH4The carrier gas of (A) is N2。
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