CN112150961A

CN112150961A - Gate drive circuit and drive method thereof, display panel and display device

Info

Publication number: CN112150961A
Application number: CN202011119896.7A
Authority: CN
Inventors: 马向文
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2020-10-19
Filing date: 2020-10-19
Publication date: 2020-12-29
Anticipated expiration: 2040-10-19
Also published as: CN112150961B

Abstract

The embodiment of the invention discloses a gate drive circuit, a control method thereof, a display panel and a display device. The grid driving circuit comprises N stages of cascaded shift registers, wherein each shift register comprises: the first output control module is used for transmitting the voltage of the first voltage end to the output end; the second output control module is used for transmitting the voltage of the second voltage end to the output end; the first node control module transmits the voltage of the first input end to a first node and transmits the voltage of the second voltage end to the first node; the second node control module transmits the voltage of the second voltage end to a second node and transmits the voltage of the second clock signal end to the second node; and the third node control module is used for transmitting the voltage of the first voltage end to the third node and transmitting the voltage of the first clock signal end to the third node. The technical scheme provided by the embodiment of the invention can ensure that the gate driving circuit has simple structure and low cost.

Description

Gate drive circuit and drive method thereof, display panel and display device

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a gate driving circuit, a control method of the gate driving circuit, a display panel and a display device.

Background

At present, a display panel on the market generally includes a display area and a non-display area, sub-pixel units are arranged in the display area in an array manner, and a gate driving circuit is arranged in the non-display area, wherein the gate driving circuit is used for outputting a gate driving signal to control the sub-pixel units in the display area to sequentially emit light. Therefore, the gate driving circuit has been a great research focus in the display field, and it is a necessary trend to provide a gate driving circuit with a simple structure.

Disclosure of Invention

The invention provides a gate driving circuit, a control method thereof, a display panel and a display device, and provides the gate driving circuit which is simple in structure and low in cost.

In a first aspect, an embodiment of the present invention provides a gate driving circuit, where the gate driving circuit includes:

n stages of cascaded shift registers, wherein N is an integer greater than or equal to 2; the shift register includes: a first voltage terminal, a second voltage terminal, a first input terminal, an output terminal, a first clock signal terminal, a second clock signal terminal, and,

the first output control module is used for responding to the conducting level of a first node and transmitting the voltage of the first voltage end to the output end;

the second output control module is used for responding to the conducting level of a second node and transmitting the voltage of the second voltage end to the output end;

a first node control module for transmitting a voltage of the first input terminal to the first node in response to a turn-on level of the first clock signal terminal, and transmitting a voltage of the second voltage terminal to the first node in response to turn-on levels of the second clock signal terminal and a third node;

a second node control module for transmitting a voltage of the second voltage terminal to the second node in response to a turn-on level of the first node, and transmitting a voltage of the second clock signal terminal to the second node in response to turn-on levels of the third node and the second clock signal terminal;

and a third node control module for transmitting the voltage of the first voltage terminal to the third node in response to the turn-on level of the first clock signal terminal, and transmitting the voltage of the first clock signal terminal to the third node in response to the turn-on levels of the first input terminal and the first clock signal terminal.

In a second aspect, an embodiment of the present invention further provides a display panel, where the display panel includes the gate driving circuit of the second aspect.

In a third aspect, an embodiment of the present invention further provides a display device, which includes the display panel described in the third aspect.

In a fourth aspect, an embodiment of the present invention further provides a driving method of a gate driving circuit, where the method includes:

the first node control module transmits the voltage of the first input terminal to the first node in response to the turn-on level of the first clock signal terminal during a period T1; the first output control module responds to the conducting level of the first node and transmits the voltage of the first voltage end to the output end;

the first output control module transmits the voltage of the first voltage terminal to the output terminal in response to the turn-on level of the first node during a period T2;

in a T3 phase, the output terminal keeps outputting the voltage output in the T2 phase;

in a stage T4, the second node control module transmits the voltage of the second clock signal terminal to the second node in response to the turn-on levels of the third node and the second clock signal terminal; the second output control module responds to the conducting level of the second node and transmits the voltage of the second voltage end to the output end;

the second output control module transmits the voltage of the second voltage terminal to the output terminal in response to the conduction level of the second node during a stage T5;

in a stage T6, the second node control module transmits the voltage of the second clock signal terminal to the second node in response to the turn-on levels of the third node and the second clock signal terminal; the second output control module responds to the conducting level of the second node and transmits the voltage of the second voltage end to the output end;

the first node control module transmits the voltage of the first input terminal to the first node in response to the turn-on level of the first clock signal terminal during a period T7; the first output control module responds to the conducting level of the first node and transmits the voltage of the first voltage end to the output end;

in the stage T8, the first output control module transmits the voltage of the first voltage terminal to the output terminal in response to the turn-on level of the first node.

In the gate driving circuit provided in the embodiment of the present invention, by setting the shift register including N stages of cascade connection, where the shift register includes the first output control module, the second output control module, the first node control module, the second node control module, and the third node control module, the first output control module transmits the voltage of the first voltage terminal to the output terminal in response to the conduction level of the first node, and the second output control module transmits the voltage of the second voltage terminal to the output terminal in response to the conduction level of the second node, a problem that a gate driving circuit with a simple structure is urgently required in the prior art is solved, and effects of simplifying the gate driving circuit and reducing cost are achieved.

Drawings

Fig. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

fig. 3 is a driving timing diagram of a gate driving circuit according to an embodiment of the invention;

fig. 4 is a flowchart illustrating a driving method of a gate driving circuit according to an embodiment of the invention;

FIG. 5 is a circuit diagram of a shift register according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another gate driving circuit according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating an alternative shift register according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating a structure of another shift register according to an embodiment of the present invention;

FIG. 9 is a diagram illustrating a shift register according to another embodiment of the present invention;

FIG. 10 is a circuit diagram of another shift register according to an embodiment of the present invention;

fig. 11 is a driving timing chart of the shift register shown in fig. 10;

FIG. 12 is a circuit diagram of a shift register according to another embodiment of the present invention;

fig. 13 is a driving timing chart of the shift register shown in fig. 12;

FIG. 14 is a circuit diagram of a shift register according to another embodiment of the present invention;

fig. 15 is a driving timing chart of the shift register shown in fig. 14;

fig. 16 is a circuit diagram of a shift register according to an embodiment of the present invention;

fig. 17 is a driving timing chart of the shift register shown in fig. 16;

FIG. 18 is a circuit diagram of another shift register according to an embodiment of the present invention;

FIG. 19 is a circuit diagram of a shift register according to another embodiment of the present invention;

FIG. 20 is a circuit diagram of a shift register according to another embodiment of the present invention;

fig. 21 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

In view of the problems mentioned in the background, an embodiment of the present invention provides a gate driving circuit, including: n stages of cascaded shift registers, wherein N is an integer greater than or equal to 2;

the shift register includes: a first voltage terminal, a second voltage terminal, a first input terminal, an output terminal, a first clock signal terminal, a second clock signal terminal, and,

the first output control module is used for responding to the conducting level of the first node and transmitting the voltage of the first voltage end to the output end;

the second output control module is used for responding to the conducting level of the second node and transmitting the voltage of the second voltage end to the output end;

the first node control module is used for responding to the conducting level of the first clock signal end and transmitting the voltage of the first input end to the first node, and responding to the conducting levels of the second clock signal end and the third node and transmitting the voltage of the second voltage end to the first node;

the second node control module is used for responding to the conducting level of the first node, transmitting the voltage of the second voltage end to the second node, and responding to the conducting levels of the third node and the second clock signal end, and transmitting the voltage of the second clock signal end to the second node;

and the third node control module is used for responding to the conduction level of the first clock signal end, transmitting the voltage of the first voltage end to the third node, and responding to the conduction levels of the first input end and the first clock signal end, and transmitting the voltage of the first clock signal end to the third node.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.

Fig. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention. Fig. 2 is a schematic structural diagram of a shift register 10 according to an embodiment of the present invention. Referring to fig. 1 and 2, the gate driving circuit includes: n stages of cascaded shift registers 10, wherein N is an integer greater than or equal to 2; the shift register 10 includes: a first voltage terminal VGL, a second voltage terminal VGH, a first input terminal IN1, an output terminal OUT, a first clock signal terminal CK, a second clock signal terminal XCK, and a first output control module 110 for transmitting a voltage of the first voltage terminal VGL to the output terminal OUT IN response to a turn-on level of a first node N1; the second output control module 120 for transmitting the voltage of the second voltage terminal VGH to the output terminal OUT in response to the turn-on level of the second node N2; a first node control module 130 for transmitting the voltage of the first input terminal IN1 to the first node N1 IN response to the turn-on level of the first clock signal terminal CK, and transmitting the voltage of the second voltage terminal VGH to the first node N1 IN response to the turn-on levels of the second clock signal terminal XCK and the third node N3; a second node control module 140 for transmitting the voltage of the second voltage terminal VGH to the second node N2 in response to the turn-on level of the first node N1, and transmitting the voltage of the second clock signal terminal XCK to the second node N2 in response to the turn-on levels of the third node N3 and the second clock signal terminal XCK; the third node control module 150 transmits the voltage of the first voltage terminal VGL to the third node N3 IN response to the turn-on level of the first clock signal terminal CK, and transmits the voltage of the first clock signal terminal CK to the third node N3 IN response to the first input terminal IN1 and the turn-on level of the first clock signal terminal CK.

Specifically, with reference to fig. 1, when the gate driving circuit is applied to the display panel, the first voltage terminal VGL of each shift register 10 is electrically connected to the first voltage signal line VGL of the display panel, the second voltage terminal VGH is electrically connected to the second voltage signal line VGH of the display panel, the first clock signal terminal CK is electrically connected to the first clock signal line CK of the display panel, and the second clock signal terminal XCK is electrically connected to the second clock signal line XCK of the display panel. The first input terminal IN1 of the first stage shift register 10 is electrically connected to the trigger signal line stv of the display panel, and the first input terminals IN1 of the second stage shift register 10 to the nth stage shift register 10 are electrically connected to the output terminal OUT of the previous stage shift register 10.

Specifically, with continued reference to fig. 2, the first output control module 110 is electrically connected to the first node N1, the first voltage terminal VGL, and the output terminal OUT; the second output control module 120 is electrically connected to the second node N2, the second voltage terminal VGH and the output terminal OUT; the first node control module 130 is electrically connected to the first clock signal terminal CK, the first input terminal IN1, the second clock signal terminal XCK, the second voltage terminal VGH, the third node N3, and the first node N1; the second node control module 140 is electrically connected to the first node N1, the second voltage terminal VGH, the third node N3, the second clock signal terminal XCK, and the second node N2; the third node control module 150 is electrically connected to the first clock signal terminal CK, the first voltage terminal VGL, the first input terminal IN1 and the third node N3.

It should be noted that, the shift register 10 includes transistors, and the on level and the off level in the embodiment of the present invention are distinguished according to the types of the transistors, the on level refers to a level capable of controlling the transistors to be turned on, and the off level refers to a level capable of controlling the transistors to be turned off, for example, when the transistors are P-type transistors, the on level is a low level, and the off level is a high level; when the transistor is an N-type transistor, the on level is high and the off level is low. It should be noted that one of the first voltage terminal VGL and the second voltage terminal VGH outputs a high level and the other outputs a low level. For convenience of illustration, the transistors are P-type transistors, the first voltage terminal VGL outputs a low level, and the second voltage terminal VGH outputs a high level, in which case, the on level is a low level and the off level is a high level.

Fig. 3 is a driving timing diagram of a gate driving circuit according to an embodiment of the invention. Fig. 4 is a flowchart illustrating a driving method of a gate driving circuit according to an embodiment of the present invention. The driving method is used for driving the gate driving circuit. Referring to fig. 2 to 4, the driving method of the gate driving circuit includes:

s110, in stage T1, the first node control module transmits the voltage of the first input terminal to the first node in response to the on level of the first clock signal terminal; the first output control module transmits the voltage of the first voltage end to the output end in response to the conducting level of the first node.

For example, referring to fig. 2 and 3, the first clock signal terminal CK is at an on level, the second clock signal terminal XCK is at an off level, and the first input terminal IN1 is at an on level. The first node control module 130 transmits the turn-on level of the first input terminal IN1 to the first node N1 IN response to the turn-on level of the first clock signal terminal CK; the second node control module 140 transmits the off level of the second voltage terminal VGH to the second node N2 IN response to the on level of the first node IN 1; the third node control module 150 transmits the turn-on level of the first voltage terminal VGL to the third node N3 in response to the turn-on level of the first clock signal terminal CK. The first output control module 110 outputs the voltage of the first voltage terminal VGL from the output terminal OUT in response to the turn-on level of the first node N1.

S120, in the stage T2, the first output control module transmits the voltage of the first voltage terminal to the output terminal in response to the on level of the first node.

For example, referring to fig. 2 and 3, the first clock signal terminal CK is at an off level, the second clock signal terminal XCK is at an on level, and the first input terminal IN1 is at an on level. Since the second clock signal terminal XCK transits from the off level to the on level at the initial time of the stage T2, the voltage of the first node N1 is coupled to the on level having a lower voltage value; the second node control module 140 transmits the off level of the second voltage terminal VGH to the second node N2 IN response to the lower on level of the voltage value of the first node IN 1; the third node control module 150 transmits the off level of the first clock signal terminal CK to the third node N3. The first output control module 110 substantially outputs the voltage of the first voltage terminal VGL from the output terminal OUT IN response to the lower turn-on level of the voltage value of the first node IN 1.

S130, in the T3 stage, the output end keeps outputting the voltage output in the stage.

For example, referring to fig. 2 and 3, the first clock signal terminal CK is at an on level, the second clock signal terminal XCK is at an off level, and the first input terminal IN1 is at an off level. The first node control module 130 transmits the turn-off level of the first input terminal IN1 to the first node N1 IN response to the turn-on level of the first clock signal terminal CK; the second node control module 140 controls the second node N2 to maintain the cut-off level of the previous stage; the third node control module 150 transmits the turn-on level of the first voltage terminal VGL to the third node N3 in response to the turn-on level of the first clock signal terminal CK. The output terminal OUT maintains the voltage of the previous stage.

S140, in stage T4, the second node control module transmits the voltage of the second clock signal terminal to the second node in response to the on levels of the third node and the second clock signal terminal; the second output control module transmits the voltage of the second voltage end to the output end in response to the conducting level of the second node.

For example, referring to fig. 2 and 3, the first clock signal terminal CK is at an off level, the second clock signal terminal XCK is at an on level, and the first input terminal IN1 is at an off level. The third node control module 150 controls the third node N3 to maintain the on level of the previous stage; the first node control module 130 transmits the turn-off level of the second voltage terminal VGH to the first node N1 in response to the turn-on level of the second clock signal terminal XCK and the third node N3; the second node control module 140 transmits the turn-on level of the second clock signal terminal XCK to the second node N2 in response to the turn-on levels of the third node N3 and the second clock signal terminal XCK. The second output control module 120 transmits the voltage of the second voltage terminal VGH to the output terminal OUT in response to the turn-on level of the second node N2.

S150, in the stage T5, the second output control module transmits the voltage of the second voltage terminal VGH to the output terminal in response to the on level of the second node.

Illustratively, the first clock signal terminal CK is at an on level, the second clock signal terminal XCK is at an off level, and the first input terminal IN1 is at an off level. The first node control module 130 transmits the turn-off level of the first input terminal IN1 to the first node N1 IN response to the turn-on level of the first clock signal terminal CK; the second node control module 140 controls the second node N2 to maintain the on level of the previous stage; the third node control module 150 transmits the turn-on level of the first voltage terminal VGL to the third node N3 in response to the turn-on level of the first clock signal terminal CK. The second output control module 120 outputs the voltage of the second voltage terminal VGH from the output terminal OUT in response to the turn-on level of the second node N2.

S160, in the stage T6, the second node control module transmits the voltage of the second clock signal terminal to the second node in response to the on levels of the third node and the second clock signal terminal; the second output control module transmits the voltage of the second voltage end to the output end in response to the conducting level of the second node.

For example, referring to fig. 2 and 3, the first clock signal terminal CK is at an off level, the second clock signal terminal XCK is at an on level, and the first input terminal IN1 is at an on level. The third node control module 150 controls the third node N3 to maintain the on level of the previous stage; the first node control module 130 transmits the turn-off level of the second voltage terminal VGH to the first node N1 in response to the turn-on level of the second clock signal terminal XCK and the third node N3; the second node control module 140 transmits the turn-on level of the second clock signal terminal XCK to the second node N2 in response to the turn-on levels of the third node N3 and the second clock signal terminal XCK. The second output control module 120 transmits the voltage of the second voltage terminal VGH to the output terminal OUT in response to the turn-on level of the second node N2.

S170, in stage T7, the first node control module transmits the voltage of the first input terminal to the first node in response to the on level of the first clock signal terminal; the first output control module transmits the voltage of the first voltage terminal VGL to the output terminal in response to the turn-on level of the first node.

S180, in the stage T8, the first output control module transmits the voltage of the first voltage terminal to the output terminal in response to the on level of the first node.

For example, referring to fig. 2 and 3, the first clock signal terminal CK is at an off level, the second clock signal terminal XCK is at an on level, and the first input terminal IN1 is at an on level. Since the second clock signal terminal XCK transits from the off level to the on level at the initial time of the stage T8, the voltage of the first node N1 is coupled to the on level having a lower voltage value; the second node control module 140 transmits the off level of the second voltage terminal VGH to the second node N2 IN response to the lower on level of the voltage value of the first node IN 1; the third node control module 150 transmits the off level of the first clock signal terminal CK to the third node N3. The first output control module 110 substantially outputs the voltage of the first voltage terminal VGL from the output terminal OUT IN response to the lower turn-on level of the voltage value of the first node IN 1.

Specifically, there are various specific implementation forms of each block in the shift register 10, and a typical example is described below, but the present application is not limited thereto.

Fig. 5 is a circuit diagram of a shift register according to an embodiment of the present invention. Referring to fig. 5, optionally, the first output control module 110 includes a first transistor M1, a first terminal of the first transistor M1 is electrically connected to the first voltage terminal VGL, a second terminal of the first transistor M1 is electrically connected to the output terminal OUT, and a control terminal of the first transistor M1 is electrically connected to the first node N1; the second output control module 120 includes a second transistor M2, a first terminal of the second transistor M2 is electrically connected to the second voltage terminal VGH, a second terminal of the second transistor M2 is electrically connected to the output terminal OUT, and a control terminal of the second transistor M2 is electrically connected to the second node N2.

With continued reference to fig. 5, optionally, the first node control module 130 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a first capacitor C1; a first terminal of the third transistor M3 is electrically connected to the first input terminal IN1, a second terminal of the third transistor M3 is electrically connected to the first node N1, and a control terminal of the third transistor M3 is electrically connected to the first clock signal terminal CK; a first terminal of the fourth transistor M4 is electrically connected to the first node N1, and a control terminal of the fourth transistor M4 is electrically connected to the second clock signal terminal XCK; a first terminal of the fifth transistor M5 is electrically connected to the second voltage terminal VGH, a second terminal of the fifth transistor M5 is electrically connected to the second terminal of the fourth transistor M4, and a control terminal of the fifth transistor M5 is electrically connected to the third node N3; the first plate of the first capacitor C1 is electrically connected to the second clock signal terminal XCK, and the second plate of the first capacitor C1 is electrically connected to the first node N1.

In the T2 stage and the T8 stage, the third node N3 and the first clock signal terminal CK are both off-level, and the voltage of the first node N1 can be more stably maintained at the on-level due to the first capacitor C1.

With continued reference to fig. 5, optionally, the second node control module 140 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a second capacitor C2, and a third capacitor C3; a first terminal of the sixth transistor M6 is electrically connected to the second voltage terminal VGH, a second terminal of the sixth transistor M6 is electrically connected to the second node N2, and a control terminal of the sixth transistor M6 is electrically connected to the first node N1; a first terminal of the seventh transistor M7 is electrically connected to the second node N2, a second terminal of the seventh transistor M7 is electrically connected to the fourth node N4, and a control terminal of the seventh transistor M7 is electrically connected to the second clock signal terminal XCK; a first terminal of the eighth transistor M8 is electrically connected to the second clock signal terminal XCK, a second terminal of the eighth transistor M8 is electrically connected to the fourth node N4, and a control terminal of the eighth transistor M8 is electrically connected to the third node N3; a first plate of the second capacitor C2 is electrically connected with the fourth node N4, and a second plate of the second capacitor C2 is electrically connected with the third node N3; the first plate of the third capacitor C3 is electrically connected to the second voltage terminal VGH, and the second plate of the third capacitor C3 is electrically connected to the second node N2.

In the T4 stage and the T6 stage, the first clock signal terminal CK is at the off level, and the voltage of the third node N3 can be more stably maintained at the on level due to the second capacitor C2. At the stage T3, the first node N1 and the second clock signal terminal XCK are both off level, the voltage at the second node N2 can be more stably maintained at the off level by the action of the third capacitor C3, and at the stage T5, the first node N1 and the second clock signal terminal XCK are both off level, the voltage at the second node N2 can be more stably maintained at the on level by the action of the third capacitor C3.

With continued reference to fig. 5, optionally, the third node control module 150 includes a ninth transistor M9, a tenth transistor M10, a first switching unit, and a fourth capacitor C4; a first terminal of the ninth transistor M9 is electrically connected to the first voltage terminal VGL, a second terminal of the ninth transistor M9 is electrically connected to the third node N3, and a control terminal of the ninth transistor M9 is electrically connected to the first clock signal terminal CK; a first terminal of the tenth transistor M10 is electrically connected to the first input terminal IN1, a second terminal of the tenth transistor M10 is electrically connected to the control terminal of the first switching unit, and a control terminal of the tenth transistor M10 is electrically connected to the first clock signal terminal CK; a first terminal of the first switching unit is electrically connected to the first clock signal terminal CK, and a second terminal of the first switching unit is electrically connected to the third node N3; the first switching unit includes at least two eleventh transistors M11 connected in series; a first plate of the fourth capacitor C4 is electrically connected to the second voltage terminal VGH, and a second plate of the fourth capacitor C4 is electrically connected to the control terminal of the first switching unit.

In the T2 stage and the T8 stage, the first clock signal terminal CK is at the off level, and the voltage of the control terminal of the first switch unit can be more stably maintained at the on level due to the fourth capacitor C4. At the stages T4 and T6, the first clock signal terminal CK is at the off level, and the voltage of the control terminal of the first switching unit can be more stably maintained at the off level due to the fourth capacitor C4.

The first switching unit includes M (M is an integer equal to or greater than 2) eleventh transistors M11 connected in series. Specifically, the control terminal of each eleventh transistor M11 is electrically connected to the second plate of the fourth capacitor C4. When M is 2 (as shown in fig. 5), the first terminal of the 1 st eleventh transistor M11 is electrically connected to the third node N3, the second terminal of the 1 st eleventh transistor M11 is electrically connected to the first terminal of the 2 nd eleventh transistor M11, and the second terminal of the 2 nd eleventh transistor M11 is electrically connected to the first clock signal terminal CK. When M is greater than 2, a first terminal of the 1 st eleventh transistor M11 is electrically connected to the third node N3, a first terminal of the jth eleventh transistor M11 is electrically connected to a second terminal of the jth-1 eleventh transistor M11, a second terminal of the jth eleventh transistor M11 is electrically connected to a first terminal of the j +1 th eleventh transistor M11 (j is greater than or equal to 2 and less than or equal to M-1, and j is an integer), and a second terminal of the mth eleventh transistor M11 is electrically connected to the first clock signal terminal CK. In this way, when a voltage withstand test is performed on the display panel (the voltage of the first clock signal terminal CK is increased), the increased voltage is distributed to the eleventh transistors M11 connected in series, and since the voltage applied to the eleventh transistors M11 after the distribution is not too large, the threshold value of the eleventh transistors M11 does not generate an overvoltage drift, so that the shift register 10 and the display panel can be ensured to output normally.

The operation of the shift register 10 will be described in detail with reference to fig. 3 and 5, wherein the first voltage terminal VGL outputs a low level, the second voltage terminal VGH outputs a high level, and the first to eleventh transistors M1-M11 are all P-type transistors, and the on level is a low level and the off level is a high level.

At stage T1, the first input IN1 is low, the first clock CK is low, and the second clock XCK is high. The first transistor M1, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are turned on, and the second transistor M2, the fourth transistor M4, and the seventh transistor M7 are turned off. The low level of the first input terminal IN1 is written into the first node N1 through the turned-on third transistor M3; the high level of the second voltage terminal VGH is written into the second node N2 through the turned-on sixth transistor M6; the low level of the first clock signal terminal CK is written into the third node N3 through the turned-on eleventh transistor M11. Eventually, the low level of the first voltage terminal VGL is outputted from the output terminal OUT through the turned-on first transistor M1.

At stage T2, the first input IN1 is low, the first clock CK is high, and the second clock XCK is low. The first transistor M1, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the eleventh transistor M11 are turned on, and the second transistor M2, the third transistor M3, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are turned off. Due to the coupling effect of the first capacitor C1, the voltage at the first node N1 is pulled low to a low level with a lower voltage value; the high level of the second voltage terminal VGH is written into the second node N2 through the turned-on sixth transistor M6; the high level of the first clock signal terminal CK is written into the third node N3 through the eleventh transistor M11, eventually causing the low level of the first voltage terminal VGL to be output from the output terminal OUT through the turned-on first transistor M1.

At stage T3, the first input IN1 is high, the first clock CK is low, and the second clock XCK is high. The third transistor M3, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are turned on, and the first transistor M1, the second transistor M2, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the eleventh transistor M11 are turned off. The high level of the first input terminal IN1 is written into the first node N1 through the turned-on third transistor M3; the second node N2 maintains the high level of the previous stage; the low level of the first voltage terminal VGL is written to the third node N3 through the turned-on ninth transistor M9. The final output terminal OUT maintains the low level of the previous stage.

At stage T4, the first input IN1 is high, the first clock CK is high, and the second clock XCK is low. The second transistor M2, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, and the eighth transistor M8 are turned on, and the first transistor M1, the third transistor M3, the sixth transistor M6, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are turned off. The high level of the second voltage terminal VGH is written to the first node N1 through the turned-on fourth transistor M4 and fifth transistor M5; the low level of the second clock signal terminal XCK is written into the second node N2 through the turned-on seventh transistor M7 and the turned-on eighth transistor M8; the third node N3 maintains the low level of the previous stage. Eventually, the high level of the second voltage terminal VGH is outputted from the output terminal OUT through the turned-on second transistor M2.

At stage T5, the first input IN1 is high, the first clock CK is low, and the second clock XCK is high. The second transistor M2, the third transistor M3, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 are turned on, and the first transistor M1, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7 and the eleventh transistor M11 are turned off. The high level of the first input terminal IN1 is written into the first node N1 through the turned-on third transistor M3; the second node N2 maintains the low level of the previous stage; the low level of the first voltage terminal VGL is written to the third node N3 through the turned-on ninth transistor M9. Eventually, the high level of the second voltage terminal VGH is outputted from the output terminal OUT through the turned-on second transistor M2.

IN the period T6, the first input terminal IN1 is at a low level, the first clock signal terminal CK is at a high level, and the second clock signal terminal XCK is at a low level. The second transistor M2, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, and the eighth transistor M8 are turned on, and the first transistor M1, the third transistor M3, the sixth transistor M6, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are turned off. The high level of the second voltage terminal VGH is written to the first node N1 through the turned-on fourth transistor M4 and fifth transistor M5; the low level of the second clock signal terminal XCK is written into the second node N2 through the turned-on seventh transistor M7 and the turned-on eighth transistor M8; the third node N3 maintains the low level of the previous stage. Eventually, the high level of the second voltage terminal VGH is outputted from the output terminal OUT through the turned-on second transistor M2.

IN the period T7, the first input terminal IN1 is at a low level, the first clock signal terminal CK is at a low level, and the second clock signal terminal XCK is at a high level. The first transistor M1, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are turned on, and the second transistor M2, the fourth transistor M4, and the seventh transistor M7 are turned off. The low level of the first input terminal IN1 is written into the first node N1 through the turned-on third transistor M3; the high level of the second voltage terminal VGH is written into the second node N2 through the turned-on sixth transistor M6; the low level of the first voltage terminal VGL is written to the third node N3 through the turned-on ninth transistor M9, and simultaneously, the low level of the first clock signal terminal CK is written to the third node N3 through the turned-on eleventh transistor M11. Eventually, the low level of the first voltage terminal VGL is outputted from the output terminal OUT through the turned-on first transistor M1.

IN the period T8, the first input terminal IN1 is at a low level, the first clock signal terminal CK is at a high level, and the second clock signal terminal XCK is at a low level. The first transistor M1, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the eleventh transistor M11 are turned on, and the second transistor M2, the third transistor M3, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are turned off. Due to the coupling effect of the first capacitor C1, the voltage at the first node N1 is pulled low to a low level with a lower voltage value; the high level of the second voltage terminal VGH is written into the second node N2 through the turned-on sixth transistor M6; the high level of the first clock signal terminal CK is written into the third node N3 through the turned-on eleventh transistor M11. Eventually, the low level of the first voltage terminal VGL is outputted from the output terminal OUT through the turned-on first transistor M1.

Fig. 6 is a schematic structural diagram of another gate driving circuit according to an embodiment of the present invention. Fig. 7 is a schematic structural diagram of another shift register according to an embodiment of the present invention. Referring to fig. 6 and 7, optionally, the shift register 10 further includes a second input terminal IN2, a gate terminal XT, and a third node auxiliary control module 160, the third node auxiliary control module 160 is configured to transmit the voltage of the second clock signal terminal XCK to the second plate of the first capacitor C1 IN response to a first gate level of the gate terminal XT, and to transmit the voltage of the second input terminal IN2 to the second plate of the first capacitor C1 IN response to a second gate level of the gate terminal XT.

Specifically, the shift register shown IN fig. 6 is mainly different from the shift register shown IN fig. 2 IN that the third node auxiliary control module 160 transmits the voltage of the second input terminal IN2 to the second plate of the first capacitor C1 IN response to the second gate level of the gate terminal XT at least IN the T6 stage and the T7 stage. From the stage T6 to the stage T7, the voltage at the second input terminal IN2 has a transition from the off level to the on level. Illustratively, when the on level is low and the off level is high, the voltage at the second input terminal IN2 has a transition from high to low, so that the voltage at the first node N1 can be coupled to be lower during the T7 phase due to the first capacitor C1; when the on level is high and the off level is low, the voltage of the second input terminal IN2 has a transition from low to high, so that the voltage value of the first node N1 can be coupled higher due to the first capacitor C1 during the T7 phase. Thus, the transistors (e.g., the first transistor M1T1 in fig. 5) in the first output control module 110 can be fully turned on (fully turned on), so as to transmit the voltage of the first level voltage end to the output end OUT of the shift register 10 more fully, so that the level transmitted to the output end OUT of the shift register 10 reaches the target voltage, thereby avoiding the tailing phenomenon and improving the display effect.

Specifically, the third node assist control module 160 may be implemented in various ways, and the following description is provided with reference to a typical example, but is not intended to limit the present application.

Fig. 8 is a schematic structural diagram of another shift register according to an embodiment of the present invention. Referring to fig. 8, optionally, the third node assist control module 160 includes a twelfth transistor M12 and a thirteenth transistor M13; the twelfth transistor M12 and the thirteenth transistor M13 are both P-type transistors (as shown in fig. 8) or both N-type transistors; the gating terminal XT comprises a first gating terminal XT1 and a second gating terminal XT2, wherein the first gating terminal XT1 is used for outputting a first gating level, and the second gating terminal XT2 is used for outputting a second gating level; a first terminal of the twelfth transistor M12 is electrically connected to the second clock signal terminal XCK, a second terminal of the twelfth transistor M12 is electrically connected to the second plate of the first capacitor C1, and a control terminal of the twelfth transistor M12 is electrically connected to the first gating terminal XT 1; a first terminal of the thirteenth transistor M13 is electrically connected to the second input terminal IN2, a second terminal of the thirteenth transistor M13 is electrically connected to the second plate of the first capacitor C1, and a control terminal of the thirteenth transistor M13 is electrically connected to the second pass terminal XT 2.

Specifically, the twelfth transistor M12 is configured to transmit the voltage of the second clock signal terminal XCK to the second plate of the first capacitor C1 in response to the first gate level; the thirteenth transistor M13 is for transmitting the voltage of the second input terminal IN2 to the second plate of the first capacitor C1 IN response to the second gate level. When the twelfth transistor M12 and the thirteenth transistor M13 are both P-type transistors, the first gate level and the second gate level are both low levels; when the twelfth transistor M12 and the thirteenth transistor M13 are both N-type transistors, the first gate level and the second gate level are both high levels.

It is understood that by providing the twelfth transistor M12 and the thirteenth transistor M13 with the same type, the two transistors can be formed through the same manufacturing process, which is beneficial to reducing the number of process steps and the cost.

Fig. 9 is a schematic structural diagram of another shift register according to an embodiment of the present invention. Referring to fig. 9, optionally, the third node assist control module 160 includes a twelfth transistor M12 and a thirteenth transistor M13; one of the twelfth transistor M12 and the thirteenth transistor M13 is a P-type transistor, and the other is an N-type transistor; a first terminal of the twelfth transistor M12 is electrically connected to the second clock signal terminal XCK, a second terminal of the twelfth transistor M12 is electrically connected to the second plate of the first capacitor C1, and a control terminal of the twelfth transistor M12 is electrically connected to the gate terminal XT; a first terminal of the thirteenth transistor M13 is electrically connected to the second input terminal IN2, a second terminal of the thirteenth transistor M13 is electrically connected to the second plate of the first capacitor C1, and a control terminal of the thirteenth transistor M13 is electrically connected to the gate terminal XT.

Specifically, the twelfth transistor M12 may be a P-type transistor, and the thirteenth transistor M13 may be an N-type transistor (as shown in fig. 9), where the first gate level is low, and the second gate level is high; it is also possible to provide the twelfth transistor M12 as an N-type transistor and the thirteenth transistor M13 as a P-type transistor, in which case the first gate level is high and the second gate level is low.

It can be understood that by providing the twelfth transistor M12 and the thirteenth transistor M13 controlled by the same signal, the number of gate terminals XT and the requirement for the number of gate signals in the shift register 10 can be reduced, making the structure of the gate driving circuit simpler.

Specifically, signals of the second input terminal IN2 and the gate terminal XT may be provided by the driving chip and transmitted to the second input terminal IN2 and the gate terminal XT through signal lines correspondingly provided IN the display panel; signals of the second input terminal IN2 and the gate terminal XT can also be provided at some nodes IN the shift register 10, so that the occupation of the pin resources of the driving chip can be saved. The signals of the second input terminal IN2 and the gate terminal XT can be provided at specific nodes IN the shift register 10, and the following description is made with reference to a typical example, but does not limit the present application.

Optionally, the first gating end of the ith-stage shift register is electrically connected with the output end of the (i +1) th-stage shift register; the second gating end of the ith-stage shift register is electrically connected with the second node of the (i +1) th-stage shift register; wherein i is more than or equal to 1 and less than or equal to N-1, and i is an integer.

For example, fig. 10 is a circuit component diagram of another shift register provided in an embodiment of the present invention. Fig. 11 is a driving timing chart of the shift register shown in fig. 10. Referring to fig. 10 and 11, in the T6 stage and the T7 stage, the output terminal OUT (i +1) of the (i +1) th stage shift register 10 is at a high level, the twelfth transistor M12 is turned off, the second node N2(i +1) of the (i +1) th stage shift register 10 is at a low level, and the thirteenth transistor M13 is turned on. In the stage T6, the high level of the fourth node N4(i +3) of the shift register 10 of the i +3 th stage is transmitted to the second plate of the first capacitor C1, and in the stage T7, the low level of the fourth node N4(i +3) of the shift register 10 of the i +3 th stage is transmitted to the second plate of the first capacitor C1, and due to the effect of the first capacitor C1, in the stage T7, the voltage value of the first node N1 is coupled to be lower, so that the first transistor M1 can be fully turned on (fully turned on state), and the voltage of the first level voltage end is more fully transmitted to the output OUT of the shift register 10, thereby avoiding the tailing phenomenon.

For example, fig. 12 is a circuit element diagram of another shift register provided in an embodiment of the present invention. Fig. 13 is a driving timing chart of the shift register shown in fig. 12. Referring to fig. 12 and 13, in the stage of T6, the high level of the second node N2(i +3) of the shift register 10 of the i +3 th stage is transmitted to the second plate of the first capacitor C1 through the turned-on thirteenth transistor M13, in the stage of T7, the low level of the second node N2(i +3) of the shift register 10 of the i +3 th stage is transmitted to the second plate of the first capacitor C1 through the turned-on thirteenth transistor M13, and in the stage of T7, the voltage value of the first node N1 is coupled to be lower due to the first capacitor C1, so that the first transistor M1 can be sufficiently turned on (fully turned-on state), and the voltage of the first level voltage terminal is more sufficiently transmitted to the output terminal OUT of the shift register 10, thereby preventing the tailing phenomenon from being generated.

For example, fig. 14 is a circuit component diagram of another shift register provided in an embodiment of the present invention. Fig. 15 is a driving timing chart of the shift register shown in fig. 14. Referring to fig. 14 and 15, during the period T6, the high level of the first clock signal terminal CK is transmitted to the second plate of the first capacitor C1 through the conducting thirteenth transistor M13, and during the period T7, the low level of the first clock signal terminal CK is transmitted to the second plate of the first capacitor C1 through the conducting thirteenth transistor M13, and due to the effect of the first capacitor C1, during the period T7, the voltage value of the first node N1 is coupled to be lower, so that the first transistor M1 can be fully turned on (fully turned on state), the voltage of the first level voltage terminal is more fully transmitted to the output terminal OUT of the shift register 10, and the tailing phenomenon is avoided.

Optionally, the first gating end of the ith-stage shift register is electrically connected to the first node of the (i +1) th-stage shift register; the second gating end of the ith-stage shift register is electrically connected with the second node of the (i +1) th-stage shift register; wherein i is more than or equal to 1 and less than or equal to N-1, and i is an integer.

For example, fig. 16 is a circuit component diagram of a shift register according to an embodiment of the present invention. Fig. 17 is a driving timing chart of the shift register shown in fig. 16. Referring to fig. 16 and 17, in the T6 stage and the T7 stage, the first node N1(i +1) of the i +1 th stage shift register 10 is at a high level, the twelfth transistor M12 is turned off, the second node N2(i +1) of the i +1 th stage shift register 10 is at a low level, and the thirteenth transistor M13 is turned on. In the stage T6, the high level of the fourth node N4(i +3) of the shift register 10 of the i +3 th stage is transmitted to the second plate of the first capacitor C1, and in the stage T7, the low level of the fourth node N4(i +3) of the shift register 10 of the i +3 th stage is transmitted to the second plate of the first capacitor C1, and due to the effect of the first capacitor C1, in the stage T7, the voltage value of the first node N1 is coupled to be lower, so that the first transistor M1 can be fully turned on (fully turned on state), and the voltage of the first level voltage end is more fully transmitted to the output OUT of the shift register 10, thereby avoiding the tailing phenomenon.

Note that, the first gate terminal of the ith stage shift register 10 is electrically connected to the first node N1(i +1) of the (i +1) th stage shift register 10; when the second gating end of the i-th stage shift register 10 is electrically connected to the second node N2(i +1) of the i + 1-th stage shift register 10, the second input end of the i-th stage shift register 10 may also be electrically connected to the second node N2(i +3) of the i + 3-th stage shift register 10, which avoids the tailing phenomenon, the principle is similar to that of the shift register 10 shown in fig. 12, and is not repeated here; alternatively, the second input terminal of the i-th stage shift register 10 may also be electrically connected to the first clock signal terminal CK, and the principle of avoiding the tailing phenomenon is similar to that of the shift register 10 shown in fig. 14, and is not described herein again.

Optionally, the gating end of the ith-stage shift register is electrically connected to the first node of the (i +1) th-stage shift register; or, the gating end of the ith-stage shift register 10 is electrically connected with the second node of the (i +1) th-stage shift register; or, the gating end of the ith-stage shift register 10 is electrically connected with the output end of the (i +1) th-stage shift register; wherein i is more than or equal to 1 and less than or equal to N-1, and i is an integer.

For example, fig. 18 is a circuit element diagram of another shift register provided in an embodiment of the present invention. In the T6 stage and the T7 stage, the output terminal OUT (i +1) of the i +1 th stage shift register 10 is at a high level, the twelfth transistor M12 is turned off, the thirteenth transistor M13 is turned on, and the voltage of the fourth node N4(i +3) of the i +3 th stage shift register 10 is transmitted to the first plate of the first capacitor C1.

For example, fig. 19 is a circuit element diagram of another shift register provided in an embodiment of the present invention. In the T6 stage and the T7 stage, the voltage of the second node N2(i +1) of the i +1 th stage shift register 10 is at a high level, the twelfth transistor M12 is turned off, the thirteenth transistor M13 is turned on, and the voltage of the fourth node N4(i +3) of the i +3 th stage shift register 10 is transmitted to the first plate of the first capacitor C1.

For example, fig. 20 is a circuit component diagram of another shift register provided in an embodiment of the present invention. In the T6 stage and the T7 stage, the voltage of the first node N1(i +1) of the i +1 th stage shift register 10 is at a high level, the twelfth transistor M12 is turned off, the thirteenth transistor M13 is turned on, and the voltage of the fourth node N4(i +3) of the i +3 th stage shift register 10 is transmitted to the first plate of the first capacitor C1.

For the shift register 10 shown in fig. 18-20, during the period T6, the high level of the fourth node N4(i +3) of the shift register 10 of the i +3 th stage is transmitted to the second plate of the first capacitor C1, during the period T7, the low level of the fourth node N4(i +3) of the shift register 10 of the i +3 th stage is transmitted to the second plate of the first capacitor C1, and due to the effect of the first capacitor C1, during the period T7, the voltage value of the first node N1 is coupled to be lower, so that the first transistor M1 can be fully turned on (fully turned on state), the voltage of the first level voltage end is more fully transmitted to the output end OUT of the shift register 10, and the tailing phenomenon is avoided.

It should be noted that, when the gate terminal of the i-th stage shift register 10 is electrically connected to the first node N1(i +1) of the i + 1-th stage shift register 10, and the gate terminal of the i-th stage shift register 10 is electrically connected to the second node N2(i +1) of the i + 1-th stage shift register 10, or the gate terminal of the i-th stage shift register 10 is electrically connected to the output terminal OUT (i +1) of the i + 1-th stage shift register 10, the second input terminal of the i-th stage shift register 10 may be further configured to be electrically connected to the second node N2(i +3) of the i + 3-th stage shift register 10, and the principle of avoiding the tailing phenomenon may refer to the original text, which is not described herein again; the second input terminal of the i-th stage shift register 10 may also be electrically connected to the first clock signal terminal CK, and the principle of avoiding the tailing phenomenon can be referred to as the original text, which is not repeated herein.

Optionally, a second input end of the ith-stage shift register is electrically connected to a second node of the (i +3) th-stage shift register; wherein i is more than or equal to 1 and less than or equal to N-3, i is an integer, and N is an integer more than 4, as shown in FIG. 12.

Optionally, the second input end of the ith-stage shift register is electrically connected to the fourth node of the (i +3) th-stage shift register; i is not less than 1 and not more than N-3, i is an integer, and N is an integer greater than 4, as shown in FIGS. 10 and 16.

Alternatively, the first clock signal terminal is electrically connected to the second input terminal, as shown in fig. 14.

In addition, in the transistors in the present application, a P-type transistor is taken as an example, and when the control terminal of the P-type transistor is at a low level, the first terminal and the second terminal of the P-type transistor are turned on, and when the control terminal of the P-type transistor is at a high level, the first terminal and the second terminal of the P-type transistor are turned off, but the present invention is not limited thereto. In addition, in the implementation, the gate of each transistor is used as the control terminal, and the first terminal of each transistor may be used as the source and the second terminal may be used as the drain, or the first terminal may be used as the drain and the second terminal may be used as the source, depending on the signal of the gate of each transistor and the type of the gate, which is not distinguished herein.

It should be noted that, in the embodiments of the present invention, both the on level and the off level are generally referred to, the on level refers to any level capable of turning on the transistor, and the off level refers to any level capable of turning off the transistor.

Based on the above inventive concept, an embodiment of the present invention further provides a display panel, which includes the gate driving circuit described in any of the above embodiments. Therefore, the display panel has the advantages of the gate driving circuit provided by the embodiment of the invention, and the same points can be understood by referring to the above description, which is not repeated herein.

Based on the above inventive concept, embodiments of the present invention further provide a display device, which includes the display panel described in any of the above embodiments. Therefore, the display device has the advantages of the display panel provided by the embodiment of the invention, and the same points can be understood by referring to the above description, which is not repeated herein.

For example, fig. 21 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 21, a display device 200 according to an embodiment of the present invention includes the display panel 100 according to an embodiment of the present invention. The display device 200 may be exemplified by any electronic device with a display function, such as a touch display screen, a mobile phone, a tablet computer, a notebook computer, or a television.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A gate drive circuit, comprising: n stages of cascaded shift registers, wherein N is an integer greater than or equal to 2;

2. A gate drive circuit as claimed in claim 1,

the first output control module comprises a first transistor, a first end of the first transistor is electrically connected with the first voltage end, a second end of the first transistor is electrically connected with the output end, and a control end of the first transistor is electrically connected with the first node;

the second output control module comprises a second transistor, a first end of the second transistor is electrically connected with the second voltage end, a second end of the second transistor is electrically connected with the output end, and a control end of the second transistor is electrically connected with the second node.

3. A gate drive circuit as claimed in claim 1,

the first node control module comprises a third transistor, a fourth transistor, a fifth transistor and a first capacitor;

a first end of the third transistor is electrically connected to the first input end, a second end of the third transistor is electrically connected to the first node, and a control end of the third transistor is electrically connected to the first clock signal end;

a first end of the fourth transistor is electrically connected with the first node, and a control end of the fourth transistor is electrically connected with the second clock signal end;

a first end of the fifth transistor is electrically connected with the second voltage end, a second end of the fifth transistor is electrically connected with a second end of the fourth transistor, and a control end of the fifth transistor is electrically connected with the third node;

the first electrode plate of the first capacitor is electrically connected with the second clock signal end, and the second electrode plate of the first capacitor is electrically connected with the first node.

4. A gate drive circuit as claimed in claim 3,

the second node control module comprises a sixth transistor, a seventh transistor, an eighth transistor, a second capacitor and a third capacitor;

a first end of the sixth transistor is electrically connected with the second voltage end, a second end of the sixth transistor is electrically connected with the second node, and a control end of the sixth transistor is electrically connected with the first node;

a first end of the seventh transistor is electrically connected with the second node, a second end of the seventh transistor is electrically connected with the fourth node, and a control end of the seventh transistor is electrically connected with the second clock signal end;

a first end of the eighth transistor is electrically connected with the second clock signal end, a second end of the eighth transistor is electrically connected with the fourth node, and a control end of the eighth transistor is electrically connected with the third node;

the first pole plate of the second capacitor is electrically connected with the fourth node, and the second pole plate of the second capacitor is electrically connected with the third node;

the first electrode plate of the third capacitor is electrically connected with the second voltage end, and the second electrode plate of the third capacitor is electrically connected with the second node.

5. A gate drive circuit as claimed in claim 1,

the third node control module comprises a ninth transistor, a tenth transistor, a first switch unit and a fourth capacitor;

a first end of the ninth transistor is electrically connected with the first voltage end, a second end of the ninth transistor is electrically connected with the third node, and a control end of the ninth transistor is electrically connected with the first clock signal end;

a first end of the tenth transistor is electrically connected to the first input end, a second end of the tenth transistor is electrically connected to the control end of the first switching unit, and the control end of the tenth transistor is electrically connected to the first clock signal end;

the first end of the first switch unit is electrically connected with the first clock signal end, and the second end of the first switch unit is electrically connected with the third node; the first switching unit comprises at least two eleventh transistors connected in series;

and the first pole plate of the fourth capacitor is electrically connected with the second voltage end, and the second pole plate of the fourth capacitor is electrically connected with the control end of the first switch unit.

6. The gate driving circuit of claim 4, wherein the shift register further comprises a second input terminal, a pass terminal, and a first node auxiliary control module,

the first node auxiliary control module is used for responding to a first gating level of the gating end, transmitting the voltage of the second clock signal end to the second plate of the first capacitor, and responding to a second gating level of the gating end, transmitting the voltage of the second input end to the second plate of the first capacitor.

7. The gate driving circuit of claim 6, wherein the first node auxiliary control module comprises a twelfth transistor and a thirteenth transistor; the twelfth transistor and the thirteenth transistor are both P-type transistors or both N-type transistors; the gating end comprises a first gating end and a second gating end, the first gating end is used for outputting the first gating level, and the second gating end is used for outputting the second gating level;

a first end of the twelfth transistor is electrically connected with the second clock signal end, a second end of the twelfth transistor is electrically connected with the second plate of the first capacitor, and a control end of the twelfth transistor is electrically connected with the first gating end;

a first end of the thirteenth transistor is electrically connected to the second input end, a second end of the thirteenth transistor is electrically connected to the second plate of the first capacitor, and a control end of the thirteenth transistor is electrically connected to the second gating end.

8. The gate driving circuit according to claim 7, wherein the first pass terminal of the i-th stage shift register is electrically connected to the first node of the i + 1-th stage shift register;

the second gating end of the ith-stage shift register is electrically connected with the second node of the (i +1) th-stage shift register; wherein i is more than or equal to 1 and less than or equal to N-1, and i is an integer.

9. The gate driving circuit according to claim 7, wherein the first pass terminal of the i-th stage shift register is electrically connected to the output terminal of the i + 1-th stage shift register;

10. The gate driving circuit of claim 6, wherein the first node auxiliary control module comprises a twelfth transistor and a thirteenth transistor; one of the twelfth transistor and the thirteenth transistor is a P-type transistor, and the other is an N-type transistor;

a first end of the twelfth transistor is electrically connected with the second clock signal end, a second end of the twelfth transistor is electrically connected with the second plate of the first capacitor, and a control end of the twelfth transistor is electrically connected with the gating end;

a first end of the thirteenth transistor is electrically connected to the second input end, a second end of the thirteenth transistor is electrically connected to the second plate of the first capacitor, and a control end of the thirteenth transistor is electrically connected to the gate end.

11. The gate driving circuit according to claim 10, wherein the pass terminal of the ith stage shift register is electrically connected to the first node of the (i +1) th stage shift register;

or the gating end of the ith-stage shift register is electrically connected with the second node of the (i +1) th-stage shift register;

or the gating end of the ith-stage shift register is electrically connected with the output end of the (i +1) th-stage shift register; wherein i is more than or equal to 1 and less than or equal to N-1, and i is an integer.

12. The gate driving circuit according to claim 6, wherein the second input terminal of the i-th stage shift register is electrically connected to the second node of the i + 3-th stage shift register; wherein i is more than or equal to 1 and less than or equal to N-3, i is an integer, and N is an integer more than 4.

13. A gate drive circuit as claimed in claim 6,

the second input end of the ith-stage shift register is electrically connected with the fourth node of the (i +3) th-stage shift register; i is more than or equal to 1 and less than or equal to N-3, i is an integer, and N is an integer more than 4.

14. A gate drive circuit as claimed in claim 6, wherein the first clock signal terminal is electrically connected to the second input terminal.

15. A display panel comprising the gate driver circuit according to any one of claims 1 to 14.

16. A display device characterized by comprising the display panel according to claim 15.

17. A driving method of a gate driving circuit, which is applied to the gate driving circuit of claim 1, the method comprising: