CN112134262A

CN112134262A - Protection circuit and circuit protection method for power device

Info

Publication number: CN112134262A
Application number: CN202011040226.6A
Authority: CN
Inventors: 张俊杰; 刘学; 刘超
Original assignee: Jiangsu Leili Motor Co Ltd
Current assignee: Changzhou Liheng Electrical Appliance Co ltd
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2020-12-25
Anticipated expiration: 2040-09-28
Also published as: CN112134262B

Abstract

The present invention relates to a protection circuit for a power device and a circuit protection method, the protection circuit including: the device comprises a voltage input end, a comparison circuit, a self-locking circuit, an unlocking signal source and a power device control circuit; when the input voltage is greater than the preset voltage, the comparison circuit outputs a first level, the self-locking circuit is triggered to be in a self-locking state, and the power device control circuit outputs a closing signal to close the power device; when the input voltage is less than or equal to the preset voltage, the comparison circuit outputs a second level, and the self-locking circuit is not triggered; when the unlocking signal source receives an unlocking signal of the unlocking signal source, the self-locking circuit is triggered to release the self-locking state of the self-locking circuit, and the power device control circuit outputs a starting signal to start the power device.

Description

Protection circuit and circuit protection method for power device

Technical Field

The present invention relates to a protection circuit for a power device and a circuit protection method.

Background

Power devices (e.g., power semiconductor devices) have been widely used in the field of power electronic control, and the controllability and high-speed switching characteristics of the power devices can achieve high efficiency of power supply and complex control of motors. In practical applications, it is required to ensure not only the reliability of the system, but also to protect the expensive power device and its load, which requires some protection measures for the control system, wherein the design requirements for the protection circuit are very high due to the short generation time, high energy and high destructiveness of the overcurrent fault.

Therefore, a protection circuit for a power device, which has a fast response speed and is cost-effective, needs to be designed.

Disclosure of Invention

The present invention addresses the above-mentioned problems and needs, and provides a protection circuit for a power device and a circuit protection method, which are capable of solving the above-mentioned problems and having other technical advantages due to the following technical solutions.

According to an aspect of the present invention, there is provided a protection circuit for a power device, including: the circuit comprises a voltage input end, a comparison circuit, a self-locking circuit, an unlocking signal source and a power device control circuit. A voltage input terminal configured to input an input voltage related to a load voltage to the protection circuit; the comparison voltage input end is configured to input a preset voltage to the protection circuit; the power device control circuit is electrically connected with a peripheral power device to control the power device to be turned on and turned off; the first input end of the comparison circuit is electrically connected with the voltage input end, the second input end of the comparison circuit is electrically connected with the comparison voltage input end, and the output end of the comparison circuit is electrically connected with the self-locking circuit; the unlocking signal source is electrically connected with the self-locking circuit, and the power device control circuit is electrically connected with the self-locking circuit.

When the input voltage is greater than the preset voltage, the comparison circuit outputs a first level, the self-locking circuit is triggered to be in a self-locking state, and the power device control circuit outputs a closing signal to close the power device; when the input voltage is less than or equal to the preset voltage, the comparison circuit outputs a second level, and the self-locking circuit is not triggered. When the unlocking signal source receives an unlocking signal of the unlocking signal source, the self-locking circuit is triggered to release the self-locking state of the self-locking circuit, and the power device control circuit outputs a starting signal to start the power device.

Through the characteristics, the protection circuit provided by the invention adopts a pure hardware circuit to realize the locking of the overcurrent state after overcurrent, and triggers the power device control circuit to protect the power device, so that the power device can be effectively protected from being damaged by the overcurrent. In addition, after overcurrent faults occur, the circuit turns off the power device within self-locking time due to the self-locking function until an unlocking signal is given, the power device cannot be turned on and off for many times when faults occur, and the power device is protected.

In some examples, the protection circuit further includes a controller including a first control port, the first control port being the unlock signal source.

In some examples, the controller further comprises a second control port electrically connected to the comparison circuit, the second control port is configured to receive a first level of the comparison circuit to trigger a brake pin in the controller, the controller counts and starts timing at the same time, and after a preset time, the first control port of the controller sends out an unlocking signal to enable the comparison circuit to output a second level.

Through the characteristics, the controller is used as an unlocking signal source, and the controller can be used for carrying out fault recovery on the overcurrent frequency judgment under the conditions of some conduction or some electromagnetic interference and the like when unreal overcurrent is generated, so that the system can work normally again.

In some examples, after the first control port of the receiving controller sends out the unlock signal, the comparison circuit continues to compare the input voltage with the preset voltage, when the input voltage is still greater than the preset voltage, the self-locking circuit is triggered again, and the brake pin of the controller triggers the count again, and the count is increased by one, and when the count of the controller is greater than the preset count, the controller stops outputting the unlock signal and indicates that the circuit is out of order.

Through the characteristics, when the circuit is in fault and overcurrent is caused, the controller can be used for judging the overcurrent frequency to carry out fault judgment, and if the fault exists all the time and is not eliminated, the circuit is indicated to be in fault in time, and a power device is protected.

In some examples, the comparison circuit includes a comparator U2 and a resistor R9, the resistor R9 having one end electrically connected to the output of the comparator U2 and another end electrically connected to a positive input of the comparator U2, a comparison voltage input electrically connected to a positive input of the comparator U2, a voltage input electrically connected to a negative input of the comparator U2, and a second control port electrically connected to the output of the comparator U2.

In some examples, the self-locking circuit includes a transistor Q1, a base of a transistor Q1 is electrically connected to an output of the comparator U2, an emitter of the transistor Q1 is electrically connected to a dc voltage source, and a collector of the transistor Q1 is electrically connected to the power device control circuit.

In some examples, the protection circuit further includes a transistor Q2 and a diode D1, a base of the transistor Q2 is electrically connected to the first control port, an emitter of the transistor Q2 is electrically connected to a collector of the transistor Q1, a collector of the transistor Q2 is electrically connected to an anode of the diode D1, and a cathode of the diode D1 is electrically connected to a negative input of the comparator U2.

In some examples, the self-locking circuit includes a transistor Q1 and a diode D1, a base of the transistor Q1 is electrically connected to an output of the comparator U2, an emitter of the transistor Q1 is electrically connected to the first control port, a collector of the transistor Q1 is electrically connected to the power device control circuit and to an anode of the diode D1, and a cathode of the diode D1 is electrically connected to a negative input of the comparator U2.

In some examples, the latch circuit includes a transistor Q1 and a diode D1, the voltage inputs include an input voltage source and a resistor R6, a base of the transistor Q1 is electrically connected to an output of the comparator U2, an emitter of the transistor Q1 is electrically connected to a dc voltage source, a collector of the transistor Q1 is electrically connected to the power device control circuit and a positive terminal of the diode D1, one end of the resistor R6 is electrically connected to the input voltage source and a negative terminal of the diode D1, the other end of the resistor R6 is electrically connected to a negative input of the comparator U2, and the first control port is electrically connected to the negative input of the comparator U2.

In some examples, the transistor Q1 is a PNP transistor, the first level is low, and the second level is high.

In some examples, the protection circuit further comprises a level conversion circuit having an input end and an output end, the level conversion circuit is configured to invert the level of the input end and output the inverted level at the output end, the input end is electrically connected with the output end of the comparison circuit, wherein the controller further comprises a second control port electrically connected to the output end of the level conversion circuit, the second control port is configured to receive the inverted level to trigger a brake pin in the controller, the controller counts and starts timing at the same time, and after a preset time, the first control port of the controller sends out an unlocking signal to enable the comparison circuit to output the second level.

In some examples, the comparison circuit includes a comparator U2 having a comparison voltage input electrically connected to a negative input of the comparator U2 and a voltage input electrically connected to a positive input of the comparator U2, and wherein the self-locking circuit includes a diode D2, a positive pole of the diode D2 electrically connected to the output of the comparator U2, and a negative pole of the diode D2 electrically connected to the voltage input and the positive input of the comparator U2.

In some examples, the level shift circuit includes a transistor Q1, a resistor R9, a resistor R13, and a resistor R14, one end of the resistor R13 is electrically connected to the output terminal of the comparator U2, the other end of the resistor R13 is electrically connected to one end of the resistor R14 and the base of the transistor Q1, the emitter of the transistor Q1 is electrically connected to the other end of the resistor R14 and the ground, the collector of the transistor Q1 is electrically connected to one end of the resistor R9, the other end of the resistor R9 is electrically connected to a dc voltage source, the first control port is electrically connected to the positive input terminal of the comparator U2, and the second control port is electrically connected to the collector of the transistor Q1.

In some examples, the transistor Q1 is an NPN transistor, the first level is high, and the second level is low.

In some examples, the comparison voltage input terminal includes a dc voltage source and a voltage divider circuit, the voltage divider circuit includes a resistor R7, a resistor R8, and a capacitor C6, the dc voltage source is electrically connected to one end of the resistor R7, the other end of the resistor R7 is electrically connected to ground through a resistor R8, a resistor R8 is connected in parallel to the capacitor C6, and the other end of the resistor R7 is electrically connected to a second input terminal of the comparison circuit.

In some examples, the power device control circuit comprises a field effect transistor, a resistor R11 and a resistor R12, one end of the resistor R11 is electrically connected with the self-locking circuit, the other end of the resistor R11 is electrically connected with the grid electrode of the field effect transistor, the source electrode of the field effect transistor is electrically connected with the ground wire, and the drain electrode of the field effect transistor is electrically connected with the power device.

In some examples, the field effect transistor is a MOS field effect transistor.

In some examples, the power device control circuit includes the controller, the controller includes a third control port electrically connected with a power device, and the third control port is configured to output a level signal to turn off the power device when the brake pin is triggered.

In some examples, the protection circuit further includes a sampling circuit configured to sample a current signal of the load and convert to a voltage signal.

In some examples, the protection circuit further includes an amplification circuit configured to amplify and output the voltage signal of the sampling circuit to a voltage input terminal.

According to another aspect of the present invention, a circuit protection method is provided, the circuit including a voltage input terminal, a comparison circuit, a self-locking circuit, an unlocking signal source, and a power device control circuit, the method including comparing a preset voltage of the comparison voltage input terminal with an input voltage of the voltage input terminal, when the input voltage is greater than the preset voltage, the comparison circuit outputting a first level, the self-locking circuit being triggered in a self-locking state, the power device control circuit outputting a turn-off signal to turn off a power device; when the input voltage is less than or equal to the preset voltage, the comparison circuit outputs a second level, and the self-locking circuit is not triggered. When the unlocking signal source receives an unlocking signal of the unlocking signal source, the self-locking circuit is triggered to release the self-locking state of the self-locking circuit, and the power device control circuit outputs a starting signal to start the power device.

In some examples, the method further comprises issuing the unlock signal as an unlock signal source through a first control port of a controller.

In some examples, the controller further comprises a second control port electrically connected to the comparison circuit, the second control port receives the first level of the comparison circuit to trigger a brake pin in the controller, the controller counts and starts timing at the same time, and after a preset time, the first control port of the controller sends out an unlocking signal to enable the comparison circuit to output the second level.

In summary, the protection circuit and the circuit protection method for the power device provided by the invention adopt a pure hardware circuit to lock the overcurrent state after overcurrent is realized, and trigger the power device control circuit to protect the power device, so that the power device can be effectively protected from being damaged by the overcurrent. In addition, after overcurrent faults occur, the circuit turns off the power device within self-locking time due to the self-locking function until an unlocking signal is given, and the power device cannot be turned on and off for many times when faults occur, so that the power device is protected. The protection circuit has high response speed and cost effectiveness.

The following description of the preferred embodiments for carrying out the present invention will be made in detail with reference to the accompanying drawings so that the features and advantages of the present invention can be easily understood.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments of the present invention will be briefly described below. Wherein the drawings are only for purposes of illustrating some embodiments of the invention and are not to be construed as limiting the invention to all embodiments thereof.

FIG. 1 is a block diagram of a protection circuit in accordance with at least one embodiment of the present invention;

FIG. 2 is a block diagram of a protection circuit according to yet another embodiment of the present invention;

fig. 3 is a schematic structural diagram of a first embodiment of a protection circuit according to the present invention;

fig. 4 is a schematic structural diagram of a second embodiment of a protection circuit according to the present invention;

fig. 5 is a schematic structural diagram of a third embodiment of a protection circuit according to the present invention;

fig. 6 is a schematic structural diagram of a fourth embodiment of a protection circuit according to the present invention;

fig. 7 is a flow diagram of a circuit protection method in accordance with at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of specific embodiments of the present invention. Like reference symbols in the various drawings indicate like elements. It should be noted that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the description and claims of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not necessarily denote a limitation of quantity. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The current protection circuit needs to sample the current of the load in the circuit and output the current to the comparison circuit. The sampling of current in the circuit is generally divided into indirect sampling or direct sampling, and the indirect sampling generally uses a special current sensor, although the precision is high and the anti-interference capability is strong, the price is expensive.

Therefore, a common method is to directly sample and serially connect a resistor in a current loop to convert a current signal into a voltage signal. And amplifying the converted voltage signal through a differential amplification circuit, sending the amplified voltage signal to a comparator for comparison, and judging whether an overcurrent fault occurs.

Since most power semiconductor devices have overcurrent endurance capacity of only a few microseconds, the comparator post-stage execution circuit must be able to turn off the power device within a few microseconds to protect the power device and the load. If the output of the comparator triggers the interruption of the MCU, the software executes the action of closing the power device, the time from the response of the MCU to the execution of the output is longer than the time that the power device can bear the overcurrent, and the software is not ready to process and the power device is damaged.

The execution circuit is usually implemented by a hardware circuit in order to satisfy the requirement of fast response. Although the hardware circuit has high response speed, when overcurrent occurs, the power device is closed, the current is reduced, and when the overcurrent is lower than the comparison threshold of the overcurrent protection, the output of the comparator is reset, and the power device is opened again. At this point, if the over-current fault still exists, the comparator output will flip into the over-current state again. In such a reciprocating manner, the power device and the load will continuously bear the overcurrent impact, and the probability of damage is also high.

The conventional method is to connect a monostable trigger (a monostable trigger built by a single chip or discrete devices) to the output end of the comparator, to make the monostable trigger output a level signal for a long time by using a jumping edge output by the comparator, to turn off the power device by a post-stage circuit, and to detect an overcurrent state by software and to continuously turn off the power device after the monostable is finished. Monostable triggers, however, are expensive and are not suitable for use in cost sensitive items.

In view of the above problems and needs, a protection circuit for a power device and a circuit protection method of the present disclosure are proposed.

Preferred embodiments of a protection circuit for a power device according to the present disclosure are described below in detail with reference to the accompanying drawings. Fig. 1 is a block diagram of a protection circuit according to at least one embodiment of the invention. Fig. 2 is a block diagram of a protection circuit according to yet another embodiment of the present invention. Fig. 3 is a schematic structural diagram of a protection circuit according to a first embodiment of the present invention. Fig. 4 is a schematic structural diagram of a protection circuit according to a second embodiment of the present invention. Fig. 5 is a schematic structural diagram of a protection circuit according to a third embodiment of the present invention. Fig. 6 is a schematic structural diagram of a protection circuit according to a fourth embodiment of the present invention.

First, referring to fig. 1, a protection circuit provided in at least one embodiment of the present disclosure includes a voltage input terminal 1, a comparison voltage input terminal 2, a comparison circuit 3, a self-locking circuit 4, an unlocking signal source 5, and a power device control circuit 6.

The voltage input terminal 1 is configured to input an input voltage related to a load voltage to the protection circuit, for example, the voltage input terminal 1 is electrically connected to a first input terminal of the comparison circuit 3.

The comparison voltage input terminal 2 is configured to input a preset voltage to the protection circuit. For example, the comparison voltage input terminal 2 is electrically connected to a second input terminal of the comparison circuit 3.

An example of a comparison circuit includes a comparator having a positive input and a negative input, and an output of the comparator. In the description herein, the first input terminal may refer to one of a positive input terminal and a negative input terminal, and accordingly, the second input terminal may refer to the other of the positive input terminal and the negative input terminal. The selection of the positive input terminal and the negative input terminal can be selected according to the actual circuit structure, and the disclosure is not limited thereto.

It should be noted that the "first level" and the "second level" described herein refer to one of a high level and a low level, respectively. In the present invention, the main function of the comparison circuit is to compare the preset voltage with the input voltage, so as to generate the level-reversal signal. For example, in normal operation, the input voltage is equal to or less than the preset voltage, the comparison circuit outputs the second level, and when the overcurrent fault occurs, the input voltage is increased to be greater than the preset voltage, and the level of the output end of the comparison circuit is inverted and changed from the second level to the first level.

The power device control circuit 6 is electrically connected with the peripheral power devices to control the power devices to be turned on and off. For example, the power devices may form a bridge inverter circuit, and the switching states of the upper and lower bridges are determined by the voltage signals applied to the control electrodes. Therefore, the power device control circuit 6 can be connected to the control electrodes of the upper and lower bridges of the bridge inverter circuit to control the on and off of the power devices.

The self-locking circuit 4 is electrically connected with the output end of the comparison circuit 3 to receive the comparison result of the comparison circuit 3 to perform circuit self-locking. The unlocking signal source 5 is electrically connected with the self-locking circuit 3, and the power device control circuit 6 is electrically connected with the self-locking circuit.

When the input voltage is greater than the preset voltage, the comparison circuit outputs a first level, the self-locking circuit is triggered to be in a self-locking state, and the power device control circuit outputs a closing signal to close the power device; when the input voltage is less than or equal to the preset voltage, the comparison circuit outputs a second level, and the self-locking circuit is not triggered.

When the unlocking signal source receives an unlocking signal of the unlocking signal source, the self-locking circuit is triggered to release the self-locking state of the self-locking circuit, and the power device control circuit outputs a starting signal to start the power device.

According to a further embodiment of the present disclosure, the protection circuit may further comprise a controller 7, the controller 7 comprising a first control port 71 and a second control port 72. The first control port 71 is the unlock signal source 5 as previously described. The second control port 72 is electrically connected to the comparison circuit 3.

The second control port 72 is configured to receive the first level of the comparison circuit 3 to trigger a brake pin in the controller 7, the controller 7 counts and starts timing at the same time, and after a preset time, the first control port 71 of the controller 7 sends out an unlocking signal, so that the comparison circuit 3 outputs the second level.

Further, after receiving the unlocking signal sent by the first control port 71 of the controller 7, the comparison circuit 3 continues to compare the input voltage with the preset voltage, when the input voltage is still greater than the preset voltage, the self-locking circuit is triggered again, the braking pin of the controller triggers the counting again, the counting is increased by one, and when the counting of the controller 7 is greater than the preset counting, the controller 7 stops outputting the unlocking signal and indicates that the circuit is out of order.

Therefore, the controller is adopted as an unlocking signal source, and the protection circuit can distinguish whether the overcurrent state really occurs or not, so that the protection circuit has robustness. Under the conditions of some conduction or some electromagnetic interference and the like, the produced unreal overcurrent can be judged by the controller to carry out fault recovery, and the system can work normally again. When the circuit is in fault and overcurrent is caused, the controller can be used for judging the overcurrent times to judge the fault, and if the fault is not eliminated all the time, the circuit is indicated to be in fault in time to protect the power device.

The Controller may be, for example, a Micro Controller Unit (MCU), a single chip, a Field Programmable Gate Array (FPGA), a digital signal processor, or the like, which has data receiving and processing capabilities and is common in the art. In the embodiment shown herein, the controller employs an MCU.

In addition, the protection circuit of the embodiment of the invention may further include other necessary peripheral circuits. For example, the comparison voltage input end comprises a direct current voltage source and a voltage division circuit, the voltage division circuit comprises a resistor R7, a resistor R8 and a capacitor C6, the direct current voltage source is electrically connected with one end of the resistor R7, the other end of the resistor R7 is electrically connected with the ground through a resistor R8, a resistor R8 is connected with the capacitor C6 in parallel, and the other end of the resistor R7 is electrically connected with the second input end of the comparison circuit. The divided voltage at the resistor R8 is used as the preset voltage.

For example, as shown in fig. 2, the protection circuit may further include a sampling circuit 8 and an amplifying circuit 9, which are cascaded, the sampling circuit 8 is configured to sample a current signal of a load and convert the current signal into a voltage signal, and the amplifying circuit 9 is configured to amplify and output the voltage signal of the sampling circuit 8 to the voltage input terminal 1.

Four exemplary embodiments of the protection circuit of the present invention will be described below with reference to fig. 3 to 6.

Fig. 3 is a schematic structural diagram of a first embodiment of a protection circuit according to the present invention.

As shown in fig. 3, the protection circuit includes a sampling circuit 8, an amplifying circuit 9, a comparing circuit 3, a self-locking circuit 4, a power device control circuit 6, and a controller 7.

The sampling circuit 8 can adopt a shunt resistor R0 to collect current in the load circuit, and the current is connected to the amplifying circuit 9 as voltage at two ends of a resistor R0.

The amplifying circuit 9 may have a variety of configurations, of which the present invention is only exemplary. The amplifying circuit comprises resistors R1-R5, capacitors C1-C4 and an operational amplifier U1. One end of the resistor R1 is electrically connected to one end of the resistor R0, one end of the resistor R2 is electrically connected to the other end of the resistor R0, the other end of the resistor R1 is electrically connected to the positive input terminal (numbered 1) of the operational amplifier U1, and the other end of the resistor R2 is electrically connected to the negative input terminal (numbered 3) of the operational amplifier U1. Operational amplifier U1 is powered by power supply VCC, and the output terminal (labeled 4) is electrically connected to resistor R5. The feedback resistor R4 has one end connected to the output terminal of the operational amplifier U1 and the other end connected to the negative input terminal of the operational amplifier U1. The resistor R4 is connected in parallel with a capacitor C3.

The capacitor C1 is connected in series with the resistor R3 and is connected to a reference voltage VREF, the capacitor C2 is connected in parallel with the resistor R3, two ends of the resistor C1 are respectively connected to a positive input end and a negative input end of the operational amplifier U1, two ends of the capacitor C4 are respectively grounded and connected to a power supply VCC, one end of the resistor R5 is connected to an output end of the operational amplifier U1, and the other end of the resistor R5 is grounded through a capacitor C5.

The comparison circuit 3 comprises a comparator U2 and a resistor R9, one end of the resistor R9 is electrically connected with the output end of the comparator U2, the other end of the resistor R9 is electrically connected with the positive input end of the comparator U2, a comparison voltage input end 2 is electrically connected with the positive input end of the comparator U2, a voltage input end 1 is electrically connected with the negative input end of the comparator U2, and the second control port 72 is electrically connected with the output end of the comparator U2.

The voltage signal amplified by the amplifying circuit 9 is supplied to one end of a resistor R6, the other end of the resistor R6 serves as a voltage input terminal 1 through a resistor R6, and the other end of the resistor R6 is connected to the negative input terminal of a comparator U2 of the comparing circuit.

The comparison voltage input end 2 comprises a direct current voltage source and a voltage division circuit, the voltage division circuit comprises a resistor R7, a resistor R8 and a capacitor C6, the direct current voltage source is electrically connected with one end of the resistor R7, the other end of the resistor R7 is electrically connected with the ground wire (grounded) through a resistor R8, a resistor R8 is connected with the capacitor C6 in parallel, and the other end of the resistor R7 is electrically connected with the positive input end of the comparison circuit.

The comparator circuit 3 may further include a pull-up resistor R10 having one end connected to the power source VCC and the other end connected to the output terminal of the comparator U2.

The self-locking circuit 4 may include a transistor Q1, a base of a transistor Q1 electrically connected to the output of the comparator U2, an emitter of a transistor Q1 electrically connected to a dc voltage source, and a collector of a transistor Q1 electrically connected to the power device control circuit.

The protection circuit further comprises a triode Q2 and a diode D1, wherein the base electrode of the triode Q2 is electrically connected with the first control port, the emitting electrode of the triode Q2 is electrically connected with the collecting electrode of the triode Q1, the collecting electrode of the triode Q2 is electrically connected with the positive electrode of the diode D1, and the negative electrode of the diode D1 is electrically connected with the negative input end of the comparator U2.

In this embodiment, the transistor Q1 is a PNP transistor, the first level is low, and the second level is high.

The working principle of the protection circuit is described below with reference to fig. 3.

When a current flows through the resistor R0, a voltage is generated across the resistor R0, which is differentially amplified by the amplifying circuit 9 for a voltage signal across R0. The advantage of using differential amplification is that the noise immunity is strong. Alternatively, a non-inverting input proportional amplifying circuit may be used instead.

The voltage signal amplified by the amplifying circuit 9 is sent to the negative input terminal of the comparator U2 to be compared with the preset voltage of the positive input terminal. When the input voltage is greater than the preset voltage, the output terminal of the comparator U2 will be flipped from high to low.

The base of the PNP transistor Q1 is connected to the output of the comparator U2, so that the comparator U2 turns on when the output is low Q1. Meanwhile, the base of the PNP transistor Q2 is connected to the first control port 71 of the MCU, and after the system is powered on, the first control port 71 remains at a low level, and the transistor Q2 is always in a conducting state.

Therefore, VCC is added to the negative input end of the comparator through Q1, Q2 and D1, so that the voltage of the negative input end is always kept to be larger than the preset voltage, the output end of the comparator U2 is always kept in a low level state, and even if a power device control circuit at the later stage turns off the power device, the current disappears, and the output end of the comparator U2 still keeps in the low level state, so that the self-locking function is realized. Before the unlocking signal source sends out the unlocking signal, the protection circuit keeps a self-locking state.

When the electronic device is unlocked, the first control port 71 of the MCU outputs a high level, the transistor Q2 is in an off state, and VCC cannot be applied to the negative input terminal of the comparator U2. Therefore, the comparison circuit 3 enters the comparison state again, and continues to compare the input voltage with the preset voltage.

Further, the second control port 72 receives a low level of the comparison circuit 3 to trigger a brake pin, also called a brake emergency pin (BKIN), in the MCU. At the moment, the MCU counts once and starts timing at the same time, and after the preset time is reached, the first control port 71 outputs a single-pulse unlocking signal to the base electrode of the triode Q2, and the Q2 is turned off, so that the self-locking loop of the comparator U2 is disconnected.

At this time, if the overcurrent fault is removed and the input voltage is less than or equal to the preset voltage, the system recovers to normal operation, and the output terminal of the comparator U2 recovers to a normal level (high level) state.

If the over-current fault is still present, the protection circuit will again enter the self-locking state, thereby initiating the aforementioned counting and timing, counting up by one. The MCU sets a certain overcurrent fault frequency (preset count), and after fault recovery is tried for multiple times, the count of the MCU is larger than the preset count, so that the fault state still exists and is not relieved. At this time, the MCU stops outputting the unlock signal and performs an overcurrent fault indication through the indication circuit.

According to the foregoing description of the embodiment, when the self-locking circuit 3 is triggered to be in the self-locking state, the power device control circuit 6 outputs a turn-off signal to turn off the power device; when the self-locking circuit 3 releases the self-locking state, the power device control circuit 6 outputs a turn-on signal to turn on the power device. With regard to the power device control circuit 6, the present invention proposes two implementations in exemplary embodiments.

First, as shown in fig. 3, the power device control circuit 6 includes a field effect transistor, a resistor R11, and a resistor R12, one end of the resistor R11 is electrically connected to the self-locking circuit 3, the other end of the resistor R11 is electrically connected to the gate of the field effect transistor, the source of the field effect transistor is electrically connected to the ground, and the drain of the field effect transistor is electrically connected to the power device.

In the present embodiment, the field effect transistor is a MOS field effect transistor (MOSFET).

As mentioned above, when the transistor Q1 is turned on, the VCC voltage is directly applied to the gate of the MOSFET, the MOSFET is turned on, and the control terminal of the power device, such as the control terminals of the upper and lower bridge arms, is set to an inactive level (e.g., a low level), so as to turn off the power device and implement the overcurrent protection function. Fig. 3 shows only one control signal for example, and those skilled in the art can also adopt multiple simultaneous controls based on the above-mentioned setting.

Alternatively, the power device control circuit 6 may also be implemented by an internal hardware functional circuit of the MCU. In some MCUs, once triggered, the emergency brake pin (BKIN) will implement the closing action of the power device through the internal hardware protection mechanism of the MCU, for example, the pin output level output invalid state of the MCU connected to the power device. For this, the MCU is required to have a corresponding functional circuit.

Those skilled in the art will recognize that power device control circuit 6 may also be implemented in other ways, such as using a transistor to turn off the control signal or connecting the output of comparator U2 to the enable of a dedicated "tri-state buffer chip" and connecting the control pins of multiple power devices to an inactive level to turn off the power devices, and the disclosure is not limited thereto.

In summary, the protection circuit according to the present invention employs a pure hardware circuit to lock the over-current state after the over-current, and triggers the power device control circuit to protect the power device, so as to effectively protect the power device from the over-current. And has the following advantages: according to the measurement and calculation of actual tests, the delay time of the protection circuit is less than 3 microseconds; due to self-locking of the self-locking circuit, enough time can be provided for the controller to process and make corresponding program processing action; after overcurrent faults occur, the power device is turned off within preset time until the controller gives an unlocking signal, the power device cannot be turned on and off for multiple times when the device is in faults, and the power device is protected; for unreal overcurrent caused by conduction or electromagnetic interference and the like, the controller can be used for judging and counting the overcurrent times, and the system can normally work again within the preset count.

In addition, the preset time and the preset count for unlocking can be adjusted according to different project application occasions and different voltage and current level occasions.

Finally, the protection circuit provided by the invention has cost benefit, and compared with a control scheme of a monostable trigger, the technical scheme of the invention can be realized by only half of the cost.

Fig. 4 is a schematic structural diagram of a second embodiment of the protection circuit according to the present invention. The present embodiment has the functions and effects of the foregoing embodiment, and only the differences from the first embodiment will be described below.

As shown in fig. 4, this second embodiment includes only one transistor Q1. Specifically, the self-locking circuit 4 includes a transistor Q1 and a diode D1, a base of the transistor Q1 is electrically connected to an output terminal of the comparator U2, an emitter of the transistor Q1 is electrically connected to the first control port 71, a collector of the transistor Q1 is electrically connected to the power device control circuit 6 and a positive electrode of the diode D1, and a negative electrode of the diode D1 is electrically connected to a negative input terminal of the comparator U2.

During normal operation, the input voltage is less than or equal to the preset voltage, the output end of the comparator U2 is at a high level, and the first control port 71 of the controller 7(MCU) outputs the high level. When overcurrent occurs, the input voltage is greater than the preset voltage, the output level of the comparator U2 is inverted to a low level, the transistor Q1 is turned on, and the high level of the first control port 71 is directly applied to the negative input end of the comparator U2, so that self-locking is caused.

When unlocking, the first control port 71 outputs a low-level pulse signal, so that the high level of the negative input terminal of the comparator U2 is restored to the input voltage, and the unlocking function is realized.

The connection and function of the second control port 72 are the same as those of the first embodiment, and are not described again.

Fig. 5 is a schematic structural diagram of a third embodiment of the protection circuit according to the present invention. The present embodiment has the functions and effects of the foregoing embodiment, and only the differences from the foregoing embodiment will be described below.

The self-locking circuit comprises a triode Q1 and a diode D1, the voltage input end 1 comprises an input voltage source and a resistor R6, the base of the triode Q1 is electrically connected with the output end of a comparator U2, the emitter of the triode Q1 is electrically connected with a direct-current voltage source, the collector of the triode Q1 is electrically connected with the power device control circuit 6 and the anode of the diode D1, one end of the resistor R6 is electrically connected with the input voltage source and the cathode of the diode D1, the other end of the resistor R6 is electrically connected with the negative input end of the comparator U2, and the first control port 71 is electrically connected with the negative input end of the comparator U2.

Specifically, the unlock signal source 5, i.e., the first control port 71, is connected to the negative input terminal of the comparator U2.

During normal operation, the input voltage is less than or equal to the preset voltage, and the output end of the comparator U2 is at a high level. When overcurrent occurs, the input voltage is greater than the preset voltage, the output end level of the comparator U2 is inverted to be a low level, the triode Q1 is conducted at the moment, and the high level of the direct-current voltage source VCC is directly applied to the negative input end of the comparator U2 so as to cause self-locking.

When the electronic lock is unlocked, the first control port 71 outputs a low-level pulse signal, so that the high level of the negative input end of the comparator U2 is restored to be input voltage, the triode Q1 is disconnected, and the unlocking function is realized.

In this embodiment, the first control port 71 may be configured to be in an open-drain output mode, and output a low-level pulse signal, so that the negative input terminal of the comparator U2 is pulled low, and the output level of the comparator U2 is restored.

Fig. 6 is a schematic structural diagram of a fourth embodiment of the protection circuit according to the present invention. The present embodiment has the functions and effects of the foregoing embodiment, and only the differences from the foregoing embodiment will be described below.

Unlike the previous embodiments, the voltage input terminal 1 of this fourth embodiment is applied to the positive input terminal of the comparator U2, so that the output logic of the comparator is different. In this embodiment, the first level is a high level, and the second level is a low level.

It should be noted that, according to the concept and teaching of the present invention, the voltage input terminal 1 of the first to third embodiments can be set at the positive input terminal, and only the components need to be adjusted accordingly.

The protection circuit of this embodiment may further include a level shift circuit having an input terminal and an output terminal. The level conversion circuit is configured to invert a level of the input terminal and output the inverted level at the output terminal, for example, invert a first level to a second level and output. The level shift circuit is used in this embodiment mainly in consideration of different output logics of the comparator. In the present embodiment, since the voltage input terminal 1 is applied to the positive input terminal of the comparator U2, when the input voltage is greater than the preset voltage, the comparator U2 outputs a high level, and the second control port 72 of the controller 7 is normally triggered by a low level, so that it is necessary to configure the level conversion circuit accordingly to convert the high level output by the comparator U2 to a low level for triggering the second control port 72 (e.g., connected to a brake pin).

Therefore, the level conversion circuit is not required to be configured for the brake pin triggered by high level.

Illustratively, the input terminal of the level conversion circuit is electrically connected to the output terminal of the comparison circuit 3. And the second control port 72 is configured to receive a flip level (in this embodiment, a low level) to trigger a brake pin in the controller 7, the controller 7 counts and starts timing at the same time, after a preset time, the first control port 71 of the controller 7 sends out an unlock signal, and the comparison circuit 3 outputs a low level.

Similar to the previous embodiment, after the first control port 71 of the receiving controller 7 sends out the unlock signal, the comparing circuit 3 continues to compare the input voltage with the preset voltage, when the input voltage is still greater than the preset voltage, the self-locking circuit 4 is triggered again, and the brake pin of the controller 7 triggers the count again, and the count is incremented by one, and when the count of the controller 7 is greater than the preset count, the controller 7 stops outputting the unlock signal and indicates that the circuit is out of order.

In this embodiment, the comparator circuit includes a comparator U2 having a comparison voltage input electrically connected to the negative input of the comparator U2 and a voltage input electrically connected to the positive input of the comparator U2, and wherein the latching circuit includes a diode D2 having an anode of the diode D2 electrically connected to the output of the comparator U2 and a cathode of the diode D2 electrically connected to the voltage input and the positive input of the comparator U2.

The level conversion circuit comprises a triode Q1, a resistor R9, a resistor R13 and a resistor R14, one end of a resistor R13 is electrically connected with the output end of the comparator U2, the other end of the resistor R13 is electrically connected with one end of a resistor R14 and the base of a triode Q1, the emitter of the triode Q1 is electrically connected with the other end of a resistor R14 and the ground wire, the collector of the triode Q1 is electrically connected with one end of the resistor R9, the other end of the resistor R9 is electrically connected with a direct-current voltage source, a first control port is electrically connected with the positive input end of the comparator U2, and a second control port is electrically connected with the collector of the triode Q1. In this embodiment, one end of the resistor R13 is used as the input terminal of the level shift circuit, and the collector of the transistor Q1 or one end of the resistor R9 is used as the output terminal of the level shift circuit.

In this embodiment, the transistor Q1 is an NPN transistor.

When an overcurrent fault occurs, the output end of the comparator U2 is inverted to output high level (the first to third embodiments are that the level is inverted from high level to low level, and the fourth embodiment is that the level is inverted from low level to high level), and a high level signal is added to the positive input end of the comparator U2 through the diode D2, so that self-locking is realized.

The unlocking function is realized by the first control port 71 of the MCU, and as long as the first control port 71 outputs a low-level pulse signal, the level of the positive input terminal of the comparator U2 is pulled low, and the level of the output terminal of the comparator U2 is restored to the low level, so as to realize the unlocking function.

In addition, when the output end of the comparator U2 is at high level, the high level is applied to the grid of the MOSFET and the base of the triode Q1(NPN triode), the MOSFET is conducted, the triode Q1 is conducted, the power device control signal is placed at an invalid level, and the power device is turned off, so that the overcurrent protection function is realized.

According to another aspect of the present invention, a circuit protection method is provided. Fig. 7 is a flow diagram of a circuit protection method in accordance with at least one embodiment of the present disclosure.

The circuit comprises a voltage input end, a comparison circuit, a self-locking circuit, an unlocking signal source and a power device control circuit. For a specific circuit example, reference may be made to the description of the foregoing embodiments, which are not repeated herein.

As shown in fig. 7, the circuit protection method includes:

comparing the preset voltage of the voltage input end with the input voltage of the voltage input end, when the input voltage is greater than the preset voltage, the comparison circuit outputs a first level, the self-locking circuit is triggered to be in a self-locking state, and the power device control circuit outputs a closing signal to close the power device; when the input voltage is less than or equal to the preset voltage, the comparison circuit outputs a second level, and the self-locking circuit is not triggered.

Illustratively, the method further comprises issuing an unlock signal through a first control port of the controller as the unlock signal source.

The controller also comprises a second control port electrically connected to the comparison circuit, the second control port receives the first level of the comparison circuit to trigger a brake pin in the controller, the controller counts and starts timing at the same time, and after a preset time, the first control port of the controller sends out an unlocking signal to enable the comparison circuit to output the second level.

Illustratively, the protection circuit may further include a level conversion circuit. The controller also comprises a second control port electrically connected to the output end of the level conversion circuit, the second control port is configured to receive the overturning level to trigger a brake pin in the controller, the controller counts and starts timing at the same time, and after the preset time is reached, the first control port of the controller sends out an unlocking signal to enable the comparison circuit to output the second level.

Illustratively, after the first control port of the receiving controller sends out the unlocking signal, the comparison circuit continues to compare the input voltage with the preset voltage, when the input voltage is still greater than the preset voltage, the self-locking circuit is triggered again, the braking pin of the controller triggers the counting again, the counting is increased by one, and when the counting of the controller is greater than the preset counting, the controller stops outputting the unlocking signal and indicates that the circuit is in fault.

The circuit protection method has a self-locking function, realizes the locking of an overcurrent state after overcurrent by adopting a pure hardware circuit, triggers the power device control circuit to protect the power device, and can effectively protect the power device from being damaged by the overcurrent. The power device is turned off within the self-locking time until an unlocking signal is given, and the power device is not turned on and off for many times when a fault occurs, so that the power device is protected.

In the above, exemplary embodiments of the protection circuit and the circuit protection method for a power device proposed by the present invention are described in detail with reference to the preferred embodiments, however, it will be understood by those skilled in the art that various modifications and changes may be made to the above specific embodiments and various combinations of the technical features and structures proposed by the present invention may be made without departing from the concept of the present invention, and the scope of the present invention is determined by the appended claims.

Claims

1. A protection circuit for a power device, comprising: the device comprises a voltage input end, a comparison circuit, a self-locking circuit, an unlocking signal source and a power device control circuit; wherein,

a voltage input terminal configured to input an input voltage related to a load voltage to the protection circuit;

the comparison voltage input end is configured to input a preset voltage to the protection circuit;

the power device control circuit is electrically connected with a peripheral power device to control the power device to be turned on and turned off;

the first input end of the comparison circuit is electrically connected with the voltage input end, the second input end of the comparison circuit is electrically connected with the comparison voltage input end, and the output end of the comparison circuit is electrically connected with the self-locking circuit;

the unlocking signal source is electrically connected with the self-locking circuit, and the power device control circuit is electrically connected with the self-locking circuit; and wherein the one or more of the one,

when the input voltage is greater than the preset voltage, the comparison circuit outputs a first level, the self-locking circuit is triggered to be in a self-locking state, and the power device control circuit outputs a closing signal to close the power device; when the input voltage is less than or equal to the preset voltage, the comparison circuit outputs a second level, and the self-locking circuit is not triggered;

2. The protection circuit of claim 1, further comprising:

and the controller comprises a first control port, and the first control port is the unlocking signal source.

3. The protection circuit of claim 2, wherein the controller further comprises a second control port electrically connected to the comparison circuit, the second control port is configured to receive the first level of the comparison circuit to trigger a brake pin in the controller, the controller counts and starts timing at the same time, and after a preset time, the first control port of the controller sends out an unlocking signal to enable the comparison circuit to output the second level.

4. The protection circuit of claim 3, wherein the comparison circuit continues to compare the input voltage to the preset voltage after the first control port of the receiving controller issues the unlock signal, the self-locking circuit is re-triggered and the brake pin of the controller re-triggers the count and increments the count by one when the input voltage is still greater than the preset voltage, and the controller stops outputting the unlock signal and indicates that the circuit is malfunctioning when the count of the controller is greater than the preset count.

5. The protection circuit of claim 3, wherein the comparison circuit includes a comparator U2 and a resistor R9, the resistor R9 having one end electrically connected to the output of the comparator U2 and another end electrically connected to a positive input of the comparator U2, a comparison voltage input electrically connected to a positive input of the comparator U2, a voltage input electrically connected to a negative input of the comparator U2, and a second control port electrically connected to the output of the comparator U2.

6. The protection circuit of claim 5, wherein the self-latching circuit comprises a transistor Q1, a base of a transistor Q1 is electrically connected to the output of the comparator U2, an emitter of a transistor Q1 is electrically connected to a DC voltage source, and a collector of a transistor Q1 is electrically connected to the power device control circuit.

7. The protection circuit of claim 6, further comprising: the triode Q2 and the diode D1, the base of the triode Q2 is electrically connected with the first control port, the emitter of the triode Q2 is electrically connected with the collector of the triode Q1, the collector of the triode Q2 is electrically connected with the positive pole of the diode D1, and the negative pole of the diode D1 is electrically connected with the negative input end of the comparator U2.

8. The protection circuit of claim 5, wherein the self-latching circuit comprises a transistor Q1 and a diode D1, a base of a transistor Q1 is electrically connected to the output of the comparator U2, an emitter of a transistor Q1 is electrically connected to the first control port, a collector of a transistor Q1 is electrically connected to the power device control circuit and to the positive terminal of a diode D1, and a cathode of a diode D1 is electrically connected to the negative input of the comparator U2.

9. The protection circuit of claim 5, wherein the latching circuit comprises a transistor Q1 and a diode D1, the voltage inputs comprise an input voltage source and a resistor R6, a base of the transistor Q1 is electrically connected to an output of the comparator U2, an emitter of the transistor Q1 is electrically connected to a DC voltage source, a collector of the transistor Q1 is electrically connected to the power device control circuit and to a positive terminal of the diode D1, one end of the resistor R6 is electrically connected to the input voltage source and to a negative terminal of the diode D1, the other end of the resistor R6 is electrically connected to a negative input of the comparator U2, and the first control port is electrically connected to the negative input of the comparator U2.

10. The protection circuit of any of claims 5-9, wherein the transistor Q1 is a PNP transistor, the first level is low, and the second level is high.

11. The protection circuit of claim 2, further comprising: the controller further comprises a second control port electrically connected to the output end of the level conversion circuit, the second control port is configured to receive the upset level to trigger a brake pin in the controller, the controller counts and starts timing at the same time, and after a preset time is reached, the first control port of the controller sends an unlocking signal to enable the comparison circuit to output a second level.

12. The protection circuit of claim 11, wherein the comparison circuit continues to compare the input voltage to the preset voltage after the first control port of the receiving controller issues the unlock signal, the self-locking circuit is re-triggered and the brake pin of the controller re-triggers the count and increments the count by one when the input voltage is still greater than the preset voltage, and the controller stops outputting the unlock signal and indicates that the circuit is malfunctioning when the count of the controller is greater than the preset count.

13. The protection circuit of claim 11, wherein the comparison circuit includes a comparator U2, a comparison voltage input electrically connected to a negative input of a comparator U2, and a voltage input electrically connected to a positive input of a comparator U2, and wherein the self-locking circuit includes a diode D2, a positive pole of the diode D2 electrically connected to an output of the comparator U2, and a negative pole of the diode D2 electrically connected to the voltage input and the positive input of the comparator U2.

14. The protection circuit of any one of claims 11-13, wherein the level conversion circuit comprises a transistor Q1, a resistor R9, a resistor R13, and a resistor R14, one end of the resistor R13 is electrically connected to the output terminal of the comparator U2, the other end of the resistor R13 is electrically connected to one end of the resistor R14 and the base of the transistor Q1, the emitter of the transistor Q1 is electrically connected to the other end of the resistor R14 and the ground, the collector of the transistor Q1 is electrically connected to one end of the resistor R9, the other end of the resistor R9 is electrically connected to a dc voltage source, the first control port is electrically connected to the positive input terminal of the comparator U2, and the second control port is electrically connected to the collector of the transistor Q1.

15. The protection circuit of claim 14, wherein the transistor Q1 is an NPN transistor, the first level is high, and the second level is low.

16. The protection circuit of claim 1, wherein the comparison voltage input terminal comprises a dc voltage source and a voltage divider circuit, the voltage divider circuit comprises a resistor R7, a resistor R8 and a capacitor C6, the dc voltage source is electrically connected to one end of the resistor R7, the other end of the resistor R7 is electrically connected to ground through a resistor R8, a resistor R8 is connected in parallel to the capacitor C6, and the other end of the resistor R7 is electrically connected to the second input terminal of the comparison circuit.

17. The protection circuit of claim 1, wherein the power device control circuit comprises a field effect transistor, a resistor R11 and a resistor R12, one end of the resistor R11 is electrically connected with the self-locking circuit, the other end of the resistor R11 is electrically connected with the gate of the field effect transistor, the source of the field effect transistor is electrically connected with the ground, and the drain of the field effect transistor is electrically connected with the power device.

18. The protection circuit of claim 17, wherein the field effect transistor is a MOS field effect transistor.

19. The protection circuit of claim 3 or 4, wherein the power device control circuit comprises the controller, the controller comprises a third control port electrically connected with a power device, and the third control port is configured to output a level signal to turn off the power device when the brake pin is triggered.

20. The protection circuit of claim 1, further comprising: and the sampling circuit is configured to sample a current signal of the load and convert the current signal into a voltage signal.

21. The protection circuit of claim 20, further comprising: and the amplifying circuit is configured to amplify and output the voltage signal of the sampling circuit to a voltage input end.

22. A circuit protection method, the circuit includes a voltage input end, a comparison circuit, a self-locking circuit, an unlocking signal source and a power device control circuit, the method includes:

comparing the preset voltage of the voltage input end with the input voltage of the voltage input end, when the input voltage is greater than the preset voltage, the comparison circuit outputs a first level, the self-locking circuit is triggered to be in a self-locking state, and the power device control circuit outputs a closing signal to close the power device; when the input voltage is less than or equal to the preset voltage, the comparison circuit outputs a second level, and the self-locking circuit is not triggered;

23. The method of claim 22, further comprising: and sending the unlocking signal by using a first control port of the controller as an unlocking signal source.

24. The method of claim 23, wherein the controller further comprises a second control port electrically connected to the comparison circuit, the second control port receives the first level of the comparison circuit to trigger a brake pin in the controller, the controller counts and starts timing at the same time, and after a preset time, the first control port of the controller sends out an unlock signal to enable the comparison circuit to output the second level.

25. The method of claim 23, wherein the protection circuit further comprises: the controller further comprises a second control port electrically connected to the output end of the level conversion circuit, the second control port is configured to receive the upset level to trigger a brake pin in the controller, the controller counts and starts timing at the same time, and after a preset time is reached, the first control port of the controller sends an unlocking signal to enable the comparison circuit to output a second level.

26. The method of claim 24 or 25, wherein after the first control port of the receiving controller issues the unlock signal, the comparison circuit continues to compare the input voltage with the preset voltage, when the input voltage is still greater than the preset voltage, the self-locking circuit is triggered again, and the brake pin of the controller triggers the count again, and the count is incremented by one, and when the count of the controller is greater than the preset count, the controller stops outputting the unlock signal and indicates that the circuit is malfunctioning.