CN112131814A - FPGA layout legalization method utilizing regional re-layout - Google Patents
FPGA layout legalization method utilizing regional re-layout Download PDFInfo
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Abstract
The invention discloses an FPGA layout legalization method by using regional rearrangement, which relates to the technical field of FPGA, and the method abstractly establishes a residual graph by regions in an initial layout state, assigns directed edges formed by abstracting the relationship between a redistributeable node and a deployable position in the residual graph by using line length as the cost of the edges, solves the residual graph based on a minimum cost maximum flow algorithm to obtain the final legal position of each redistributeable node, applies the maximum flow algorithm to the legalization part of a secondary linear programming algorithm, enables the original legalization process without guidance to have guidance, and optimizes the initial layout to a certain extent while legalizing to ensure that the legalized line length is shorter, the final solution quality is improved to a certain extent, and the layout position occupied by the legal node is also involved in modeling solution, The layout result is better.
Description
Technical Field
The invention relates to the technical field of FPGA, in particular to an FPGA layout legalization method utilizing area rearrangement.
Background
A Field-Programmable Gate Array (FPGA) is a chip widely used in household appliances, large machinery and even aerospace. The use of FPGA chips does not require Electronic Design Automation (EDA) tools. Layout is an important ring in EDA tools, which has a large impact on the speed of operation of the EDA tool itself, and the ultimate quality of the processed circuit.
In recent years, the circuit scale of FPGA chips has rapidly increased to make them more powerful, but at the same time, it has also presented challenges to the corresponding EDA tools. Analytical algorithms are one of the mainstream directions in present-day layout algorithms due to their property of being able to use mathematical methods to quickly find the global optimal solution. The quadratic linear programming algorithm is one of analytic algorithms, and when the quadratic linear programming algorithm is specifically applied to solving a layout problem, the characteristic of fast solving is shown, but after the solving is completed, an illegal layout still exists, for example, common nodes with overlapping exist, and therefore, the legal operation needs to be performed again.
The traditional legalization operation uses a simple nearby placement principle to process illegal nodes, namely a nearest legal position is searched for around the illegal nodes based on a Manhattan distance graph, as shown in FIG. 1, a central position 0 is the position where the illegal nodes are located, distances of four positions, namely an upper position, a lower position, a left position and a right position, which are directly connected with the illegal nodes, are marked as 1, distances of positions, which are directly connected with the positions of the. The existing legalization operation sequentially searches for vacant legal positions from near to far according to a Manhattan distance graph to place the current illegal node. The method is simple and feasible, but has no guidance, and the following problems exist in the selection process, such as: is the location distance marked by manhattan distance, is the distance close must be better than the distance far? There are multiple locations with the same manhattan distance, and whether these locations are the same or not? These problems lead to the original legalization process not considering the layout quality problem after the legalization although the illegal layout can be quickly legalized, which often leads to the final solution being unsatisfactory.
Disclosure of Invention
The invention provides an FPGA layout legalization method using area re-layout aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:
a method for legalizing an FPGA layout by using area re-layout comprises the following steps:
determining the line length of each net according to the initial layout state of the FPGA, wherein the initial layout state comprises a plurality of redistributable nodes, the redistributable nodes comprise a plurality of legal nodes which are designated to be placed on legal positions of the FPGA and a plurality of illegal nodes which are not designated to the legal positions, and each redistributable node is a functional module in the layout netlist;
dividing the FPGA into a plurality of areas, and selecting a target area from the divided areas according to an initial layout state, wherein the target area is an area internally containing at least one illegal node;
abstracting the initial layout state in each target area to establish a residual graph, wherein the residual graph at least comprises graph nodes abstractly formed by each redistributable node and each distributable position in the target area and first directed edges between the corresponding graph nodes abstractly formed by the relationship between each redistributable node and the distributable position; the deployable positions include layout positions within the target area that have been assigned to legitimate nodes and layout positions that are unoccupied by any node;
assigning values to each first directed edge in the residual graph by using the line length of the corresponding line net to obtain the cost of each first directed edge;
solving the residual graph based on a minimum-cost maximum-flow algorithm, updating the residual graph until the residual graph with the maximum flow and the minimum cost under the same flow condition is obtained, and determining the final legal position of each redistributable node in the finally obtained residual graph as a distributable position in the same path;
and obtaining the final legal position of each redistribution node, and placing each redistribution node to the corresponding final legal position to finish layout legalization of the FPGA.
The method comprises the following steps that the initial layout state further comprises a plurality of fixed nodes which are designated to be placed on legal positions of the FPGA, each fixed node is also a functional module in the layout netlist, the reconfigurable nodes in each target area are all functional modules except the fixed nodes, the reconfigurable positions in each target area are all layout positions except the legal positions occupied by the fixed nodes, and the layout positions occupied by the fixed nodes are kept unchanged before and after layout legalization of the FPGA.
The further technical scheme is that the fixed node comprises at least one functional module of BRAM, CMT, DSP, GTP, PCI and EMAC.
The further technical scheme is that the method for obtaining the final legal position of each redistributable node further comprises the following steps:
for each target area, marking the redistributable nodes of which the final legal positions are not found in the current target area in the target area;
after traversing all target areas in the FPGA, if marked redistributable nodes are contained in the overall area of the FPGA, the FPGA is divided into a plurality of new areas with area ranges larger than the current area again, and a new target area containing at least one marked redistributable node is selected from the divided new areas according to the initial layout state;
and abstracting each redistributable node and each redistributable position in each new target area to establish a residual graph and solving to obtain a final legal position, corresponding to each redistributable node in the new target area, in the target area, and marking the redistributable nodes of which the final legal position is not found in the current target area in the target area.
The further technical scheme is that the number of the total layout positions contained in each target area is not less than the number of the total functional modules contained in the target area.
The method comprises the following steps that a plurality of nodes which can be redistributed in each target area belong to different node categories, the nodes which can be redistributed in the target area belong to different position categories, and the node categories and the position categories have corresponding relations, so that the number of the nodes which can be redistributed in each position category in the target area is not less than that of the nodes which can be redistributed in the corresponding node category.
The further technical scheme is that the FPGA is divided into a plurality of areas, and the method comprises the following steps:
and dividing the FPGA according to each domain in the FPGA architecture, wherein each divided domain is the same as each domain of the FPGA architecture.
The further technical scheme is that the FPGA is divided into a plurality of areas, and the method comprises the following steps:
and dividing the FPGA according to a user-defined division rule, wherein each divided region is different from each region of the FPGA framework.
The further technical scheme is that the area ranges of all the areas obtained by dividing the FPGA are the same.
The further technical scheme is that at least two regions of each region obtained by dividing the FPGA have different region ranges.
The further technical scheme is that the method for establishing the residual diagram by abstracting the initial layout state in each target area comprises the following steps:
abstracting each redistributable node and each distributable position in the initial layout state to form a graph node, and abstracting the relationship between the redistributable node and the distributable position to form a first directed edge between the corresponding graph nodes; establishing a virtual source point, establishing a second directed edge between the virtual source end and the graph node of each distributable node, establishing a virtual terminal, and establishing a third directed edge between the graph node of each distributable position and the virtual terminal;
the method further comprises: and assigning 0 to both the second directed edge and the third directed edge.
The further technical scheme is that the residual graph is solved based on the minimum cost maximum flow algorithm and is updated until the residual graph with the maximum flow and the minimum cost under the same flow condition is obtained, and the method comprises the following steps:
searching a path with the minimum cost in the residual graph by utilizing a Dijkstra shortest path algorithm;
the path is augmented, all the first directed edges on the path with the minimum searched cost are reversed, and the cost of the first directed edges is negated to obtain a new residual graph;
and re-executing the step of searching the path with the minimum cost in the residual graph by utilizing the Dijkstra shortest path algorithm until the residual graph with the maximum flow and the minimum cost under the condition of the same flow is obtained when no path exists between the virtual source point and the virtual destination point.
The technical scheme is that each redistribution node is a functional module in the layout netlist, the functional module is a minimum basic unit in the layout netlist, and the functional module corresponds to a slice level module or a lookup table/register level module in the FPGA architecture.
The further technical scheme is that the method for determining the line length of each line net according to the initial layout state of the FPGA comprises the following steps:
establishing a boundary frame structure according to the initial layout state, wherein the boundary frame structure records the state of a wire net according to the boundary position and the number of nodes positioned on the boundary;
obtaining the half perimeter of each wire mesh according to the bounding box structure;
determining an influence factor corresponding to the size of the net of each net according to a preset relation, wherein the size of the net is the number of nodes in the net;
and determining the product of the half-perimeter of each wire mesh and the corresponding influence factor as the wire length of the wire mesh.
The beneficial technical effects of the invention are as follows:
the method comprises the steps of abstracting a redistributable node and a redistributable position to form a residual graph so as to convert a layout legalization problem into solving a maximum flow from a virtual source point to a virtual destination in the residual graph, evaluating by line length, assigning a value to a directed edge from each redistributable node to the redistributable position as a cost value, and further converting the layout legalization problem into a minimum-cost maximum flow problem in a maximum flow algorithm; the method applies the maximum flow algorithm to the legalization part of the quadratic linear programming algorithm, so that the legalization process which originally does not have guidance becomes guidance, the quality of final solution is improved to a certain extent, the legalized line length is shorter, and the layout result is better. Meanwhile, the legal nodes and the layout positions occupied by the legal nodes also participate in modeling solution, so that the initial layout is optimized by the maximum flow algorithm besides the legalization of the illegal nodes, and the layout result is better.
Drawings
FIG. 1 is a Manhattan distance graph used in prior art layout legalization of FPGAs.
FIG. 2 is a method flow diagram of a method of legalization of an FPGA layout of the present application.
FIG. 3 is a schematic diagram of the remaining graph formed for a redistributable node and a deployable location abstraction.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
The application discloses a method for legalizing an FPGA layout by using regional re-layout, please refer to a flow chart shown in FIG. 2, the method comprises the following steps:
and step S1, after the initial layout of the FPGA is completed, determining the line length of each line net according to the initial layout state of the FPGA.
The FPGA is provided with a plurality of layout positions, each functional module in the layout netlist is laid out on the FPGA by using a layout algorithm during initial layout, the layout algorithm used during initial layout can be a conventional analytic algorithm, and details are not repeated in the application. After the initial layout is completed, a part of the functional modules in the layout netlist are respectively assigned and arranged at each layout position of the FPGA, so that the layout of the part of the functional modules is legal, and the layout of the part of the functional modules is illegal if the positions of the functional modules are overlapped. Accordingly, among all the layout positions on the FPGA, a part of the layout positions may be assigned to one functional module, the layout positions are legal positions, a part of the layout positions may be assigned to a plurality of functional modules, and a part of the layout positions may not be assigned to any functional module.
The functional modules which are respectively appointed to be arranged at the legal positions of the FPGA can comprise two types: one is called legal node, the other is called fixed node, the legal node is a functional module which is assigned to be placed on the legal position of the FPGA and the position of which can be changed again, and the fixed node is a functional module which is assigned to be placed on the legal position of the FPGA and the position of which can not be changed again, namely the layout position of the fixed node can not be changed after being determined according to the initial layout state, the fixed node is usually marked in advance and can exist zero or any more, in the application, the fixed node comprises at least one functional module of BRAM, CMT, DSP, GTP, PCI and EMAC.
Thus, in the present application, the initial layout state includes several re-distributable nodes, or alternatively, several re-distributable nodes and several fixed nodes. Both the redistributable node and the fixed node are functional modules in the layout netlist, and the functional module is the minimum basic unit in the layout netlist and corresponds to a slice-level module or a look-up table/register (LUT/REG) level module in the FPGA architecture. The redistribution nodes comprise a plurality of legal nodes and a plurality of illegal nodes, the illegal nodes are functional modules which are not assigned with legal positions, and the legal nodes and the fixed nodes are defined as above.
In addition, the initial layout state further includes a plurality of distributable positions on the FPGA, or further includes a plurality of distributable positions and fixed positions on the FPGA, and both the distributable positions and the fixed positions are one layout position on the FPGA. The distributable positions comprise layout positions assigned to legal nodes and layout positions not occupied by any nodes, and the fixed positions are the layout positions assigned to the fixed nodes.
When the wire length of each wire mesh is determined, the half perimeter of each wire mesh and the wire mesh size of each wire mesh are determined, wherein the wire mesh size is the number of nodes included in each wire mesh. When the half-perimeter of the nets is determined, a bounding box structure (bounding box structure) is firstly established according to an initial layout state, then the half-perimeter of each net is obtained according to the bounding box structure, and the state of the nets is recorded by the bounding box structure according to the boundary positions and the number of nodes positioned on the boundary. And determining the influence factor corresponding to the size of the net of each net according to the preset relation, wherein the length of each net is the product of the half perimeter of the net and the corresponding influence factor. The preset relation between the size of the wire mesh and the influence factor can be obtained by fitting in advance, and a specific functional relation is not provided.
Step S2, dividing the FPGA into a plurality of areas, and selecting a target area from the divided areas according to the initial layout state, wherein the target area is an area containing at least one illegal node inside.
The present application provides two divisions:
(1) and dividing the FPGA according to each domain in the FPGA architecture, wherein each divided domain is the same as each domain of the FPGA architecture.
(2) And dividing the FPGA according to the customized division rule, wherein each divided region is different from each domain of the FPGA framework.
The area ranges of the divided areas may be the same, or there may be at least two areas with different area ranges, but the layout position and the function module in each area need to satisfy the following conditions:
the total number of layout positions contained in each area is not less than the total number of functional modules contained in the area, and since the fixed nodes and the fixed positions occupied by the fixed nodes are fixed, the total number of distributable positions contained in each area is not less than the total number of distributable nodes contained in the area. For example, a region contains K layout positions, wherein K1 distributable positions and K2 fixed positions, and the region contains L function modules, wherein L1 distributable nodes and L2 fixed nodes, K is larger than or equal to L, K1 is larger than or equal to L1, and K2 is equal to L2.
Further, in the present application, all the redistributable nodes may belong to several different node classes according to the function class, and each node class includes several redistributable nodes (including legitimate nodes and/or illegitimate nodes). The deployable locations on the corresponding FPGA also belong to several different location categories, each location category including several deployable locations (including layout locations that have been assigned to legitimate nodes and/or layout locations that are unoccupied by any node). The node category and the position category have a corresponding relationship, which may be a many-to-many relationship, and the correspondence indicates that the redistribution nodes belonging to one node category are arranged at the redistribution positions of the corresponding position category, so that the number of redistribution nodes included in each position category in each region is not less than the number of redistribution nodes included in the corresponding node category. For example, in the above example, it is assumed that L1 redistributable nodes belong to node class 1 and node class 2, where node class 1 contains L11 redistributable nodes and node class 2 contains L12 redistributable nodes. The K1 deployable positions belong to a position class 1 and a position class 2, the position class 1 comprises K11 deployable positions, the position class 2 comprises K12 deployable positions, and if the node class 1 corresponds to the position class 1 and the node class 2 corresponds to the position class 2, K11 ≧ L11 and K12 ≧ L12 are required to be satisfied in addition to the above-mentioned requirement that K1 ≧ L1 are required to be satisfied.
In step S3, a residual diagram is created by abstracting the initial layout state in each target area.
When the residual graph is established, each redistributable node and each distributable position in the initial layout state of the target area are abstracted to form graph nodes, and the relationship between the redistributable nodes and the distributable positions is abstracted to form a first directed edge between the corresponding graph nodes. The remaining graph thus includes at least a first directed edge between graph nodes abstractly formed for each re-arrangeable node and each deployable location within the target area, and corresponding graph nodes abstractly formed for relationships between each re-arrangeable node and the deployable location.
In addition, when the residual graph is established, a virtual source point S is also established, a second directed edge is established between the virtual source point S and the graph nodes of all the nodes capable of being redistributed, a virtual terminal point T is established, and a third directed edge is established between the graph nodes of all the vacant positions and the virtual terminal point T.
The schematic diagram of the created residual graph is shown in fig. 3, wherein for the graph nodes formed by the abstraction of the redistributable nodes, the graph nodes formed by the abstraction of the legal nodes are shaded, and the graph nodes formed by the abstraction of the illegal nodes are blank. And for the graphic nodes formed by the deployable position abstraction, the graphic nodes formed by the layout position abstraction occupied by the legal nodes are represented by shading, and the graphic nodes formed by the layout position abstraction not occupied by any node are represented by blank. The layout legalization problem thus becomes a solution to the maximum flow from the virtual source point S to the virtual destination point T. In order to make the searching process have guidance, the method and the device use the line length to evaluate, use the line length of the net corresponding to each first directed edge to assign the first directed edge to obtain the Cost of each first directed edge, and assign the Cost of all the second directed edges and the Cost of the third directed edges to 0, so that the layout legalization problem is further converted into the problem of the minimum Cost maximum Flow (Min-Cost Max-Flow) in the maximum Flow algorithm.
And step S4, solving the residual graph based on the minimum cost maximum flow algorithm, updating the residual graph until the residual graph with the maximum flow and the minimum cost under the same flow is obtained, and determining the final legal position of each redistributable node in the finally obtained residual graph to be the distributable position in the same path.
The solving process is as follows:
(1) and finding the path with the minimum cost in the residual graph by utilizing a Dijkstra shortest path algorithm. The Dijkstra shortest path algorithm does not allow a negative value to occur in a path in the remaining graph, and therefore, a potential is added to each graph node to convert the remaining graph containing the path with the negative cost into a graph containing no path with the negative cost under the condition that the structure of the remaining graph is guaranteed to be unchanged so as to be applicable to the algorithm, for example, corresponding values can be added to the costs of all paths at the same time, and the like, which is not described in detail in the present application.
(2) And (4) augmenting the path, reversing all the first directed edges on the path with the minimum searched cost, and taking the negative cost of the first directed edges to obtain a new residual graph.
(3) And (3) re-executing the steps (1) and (2) until no path exists between the virtual source point S and the virtual destination point T, wherein the obtained residual graph is the residual graph with the largest flow and the smallest cost under the condition of the same flow.
The above process uses the Ford-Fulkerson algorithm to ensure that the maximum flow is found at last, and a mathematical induction method can be used to simply prove that the flow with the minimum cost under the current flow is found out in each cycle of the solving process, wherein the relevant properties of the related graph are not described herein again:
1. this is clearly true for a flow rate of 1.
2. If the flow rate is i, f is the least expensive flow, and the remaining graph does not necessarily contain a negative cost loop.
3. And (3) marking the flow with the flow rate of i +1 deduced by the solving method as g, and marking the path g-f as a path with the minimum cost of the virtual source point S and the virtual end point T as r.
4. If there is a flow h with a flow rate of i +1 that costs less than g, then for the two flows with the same flow rate, there must be a loop for h-g, and because the cost of h is less than g, at least one loop with a negative cost must be included in the loop of h-g, then h-f is composed of path r and several loops with a negative cost, i.e. there is a negative cost loop in the remaining graph of f.
5. If there are negative loops in the remaining graph of f, then f is not the least expensive flow with flow i, which is contrary to the assumption.
6. Therefore, g is the least expensive flow at the flow rate of i +1, as was discussed.
And step S5, obtaining the final legal position of each redistributable node.
Because the legal nodes in the initial layout state and the layout positions occupied by the legal nodes participate in modeling solution together, the legal positions of the legal nodes can be obtained again after the solution, and the new legal positions of the legal nodes can be obtained again, so that the layout legalization is finished by the method, and the original layout is optimized.
Meanwhile, the nodes which can be rearranged are all other functional modules except the fixed nodes, and the positions which can be arranged are all other layout positions except the legal positions occupied by the fixed nodes, namely the fixed nodes and the fixed positions do not participate in modeling, so that the fixed nodes always occupy the original layout positions, and the layout positions occupied by the fixed nodes are kept unchanged before and after the layout of the FPGA is legal.
In an ideal state, all the redistribution nodes in each target area can find corresponding final legal positions in the redistribution positions of the current target area, and the final legal positions of the redistribution nodes in each target area can be respectively obtained after all the target areas in the FPGA are directly traversed.
However, in an actual situation, since resources in a single target area are limited, there may be a situation that resources in one target area are exhausted but a redistribution node still cannot find a final legal position, but the nature of the quadratic linear programming algorithm can know that the number of redistribution nodes in the theoretical situation is small, so if the situation occurs, firstly, a redistribution node in each target area, which does not find a final legal position in the current target area, is marked, and after all target areas are traversed, all marked redistribution nodes are uniformly processed, wherein the method includes:
the FPGA is divided into a plurality of new areas with area ranges larger than the current area again, and the FPGA can be directly divided again in actual operation or a plurality of adjacent current areas are combined. And selecting a new target area containing at least one marked redistributable node in the new divided areas according to the initial layout state. And abstracting and establishing a residual graph and solving each redistributable node and each redistributable position in each new target area to obtain a final legal position, corresponding to each redistributable node in the new target area, in the target area. Namely, the processing is still carried out according to the region, and the final legal position of each reconfigurable node is found in a larger region with more resources by using the steps for the reconfigurable nodes and the reconfigurable positions. Similarly, if there are still redistributable nodes without corresponding final legal positions, marking is performed in the same way, after traversal, if there are still marked redistributable nodes, the FPGA is divided into a plurality of new areas with area ranges larger than the current area again, iteration is performed until all the redistributable nodes have final legal positions, and in this case, it is possible to loop to search in the global range finally.
If the fixed nodes exist, the layout positions of the fixed nodes are kept unchanged, and each redistribution node is placed to the corresponding final legal position, so that layout legalization of the FPGA is completed.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.
Claims (14)
1. A method for legalizing an FPGA layout by using area re-layout is characterized by comprising the following steps:
determining the line length of each net according to the initial layout state of the FPGA, wherein the initial layout state comprises a plurality of redistributable nodes, the redistributable nodes comprise a plurality of legal nodes which are designated to be placed on legal positions of the FPGA and a plurality of illegal nodes which are not designated to the legal positions, and each redistributable node is a functional module in a layout netlist;
dividing the FPGA into a plurality of areas, and selecting a target area from the divided areas according to the initial layout state, wherein the target area is an area internally containing at least one illegal node;
abstracting the initial layout state in each target area to establish a residual graph, wherein the residual graph at least comprises graph nodes abstractly formed by each redistributable node and each distributable position in the target area and first directed edges between corresponding graph nodes abstractly formed by the relationship between each redistributable node and the distributable position; the deployable positions comprise layout positions within the target area that have been assigned to legitimate nodes and layout positions that are unoccupied by any node;
assigning values to each first directed edge in the residual graph by using the line length of the corresponding line net to obtain the cost of each first directed edge;
solving the residual graph based on a minimum-cost maximum-flow algorithm, updating the residual graph until the residual graph with the maximum flow and the minimum cost under the condition of the same flow is obtained, and determining the final legal position of each redistributable node in the finally obtained residual graph to be a distributable position in the same path;
and obtaining the final legal position of each redistribution node, and placing each redistribution node to the corresponding final legal position to finish the layout legalization of the FPGA.
2. The method according to claim 1, wherein the initial layout state further includes a plurality of fixed nodes that have been designated to be placed at legal positions of the FPGA, each of the fixed nodes is also a functional module in the layout netlist, so that the reconfigurable nodes in each target region are all the functional modules except the fixed nodes, the reconfigurable positions in each target region are all the layout positions except the legal positions occupied by the fixed nodes, and the layout positions occupied by the fixed nodes remain unchanged before and after the layout of the FPGA is legal.
3. The method of claim 2, wherein the fixed node comprises at least one functional module of BRAM, CMT, DSP, GTP, PCI, and EMAC.
4. The method of claim 1, wherein obtaining the final legal location of each redistributable node further comprises:
for each target area, marking the redistributable nodes of which the final legal positions are not found in the current target area in the target area;
after traversing all target areas in the FPGA, if marked redistributable nodes are contained in the overall area of the FPGA, the FPGA is divided into a plurality of new areas with area ranges larger than the current area again, and a new target area containing at least one marked redistributable node is selected from the divided new areas according to the initial layout state;
abstracting and establishing a residual graph and solving each redistributable node and each redistributable position in each new target area to obtain a final legal position, corresponding to each redistributable node in the new target area, in the target area, and performing the step of marking the redistributable nodes, which are not located in the current target area, in the target area.
5. The method of claim 1, wherein the total number of layout positions contained within each target area is not less than the total number of functional modules contained within the target area.
6. The method according to claim 5, wherein the redistribution nodes in each target area belong to a plurality of different node categories, the redistribution positions in the target area belong to a plurality of different position categories, and there is a correspondence between a node category and a position category, so that the number of redistribution nodes included in each position category in the target area is not less than the number of redistribution nodes included in the corresponding node category.
7. The method according to any of claims 1-6, wherein said dividing said FPGA into a number of regions comprises:
and dividing the FPGA according to each domain in the FPGA architecture, wherein each divided domain is the same as each domain of the FPGA architecture.
8. The method according to any of claims 1-6, wherein said dividing said FPGA into a number of regions comprises:
and dividing the FPGA according to a user-defined division rule, wherein each divided region is different from each domain of the FPGA framework.
9. The method according to any one of claims 1 to 6, wherein the area ranges of the respective areas obtained by dividing the FPGA are the same.
10. The method according to any one of claims 1 to 6, wherein there are at least two regions having different region ranges for each region divided by the FPGA.
11. The method according to any one of claims 1-6, wherein abstracting the initial layout state in each of the target regions to create a residual graph comprises:
abstracting each redistributable node and each distributable position in the initial layout state to form a graph node, and abstracting the relationship between the redistributable node and the distributable position to form a first directed edge between the corresponding graph nodes; establishing a virtual source point, establishing a second directed edge between the virtual source point and the graph node of each distributable node, establishing a virtual terminal, and establishing a third directed edge between the graph node of each distributable position and the virtual terminal;
the method further comprises: and assigning 0 to both the second directed edge and the third directed edge.
12. The method of claim 11, wherein the solving the residual graph based on the min-cost max-flow algorithm and updating the residual graph until a residual graph with a largest flow and a smallest cost at the same flow rate is obtained comprises:
finding a path with the minimum cost in the residual graph by utilizing a Dijkstra shortest path algorithm;
the path is augmented, all the first directed edges on the path with the minimum searched cost are reversed, and the cost of the first directed edges is taken as negative, so that a new residual graph is obtained;
and re-executing the step of searching the path with the minimum cost in the residual graph by utilizing the Dijkstra shortest path algorithm until the residual graph with the maximum flow and the minimum cost under the condition of the same flow is obtained when no path exists between the virtual source point and the virtual destination point.
13. The method of claim 1, wherein each redistributable node is a functional module in the layout netlist, the functional module is the smallest basic unit in the layout netlist, and the functional module corresponds to a slice-level module or a look-up table/register-level module in the FPGA architecture.
14. The method of claim 1, wherein determining the line length of each net according to the initial layout state of the FPGA comprises:
establishing a boundary frame structure according to the initial layout state, wherein the boundary frame structure records the state of the wire network according to the boundary position and the number of the nodes positioned on the boundary;
obtaining the half perimeter of each wire mesh according to the bounding box structure;
determining an influence factor corresponding to the size of a net of each net according to a predetermined relationship, wherein the size of the net is the number of nodes in the net;
and determining the product of the half perimeter of each wire mesh and the corresponding influence factor as the wire length of the wire mesh.
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