CN106021722A - FPGA layout-based optimization method - Google Patents
FPGA layout-based optimization method Download PDFInfo
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- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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Abstract
The invention provides an FPGA layout-based optimization method. The method comprises the steps of dividing an FPGA into a plurality of grids same in size, and calculating a wire net length and an area density sum; constructing a cost function consisting of the wire net length and the area density sum, and obtaining initial layout coordinates of each node when the cost function is minimized by applying a mathematic analysis method; obtaining adjustment coordinates of each node according to the initial layout coordinates of each node and a rectangular judgment frame in a grid where each node is located; and calculating area density of each grid and determining a density state of each grid for a layout formed by the adjustment coordinates of each node, and performing solving on the cost function again to obtain optimized layout coordinates of each node when the cost function is minimized. According to the method, nodes in a grid with the relatively high density can be quickly and effectively diffused to grids around so as to obtain a more excellent layout.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly relate to a kind of optimization method based on FPGA layout.
Background technology
In recent years, along with developing rapidly of integrated circuit technique, FPGA (Field-Programmable Gate
Array, field programmable gate array) because having that integrated level is high, logical resource is abundant, flexible design and can
The feature such as reconstitution and be used widely.
The resource of FPGA is mainly by programmed logical module (Configurable Logic Block, CLB), defeated
Enter output module (Input Output Block, IOB) and interconnector (Interconnect) three parts group
Becoming, wherein, programmed logical module is by several basic logic units (Basic Logic Element, BLE)
Composition.Under normal circumstances, above-mentioned resource is not evenly distributed on fpga chip.If placement algorithm
Designing unreasonable, may result in the resource that should put together, be but placed is far, so that
Wiring difficulty increases, and sequential time delay is long, can not meet the design requirement of user.As can be seen here, at FPGA
Layout designs in, the actual performance of fpga chip is affected the biggest by the reasonability of layout.
At present, existing FPGA placement algorithm has iterative algorithm, smallest partition method and mathematical programming approach, base
Main thought in the placement algorithm of mathematical programming approach is:
First stage initial layout, obtains the ideal position of each node.
The cost function that structure is made up of gauze length function and area density function, and obtained by analytic method
To making the minimum globally optimal solution of described integrate-cost function, it is the ideal position of each node.
Second stage local legalizes detection, obtains the correct position of each node.
Specifically, local legalizes detection as shown in Figure 1, it is assumed that obtain 10 nodes all by initial layout
Fall in grid 1, due to the resource-constrained in grid 1 (for convenience of explanation, it is assumed here that in grid 1
A node can only be placed), it is necessarily required to be placed on unnecessary node in other grid, i.e. according to position
2, the order of 3,4,5 gradually stretches out, if there being other node to place on grid N, and can only
On grid N+1, examination is put, till examination is put successfully.
Wherein, described node is the logical block of user's design.
During realizing the present invention, inventor finds at least to exist in prior art following technical problem:
Placing the situation of multiple node in the most same grid of above-mentioned initial layout, this is just
Make to legalize the overlong time of detection, and when there is above-mentioned situation, and existing local legalizes detection
Also the global optimum's result that can obtain in heavy damage initial layout.
Summary of the invention
The optimization method based on FPGA layout that the present invention provides, it is by judgement penalty mechanism, it is possible to will
Node in the higher grid of density is fast and effeciently diffused to periphery grid, thus obtains more excellent layout
Effect.
The present invention provides a kind of optimization method based on FPGA layout, including:
Step 1) described FPGA is divided into the grid that multiple size is identical, wherein, described grid sets
It is equipped with the rectangle decision box centered by the centre coordinate of described grid；
Step 2) according to company between place coordinate and each node described of each node in described FPGA
The relation that connects calculates gauze length wl；
Step 3) according to the interstitial content comprised in each grid, calculate the area density of each grid and incite somebody to action
The area density of described each grid carries out summation operation, to obtain area density and the des of all grids；
Step 4) structure cost function cost=wl+des, and use mathematical analysis method to described cost letter
Number solves, and obtains so that the initial layout coordinate of each node described during described cost function minimum；
Step 5) according to the initial layout coordinate of each node described and each node described within a grid
Rectangle decision box, obtains the adjustment coordinate of each node described；
Step 6) for the layout formed by the adjustment coordinate of each node described, according in each grid
The interstitial content comprised, calculates the area density of each grid and determines the density state of each grid；
Step 7) for by the layout that coordinate is formed that adjusts of each node described, repetition step 2) extremely
Step 4), until the ratio of previous cost function minimum and current cost function minimum is at preset range
Terminate time interior, to obtain the optimization layout coordinate of each node described, wherein, the optimization of each node described
Layout coordinate is the coordinate of each node described corresponding to described current cost function minimum；
Wherein, the logical block during described node is described FPGA.
Alternatively, the described grid that described FPGA is divided into multiple size identical includes:
Variable step mode is used by stages described FPGA to be divided into the grid that multiple size is identical.
Alternatively, the initial layout coordinate of each node described in described basis and each node place grid described
In rectangle decision box, the adjustment coordinate obtaining each node described includes:
Judge the initial layout coordinate of present node be whether its in rectangle decision box within a grid；
If the initial layout coordinate of described present node be positioned at its rectangle decision box within a grid, then
Using the centre coordinate of described present node place grid as the adjustment coordinate of described present node；
If the initial layout coordinate of described present node be positioned at its outside rectangle decision box within a grid, then
On the initial layout coordinate of described present node, one random value of superposition, obtains the random of described present node
Layout coordinate, and judge arbitrary placement's coordinate of described present node whether be positioned at its rectangle within a grid
In decision box, if arbitrary placement's coordinate of described present node is positioned at the rectangle decision box of its place grid,
Then using the centre coordinate of described present node place grid as the adjustment coordinate of present node, work as if described
Arbitrary placement's coordinate of front nodal point is positioned at outside the rectangle decision box of its place grid, then retain described present node
Initial layout coordinate as the adjustment coordinate of described present node.
Alternatively, described density state includes undersaturated condition, saturation and over-saturation state, described deficient
Saturation represents can also place node in current grid, wherein, described saturation represents current grid
In can not place node again, at least one node in described over-saturation state representation current grid need place
In the adjacent mesh that can also place node of described current grid.
The optimization method based on FPGA layout that the embodiment of the present invention provides, is divided into many by described FPGA
The grid that individual size is identical, and calculate gauze length and area density and；Structure is by described gauze length dough-making powder
Long-pending density and the cost function of composition, and when using mathematical analysis method to obtain so that described cost function minimum
The initial layout coordinate of each node described；Initial layout coordinate according to each node described and described respectively
Individual node rectangle decision box within a grid, obtain the adjustment coordinate of each node described；For by described
The layout that the adjustment coordinate of each node is formed, calculates the area density of each grid and determines each grid
Density state, and again described cost function is solved, when obtaining so that described cost function minimum
The optimization layout coordinate of each node described.Compared with prior art, its each joint in described FPGA
On the basis of the initial layout coordinate of point, devise a kind of decision mechanism based on rectangle decision box so that occur
During the higher grid of density, it is possible to fast and effeciently the node in this grid is spread to periphery grid, thus
The layout effect more being had.
Accompanying drawing explanation
Fig. 1 is the schematic diagram detected that legalizes in prior art；
The flow chart of Fig. 2 one embodiment of the invention optimization method based on FPGA layout；
Fig. 3 is the distribution schematic diagram of the initial layout coordinate of each node in the described FPGA in above-mentioned enforcement；
Fig. 4 is area ratio in the adjustment coordinate process obtaining each node in described FPGA in above-described embodiment
Calculation schematic diagram.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with the present invention
Accompanying drawing in embodiment, is clearly and completely described the technical scheme in the embodiment of the present invention, it is clear that
Described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on this
Embodiment in bright, the institute that those of ordinary skill in the art are obtained under not making creative work premise
There are other embodiments, broadly fall into the scope of protection of the invention.
The present invention provides a kind of optimization method based on FPGA layout, as in figure 2 it is shown, described method includes:
S11, described FPGA is divided into the grid that multiple size is identical.
Wherein, described grid is provided with the rectangle decision box centered by the centre coordinate of described grid.
S12, close according to connection between place coordinate and each node described of each node in described FPGA
System calculates gauze length wl.
Wherein, the logical block during described node is described FPGA.
Such as, described calculating gauze length wl can use semi-perimeter algorithm, but is not limited to this, wherein,
The semi-perimeter of a length of minimum rectangle comprising all nodes in gauze of described half cycle:
Wherein, e represents the region of all grid protocol, viAnd vjRepresent node i and node j respectively, node i
Coordinate is (xi,yi), the coordinate of node j is (xj,yj)。
S13, according to the interstitial content comprised in each grid, calculate the area density of each grid and by described
The area density of each grid carries out summation operation, to obtain area density and the des of all grids.
Wherein, the area density of grid can so calculate, but is not limited to this:
S14, structure cost function cost=wl+des, and use mathematical analysis method that described cost function is entered
Row solves, and obtains so that the initial layout coordinate of each node described during described cost function minimum.
S15, according to the initial layout coordinate of each node described and each node described rectangle within a grid
Decision box, obtains the adjustment coordinate of each node described.
S16, for being adjusted the layout that formed of coordinate by each node described, comprise according in each grid
Interstitial content, calculate the area density of each grid and determine the density state of each grid.
Wherein, described density state includes that undersaturated condition, saturation and over-saturation state, described owing are satisfied
With state representation current grid can also be placed node, described saturation represents can not be again in current grid
Placing node, at least one node in described over-saturation state representation current grid needs to be positioned over described working as
In the adjacent mesh that can also place node of front grid.
Such as, the density state of the area density grid less than 0.8 is set to undersaturated condition, area is close
The density state of degree grid between 0.8 and 1.2 is set to saturation, by area density more than 1.2
The density state of grid be set to over-saturation state.
S17, for being adjusted the layout that formed of coordinate by each node described, repeat S12 to S14, directly
To the ratio of previous cost function minimum and current cost function minimum in preset range time terminate,
To obtain the optimization layout coordinate of each node described, wherein, the optimization layout coordinate of each node described is
The coordinate of each node described corresponding to described current cost function minimum.
Wherein, described preset range is to be determined based on step-length when described FPGA is divided into multiple grid.
The optimization method based on FPGA layout that the embodiment of the present invention provides, is divided into many by described FPGA
The grid that individual size is identical, and calculate gauze length and area density and；Structure is by described gauze length dough-making powder
Long-pending density and the cost function of composition, and when using mathematical analysis method to obtain so that described cost function minimum
The initial layout coordinate of each node described；Initial layout coordinate according to each node described and described respectively
Individual node rectangle decision box within a grid, obtain the adjustment coordinate of each node described；For by described
The layout that the adjustment coordinate of each node is formed, calculates the area density of each grid and determines each grid
Density state, and again described cost function is solved, when obtaining so that described cost function minimum
The optimization layout coordinate of each node described.Compared with prior art, its each joint in described FPGA
On the basis of the initial layout coordinate of point, devise a kind of decision mechanism based on rectangle decision box so that occur
During the higher grid of density, it is possible to fast and effeciently the node in this grid is spread to periphery grid, thus
The layout effect more being had.
Alternatively, the described grid that described FPGA is divided into multiple size identical includes:
Variable step mode is used by stages described FPGA to be divided into the grid that multiple size is identical.
From step S15, the adjustment of each node location is that the size with grid has relation, if grid
Dividing too much, inaccuracy when mesh-density can be caused to calculate, because some node has only taken up string or
Row grid, interstitial content is unbalanced；If stress and strain model obtains too small, the calculating of described cost function can be caused
Amount is big, the problem that result does not restrains.Based on above-mentioned consideration, the stress and strain model for described FPGA can be adopted
Carry out stage by stage by variable step mode, such as, can use following dividing mode:
1) mode using step-length to be 9 units in the elementary step carries out stress and strain model.
Specifically, the stress and strain model mode keeping step-length to be 9 units, cycle calculations cost function is until expiring
The previous cost function value of foot be after more than 10 times of cost function value once time jump out the net in elementary step
Lattice divide, and transfer the stress and strain model of second stage to.
2) step-length is used to be 3 units or 6 units carry out stress and strain model in second stage.
Specifically, the stress and strain model mode keeping step-length to be 3 units or 6 units, cycle calculations generation
Valency function is until meeting after previous cost function value is 1 times of cost function value once with up to 10 times
Jump out the stress and strain model of second stage time following, and transfer the stress and strain model of phase III to.
2) step-length is used to be 1 unit or 2 units carry out stress and strain model in the phase III.
Specifically, the stress and strain model mode keeping step-length to be 1 unit or 2 units, cycle calculations generation
Valency function is until jumping out when meeting after previous cost function value is less than 1 times of cost function value once
The stress and strain model of phase III, to obtain final stress and strain model result.
Wherein, described 1 unit represents that in FPGA, minimum logical block occupied area is converted into foursquare
The length of side.
Further, the initial layout coordinate of each node described in described basis and each node place net described
Rectangle decision box in lattice, the adjustment coordinate obtaining each node described includes:
Judge the initial layout coordinate of present node be whether its in rectangle decision box within a grid；
If the initial layout coordinate of described present node be positioned at its rectangle decision box within a grid, then
Using the centre coordinate of described present node place grid as the adjustment coordinate of described present node；
If the initial layout coordinate of described present node be positioned at its outside rectangle decision box within a grid, then
On the initial layout coordinate of described present node, one random value of superposition, obtains the random of described present node
Layout coordinate, and judge arbitrary placement's coordinate of described present node whether be positioned at its rectangle within a grid
In decision box, if arbitrary placement's coordinate of described present node is positioned at the rectangle decision box of its place grid,
Then using the centre coordinate of described present node place grid as the adjustment coordinate of present node, work as if described
Arbitrary placement's coordinate of front nodal point is positioned at outside the rectangle decision box of its place grid, then retain described present node
Initial layout coordinate as the adjustment coordinate of described present node.
As it is shown on figure 3, be the distribution schematic diagram of the initial layout coordinate of each node in described FPGA,
Wherein, the grid that empty wire frame representation divides, the solid box in dotted line frame represents rectangle decision box, hollow
Circle represents the centre coordinate of grid respectively, and solid rim represents node, and the most described node on behalf user sets
The logical block of meter.Problem for convenience of description, it is assumed here that grid be the length of side be the square of H, accordingly
Ground, rectangle decision box can be the length of side be the square of 3*H/5.
Below in Fig. 3 as a example by grid 1, illustrate the present invention obtains (the i.e. node 1 of each node in grid 1
With node 2) adjustment coordinate:
From the grid 1 of Fig. 3, node 1 is positioned at the rectangle decision box in grid 1, then by grid 1
Centre coordinate as the adjustment coordinate of node 1；Node 2 is positioned at outside the rectangle decision box in grid 1, this
Time, need one random value of superposition on the position coordinate of node 2, obtain the arbitrary placement of node 2
Coordinate, and the rectangle decision box whether arbitrary placement's coordinate of decision node 2 again is positioned in grid 1,
If it is, using the centre coordinate of grid 1 as the adjustment coordinate of node 2, if it does not, i.e. node 2
Arbitrary placement's coordinate is positioned at outside the rectangle decision box in grid 1, then retain the original position of node 2, i.e. node 2
To remain as its initial layout coordinate constant in position.Now, the area of node 2 is proportionally assigned to accordingly
Grid in, such as the area ratio during node 2 is assigned to grid 4 is (as shown in Figure 4):
As can be seen here, for the node in rectangle decision box, unless the node density in grid is the highest, otherwise
It is placed on the center of grid as far as possible；For the node outside rectangle decision box, owing to it may be moved
Can also place in the adjacent mesh of node to other, the area of such node also can be according to distance proportion at it
He is allocated in network so that the probability of layout to each grid all can embody, and add each grid
Cost, thus the layout effect more being had.
One of ordinary skill in the art will appreciate that all or part of flow process realizing in above-described embodiment method,
Can be by computer program and complete to instruct relevant hardware, described program can be stored in a calculating
In machine read/write memory medium, this program is upon execution, it may include such as the flow process of the embodiment of above-mentioned each method.
Wherein, described storage medium can be magnetic disc, CD, read-only store-memory body (Read-Only Memory,
Or random store-memory body (Random Access Memory, RAM) etc. ROM).
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is not limited to
This, any those familiar with the art, in the technical scope that the invention discloses, can readily occur in
Change or replacement, all should contain within protection scope of the present invention.Therefore, protection scope of the present invention
Should be as the criterion with scope of the claims.
Claims (4)
1. an optimization method based on FPGA layout, it is characterised in that described method includes:
Step 1) described FPGA is divided into the grid that multiple size is identical, wherein, described grid sets
It is equipped with the rectangle decision box centered by the centre coordinate of described grid；
Step 2) according to company between place coordinate and each node described of each node in described FPGA
The relation that connects calculates gauze length wl；
Step 3) according to the interstitial content comprised in each grid, calculate the area density of each grid and incite somebody to action
The area density of described each grid carries out summation operation, to obtain area density and the des of all grids；
Step 4) structure cost function cost=wl+des, and use mathematical analysis method to described cost letter
Number solves, and obtains so that the initial layout coordinate of each node described during described cost function minimum；
Step 5) according to the initial layout coordinate of each node described and each node described within a grid
Rectangle decision box, obtains the adjustment coordinate of each node described；
Step 6) for the layout formed by the adjustment coordinate of each node described, according in each grid
The interstitial content comprised, calculates the area density of each grid and determines the density state of each grid；
Step 7) for by the layout that coordinate is formed that adjusts of each node described, repetition step 2) extremely
Step 4), until the ratio of previous cost function minimum and current cost function minimum is at preset range
Terminate time interior, to obtain the optimization layout coordinate of each node described, wherein, the optimization of each node described
Layout coordinate is the coordinate of each node described corresponding to described current cost function minimum；
Wherein, the logical block during described node is described FPGA.
Method the most according to claim 1, it is characterised in that described described FPGA is divided into many
The grid that individual size is identical includes:
Variable step mode is used by stages described FPGA to be divided into the grid that multiple size is identical.
Method the most according to claim 1, it is characterised in that at the beginning of each node described in described basis
Beginning layout coordinate and each node described rectangle decision box within a grid, obtain the tune of each node described
Whole coordinate includes:
Judge the initial layout coordinate of present node be whether its in rectangle decision box within a grid；
If the initial layout coordinate of described present node be positioned at its rectangle decision box within a grid, then
Using the centre coordinate of described present node place grid as the adjustment coordinate of described present node；
If the initial layout coordinate of described present node be positioned at its outside rectangle decision box within a grid, then
On the initial layout coordinate of described present node, one random value of superposition, obtains the random of described present node
Layout coordinate, and judge arbitrary placement's coordinate of described present node whether be positioned at its rectangle within a grid
In decision box, if arbitrary placement's coordinate of described present node is positioned at the rectangle decision box of its place grid,
Then using the centre coordinate of described present node place grid as the adjustment coordinate of present node, work as if described
Arbitrary placement's coordinate of front nodal point is positioned at outside the rectangle decision box of its place grid, then retain described present node
Initial layout coordinate as the adjustment coordinate of described present node.
Method the most according to claim 1, it is characterised in that described density state includes undersaturation shape
State, saturation and over-saturation state, described undersaturated condition represents can also place node in current grid,
Described saturation represents can not place node again in current grid, described over-saturation state representation current grid
In at least one node need to be positioned in the adjacent mesh that can also place node of described current grid.
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| US10528695B1 (en) | 2018-07-27 | 2020-01-07 | International Business Machines Corporation | Integer arithmetic method for wire length minimization in global placement with convolution based density penalty computation |
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| CN112149376A (en) * | 2020-09-25 | 2020-12-29 | 无锡中微亿芯有限公司 | FPGA layout legalization method based on maximum flow algorithm |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10528695B1 (en) | 2018-07-27 | 2020-01-07 | International Business Machines Corporation | Integer arithmetic method for wire length minimization in global placement with convolution based density penalty computation |
| CN111259614A (en) * | 2018-11-15 | 2020-06-09 | 北京大学 | Design method for optimizing metal routing of fishbone clock tree |
| CN111259614B (en) * | 2018-11-15 | 2022-04-26 | 北京大学 | Design method for optimizing metal routing of fishbone clock tree |
| CN112131814A (en) * | 2020-09-25 | 2020-12-25 | 无锡中微亿芯有限公司 | FPGA layout legalization method utilizing regional re-layout |
| CN112149376A (en) * | 2020-09-25 | 2020-12-29 | 无锡中微亿芯有限公司 | FPGA layout legalization method based on maximum flow algorithm |
| CN112131814B (en) * | 2020-09-25 | 2021-12-10 | 无锡中微亿芯有限公司 | FPGA layout legalization method utilizing regional re-layout |
| CN112149376B (en) * | 2020-09-25 | 2022-02-15 | 无锡中微亿芯有限公司 | FPGA layout legalization method based on maximum flow algorithm |
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| CN106021722B (en) | 2018-11-20 |
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