CN107967372B

CN107967372B - FPGA (field programmable Gate array) overall layout legalization method

Info

Publication number: CN107967372B
Application number: CN201610914808.XA
Authority: CN
Inventors: 王似飞; 李佐渭; 沈磊; 翟四通; 吴昌
Original assignee: Shanghai Fudan Microelectronics Group Co Ltd
Current assignee: Shanghai Fudan Microelectronics Group Co Ltd
Priority date: 2016-10-20
Filing date: 2016-10-20
Publication date: 2021-05-28
Anticipated expiration: 2036-10-20
Also published as: CN107967372A

Abstract

A legalization method for FPGA overall layout includes firstly legalizing macro module by means of integer programming and network flow, then legalizing standard unit with constraint by means of hierarchical integer programming, and finally legalizing standard unit without constraint by means of hierarchical network flow. The invention carries out legalization operation under the condition of destroying the overall layout result as little as possible by carrying out legalization on the unit modules with different types and different constraints in a grading way and moving units in a small range, thereby ensuring the effectiveness of the overall layout, reducing the damage of the legalization to the overall layout by reducing the local crowding degree, easily expanding the legalization frame by a grading way and obviously improving the legalization layout efficiency.

Description

FPGA (field programmable Gate array) overall layout legalization method

Technical Field

The invention relates to the Field of integrated circuit design, in particular to a Field Programmable Gate Array (FPGA) overall layout legalization method.

Background

The FPGA adopts a concept of a Logic Cell array lca (Logic Cell array), and includes a configurable Logic module clb (configurable Logic block), an input Output module iob (input Output block), and an internal connection (Interconnect). A Field Programmable Gate Array (FPGA) is a programmable device that has a different structure than conventional logic circuits and gate arrays (e.g., PAL programmable array logic, GAL gate array logic, and CPLD complex programmable logic devices). The FPGA utilizes small lookup tables (16 × 1 RAM) to realize combinational logic, each lookup table is connected to the input end of a D flip-flop, and the flip-flops drive other logic circuits or drive I/O (input/output) circuits, so that basic logic unit modules capable of realizing both combinational logic functions and sequential logic functions are formed, and the modules are connected with each other or connected to an I/O (input/output) module by utilizing metal connecting wires. The logic of the FPGA is implemented by loading programming data into the internal static memory cells, the values stored in the memory cells determine the logic function of the logic cells and the connection between the modules or between the modules and the I/O and finally the functions that the FPGA can implement, the FPGA allowing an unlimited number of programming.

The typical FPGA development process generally includes main steps of function definition, device model selection, design input, function simulation, comprehensive optimization, post-comprehensive simulation, layout, wiring, post-simulation, board-level simulation, chip programming and debugging, and the like.

As shown in fig. 1, the position of the placement in the physical Design of the whole chip is shown, the input of the placement is the netlist information after packaging, the Constraint information of the chip and the Constraint information customized by the User, including the physical constraints written in the User Constraint File (UCF for short) and the delay constraints written in the new thought technology Design Constraint File (SDC for short), and the output is the netlist after placement for the automatic router to route.

As shown in fig. 2, the automated layout of the FPGA chip comprises the following steps: input-output layout, global clock layout, initial layout, overall layout, legal layout and detailed layout.

Input and output layout: and an input/output module in the circuit is placed, all IOBs are randomly placed at specified positions according to physical constraints (voltage, level and the like) of the chip, namely an integer programming problem is constructed, the optimal input/output layout is obtained by solving the integer programming problem, and if the optimal solution cannot be obtained, related errors are reported.

Clock layout: if the number of the clock nets used by the circuit is more than the number of different clocks supported by each clock area, the unit modules driven by the clock nets need to be pre-distributed in position, and the unit modules are distributed in the designated clock area, so that the clock nets of the whole circuit are not crowded, and the router can be smoothly carried out.

Initial layout: and constructing a target constraint problem of the length of a secondary line according to the position of the output module and the constraint of a clock area, and solving the target constraint problem by adopting a conjugate gradient method of pre-optimization treatment, namely obtaining the initial positions of all unit modules, wherein the initial positions do not depend on the initial solution of the layout, so that the layout with the shortest line length is obtained.

Overall layout: and constructing a target constraint problem similar to a half perimeter according to the initial positions of all the unit modules and the topological connection of the circuit, solving by adopting a conjugate gradient method based on a mixed step length adjusting strategy, and distributing the unit modules in a whole manner by aiming at the modules of different levels, the layout state and a calculation mode for dynamically adjusting the step length. After the overall layout, the overall distribution of the unit modules is quite uniform, but there are locally overlapping unit modules.

Legal layout: after the overall layout, the unit modules are distributed relatively uniformly on the whole FPGA chip, but the unit modules are still floating point coordinates, the unit modules are moved to positions of legal integers in a short distance, so that the unit modules are not overlapped, and the positions to which the units are moved are compatible with the type of the unit, which is a necessary step after the overall layout.

Detailed layout: the overall layout does not guarantee the optimality of the local part, and the legal layout further destroys the optimal solution of the local part, so that detailed layout is required to make up for the damage of the local layout caused by the previous two steps. The detailed layout is based on a low-temperature simulated annealing method, two unit modules are moved or exchanged in a close distance, and the layout of a local area is optimized.

After each part of layout, the state of the current layout can be measured, and if the current layout is found to be incapable of continuing to execute another part, the previous part needs to be returned, and the whole layout flow is readjusted and executed.

Layout is a relatively time-consuming step in the whole process, which reasonably configures the hardware primitives and the bottom layer cells in the logic netlist to the inherent hardware structure inside the chip, and often needs to choose between optimal speed and optimal area. At present, the size of an FPGA is getting bigger and bigger, the structure is getting more and more complex, wherein the types of logic unit modules are getting more and more, and include large logic units such as a DSP and a RAM, and the routing between some units is fixed connection, such as a carry chain (carry chain) and a shift register (shift register), which all limit the random placement of the logic units, especially when there is a timing constraint condition, because the layout plays a decisive role in the speed of the FPGA layout, the timing constraint is taken into consideration during the layout process, otherwise, the timing constraint is difficult to be satisfied by the optimization of subsequent routing and the like. Therefore, how to quickly and effectively carry out automatic layout plays a crucial role in FPGA layout design. In order to accelerate the efficiency of the automatic layout software, the global optimization is carried out by adopting an overall layout mode, but the overall layout result is not legal layout, so a step of legal operation is added after the overall layout. The quality of legalization has a great influence on the result of layout, and especially when a locally crowded area exists after the overall layout, the unreasonable legalization easily causes large-scale movement of the unit modules, which violates the overall layout and cannot well join the result of the overall layout.

Disclosure of Invention

The invention provides a legalization method for FPGA (field programmable gate array) overall layout, which is used for legalizing unit modules with different types and different constraints through hierarchical processing and carrying out legalization operation under the condition of destroying an overall layout result as little as possible through small-range unit movement so as to ensure the effectiveness of the overall layout.

In order to achieve the above object, the present invention provides a method for legalizing an overall layout of an FPGA, comprising the steps of:

step S1, legalizing the macro module by adopting an integer programming and network flow mode;

the macro module has sparse resources and has a relatively long distance between legal positions;

step S2, legalizing the restricted standard cell by adopting a hierarchical integer programming mode;

the standard unit with the constraint is a standard unit module which occupies more resources and has relative position constraint;

and step S3, legalizing the unconstrained standard cell in a hierarchical network flow mode.

In step S1, while performing the overall layout, the macro block is legal by using integer programming and network flow.

In step S2, the method for legalizing the constrained standard cell in the hierarchical integer programming manner specifically includes the following steps:

step S2.1, dividing the chip into a plurality of columns, and moving the standard unit to the nearest column in the horizontal direction;

the columns can comprise a column of grids and can also comprise a plurality of columns of grids;

the number of standard cells in each column should be less than or equal to the capacity of the column;

s2.2, moving the standard cells of two adjacent columns by a greedy method to reduce the local crowding degree in the columns;

step S2.3, the standard units in each column are moved to the nearest type compatible position in the vertical direction;

the number of standard cells in each location should be less than or equal to the capacity of the location.

In step S3, the method for validating unconstrained standard cells by using hierarchical network flows includes the following steps:

s3.1, dividing the chip into a plurality of windows, solving the MFC problem by adopting a network flow simplex method to obtain the coordinates of the windows corresponding to the standard units, and moving the standard units into each window;

the window comprises a plurality of grids;

and S3.2, solving the optimal matching problem of the bipartite graph by adopting a network flow simplex method or a Hungarian algorithm, and moving the standard cells in each window to the matched position.

When the macro block is also constrained, it legalizes the constrained macro block in a hierarchical integer program manner as described in step S2, and when the macro block is unconstrained, it legalizes the unconstrained macro block in a hierarchical network flow manner as described in step S3.

Relative position constraints encompass two broad categories: one type is a user-specified display constraint and the other type is a chip-related implicit constraint, the units of each type of constraint together constituting a large macroblock.

Constructing the user-specified display constraints into a sparse macroblock to handle:

specification of relative positions of standard cells of the same type: the adopted coordinate system is a coordinate system corresponding to the local type;

specification of relative positions of heterogeneous standard cells: the coordinate system used can only be the global coordinate system RPM.

The implicit constraints associated with the chip are translated into dense macroblock processing.

And after the legalization operation in each step is finished, judging whether the legalization operation fails or not, if not, performing the next step, if so, readjusting the parameters and re-executing the legalization of the current step if the failure times are less than the specified times, and if the failure times are more than or equal to the specified times, restarting the whole legalization process.

The invention has the following advantages:

1. by reducing the degree of local congestion, the damage to the overall layout caused by legalization is reduced.

2. The legalization framework is easily extended by means of a hierarchy.

3. The efficiency of legal layout is obviously improved.

Drawings

Fig. 1 is a diagram showing a positional relationship of a layout in the entire chip physical design in the related art.

FIG. 2 is a flowchart of the steps of the automated layout of a prior art FPGA chip.

FIG. 3 is a flowchart of a method for legalizing an overall FPGA layout according to the present invention.

FIG. 4 is a hierarchical schematic of the legalization of constrained elements.

FIG. 5 is a schematic diagram of the division of an unconstrained standard cell chip window.

FIG. 6 is a schematic diagram of the type of relative position constraint.

FIG. 7 is a schematic diagram showing relative position constraints.

FIG. 8 is a schematic diagram of implicit relative position constraints.

Detailed Description

The preferred embodiment of the present invention will be described in detail below with reference to fig. 3 to 8.

The legal layout plays a role in starting and stopping in the whole layout process and is a necessary way for converting illegal layout into legal layout. After the overall layout, the coordinates of the unit module are floating point values, and the coordinates of the positions (Site) where the units can be placed on the chip are integer values, so that the coordinates of the unit module are rounded, which is similar to the processing operation defined by branches. So, in essence, a legal layout is a problem for integer programming. But run time is not allowed if solved with the general integer-programmed solver, and grows exponentially as the problem grows in size.

As shown in fig. 3, the present invention provides a method for legalizing an overall layout of an FPGA, comprising the following steps:

the macro module has sparse resources and relatively long distance between legal positions, and comprises a Digital Signal Processor (DSP), a Random Access Memory (RAM), a unit module with very tight constraint and the like;

after each legalization macro module, judging whether the legalization operation fails, if not, performing step S2, if so, further judging the failure times, if the legalization failure times are less than the designated times, performing step S1 again, and if the legalization failure times are more than or equal to the designated times, performing step S1 again;

the standard unit with the constraint is a standard unit module which occupies more resources and has a relative position (RLOC) constraint;

after the standard cells with the constraints are legalized each time, judging whether the legalization operation fails, if not, performing step S3, if so, further judging the failure times, if the legalization failure times are less than the specified times, readjusting parameters (including adjusting priorities of different constraints, the range of positions where each standard cell can be placed and the like), performing step S2 again, and if the legalization failure times are more than or equal to the specified times, performing step S1 again;

step S3, legalizing the unconstrained standard cell by adopting a hierarchical network flow mode;

after each time of legalizing the unconstrained standard cell, judging whether the legalization operation fails, if not, finishing the legalization, if fails, further judging the failure times, if the legalization failure times is less than the specified times, readjusting parameters (including adjusting hierarchical levels, dividing modes of windows after the classification, and the like), and performing the step S3 again, and if the legalization failure times is more than or equal to the specified times, performing the step S1 again.

When the legalization failure of each small step is less than the designated times, the parameters are readjusted, the legalization of the current step is executed again, and when the legalization times of each small step are more than or equal to the designated times, the whole legalization process is restarted, so that the legal layout is ensured to be obtained or corresponding error information is reported.

In the step S1, while performing the overall layout, the macro block is validated by using an integer programming and network flow method, and the macro block is fixed in advance to prevent the fluctuation of the layout result caused by the discontinuity of the resources.

The macro module legalization legalizes the unit modules with complex DSP, RAM and physical constraints (describing the constraints of the module itself or the relative positions of other modules), the DSP and RAM are sparsely distributed on the whole chip, and are less than the CLB, and a row of DSP or RAM is relatively far away from the adjacent DSP or RAM, so that the moving range of the DSP and RAM units from one legal position to the other legal position is relatively large, and in order to prevent the DSP and RAM units from moving in a large range after the overall layout from affecting the layout, the invention fixes the DSP and RAM units after the first rounds of the overall layout are finished, and prevents the rear layout from causing a bumping phenomenon.

In step S2, a hierarchical integer programming method is used to legalize the standard cell with constraints, and in the whole layout process, the relative position constraint is an especially intractable constraint, and when there are many such constraints, it is easy to cause a local unsolved constraint. Layout legalization is the problem that a small-amplitude mobile unit puts the layout constraint at a legal position under the condition that the layout constraint is met, and the essence is integer programming. As the integer programming problem is increased along with the increase of scale and the solving time exponential level is increased, when more unit modules are used, the solving efficiency is greatly reduced, so that the current framework adopts a hierarchical integer programming model, is divided into a horizontal direction and a vertical direction, and is respectively optimized from the X direction and the Y direction.

Fig. 4 is a schematic diagram of a hierarchy of legalization of a constrained unit, and the method for legalizing a constrained standard unit by using a hierarchical integer programming specifically includes the following steps:

the columns can comprise a column of grids (Tile) and can also comprise a plurality of columns of grids; as shown in fig. 4, the grid (Tile) is a two-dimensional grid structure, one CLB is a Tile, one DSP is also a Tile, and each column of grids (Tile) forms a Col;

in the stage, all standard units can only move in the horizontal direction, the target positions of the standard units are divided columns, so that an integer programming problem can be constructed, the target equation is that the cost of all standard units moving horizontally is minimum, the constraint is that all standard units move to the corresponding columns, and the capacity of each type of standard unit in each column cannot exceed that of the column;

after the standard cells are distributed to each row, although the standard cells meet the constraint of the capacity of the row, the height of each row is very high, so that the crowdedness of a local area in the row is high, and the crowdedness of an adjacent row is low, so that the two adjacent rows are simply moved by a greedy method, the local crowdedness is further reduced, the standard cells are driven to move in a small range by reducing the crowdedness, and the overall layout result is ensured;

the number of standard cells in each location should be less than or equal to the capacity of the location;

the standard cells in each column are legalized, which is still a problem of integer programming, the optimization goal is that the standard cells move vertically with minimum cost, the constraint is that all standard cells move to the corresponding positions inside the Tile, and the standard cells in each position cannot exceed the capacity of the position and are compatible with the type of the position.

By adopting the hierarchical legalization strategy, the scale of the integer programming problem is greatly reduced, so that the time for branching and delimiting is reduced, and the legalization of the module with the constraint unit is accelerated.

In step S3, the unconstrained standard cell is legalized in a hierarchical network flow manner, the integer programming problem is solved at a slower speed with an increase in scale, and the unconstrained standard cell occupies a large proportion of the whole circuit, so the legalization of the unconstrained standard cell is solved in a network flow manner.

The method for legalizing the unconstrained standard cell in the hierarchical network flow mode comprises the following steps:

s3.1, dividing the chip into a plurality of windows (windows), solving the MFC problem by adopting a network flow simplex method to obtain the coordinates of the windows corresponding to the standard units, and moving the standard units into each Window;

the window comprises a plurality of Tiles, and in the embodiment, the size of each window is equivalent to the size of dozens of Tiles to dozens of Tiles;

as shown in fig. 5, the diagram is a schematic diagram of window division of an unconstrained standard cell chip, after the overall layout, it can only be ensured that the global cell module distribution is uniform, but there still exist some crowded areas, and when the chip utilization rate is high, the effect on the algorithm efficiency is relatively large by performing the legalization on all the standard cells together, so that each standard cell is locally allocated to each window first by adopting a network flow manner, and it is ensured that the standard cell allocated to a specific window can be placed in the current window;

the problem that the cell modules are distributed in each window can be simulated into an MFC (micro-fuel cell), all windows and all cells form all nodes on the problem of the MFC, all the nodes have capacity constraints, and an edge exists between each cell and a window which can be placed to represent the cost of placing the cell into a corresponding window; the MFC problem can be solved by a network flow simplex method to obtain the coordinates of windows corresponding to all units, the solution idea of the network flow simplex method is to transform from one comprehension to another comprehension, and an optimal solution is obtained by finite transformation; the MCF problem is that a spanning tree is constructed, an edge which can reduce cost is selected from edges which are not on the spanning tree and added into the spanning tree, one more edge is added, the original spanning tree can be made to form a ring inevitably, then the capacity of each edge is adjusted, key edges on the ring are deleted (edges which can not increase or reduce Flow) so that the solution of the MCF problem can be obtained through finite times of spanning tree transformation;

s3.2, solving the optimal matching problem of the bipartite graph by adopting a network flow simplex method or a Hungarian algorithm, and moving the standard cells in each window to a matching position;

after all the units are distributed on the window, further legalization operation can be carried out on the units in the window, at this time, the problem of MCF can be constructed according to the method of the step S3.1, each standard unit and all the positions are nodes in the MFC, each node is marked with capacity constraint, an edge exists between each standard unit and each legal position, the edge is marked with the cost of the standard unit moving to the corresponding position, and the legal layout can be obtained by solving through a network flow simplex method or a Hungarian algorithm;

the hungarian algorithm mainly solves the optimal matching problem of bipartite graphs, the problem of the step S3.2 is also the bipartite graph matching problem, all standard units are matched with positions, the main idea is to constantly search an augmentation path to increase matching edges and matching points in matching or reduce matching cost, and after a limited step, when the augmentation path cannot be found, the optimal matching is achieved, namely legal layout is obtained.

The invention supports legalization of macro modules with constraints or standard units with constraints and supports constraint of relative positions between unit modules.

The relative position constraint (RLOC) is a particularly intractable constraint during the whole layout, which easily causes a local unsolvation when there are many such constraints. As shown in fig. 6, the relative position constraint includes two categories, one is a display constraint specified by a user and defined in the UCF file by the user, and the other is a chip-related implicit constraint and a physical constraint implicitly existing according to the internal structure of the chip, and the units of each constraint together form a large macroblock.

The user-specified display constraints are constructed into a sparse macroblock (a sparse macroblock due to the possible holes in the middle of the macroblock): the display constraints specified by the user are all specified through the UCF file, describe the relative relationship of the positions of a group of standard units, can specify the relative relationship of the positions of the standard units of the same type, and can also specify the relative relationship of the positions of the standard units of different types.

Specification of relative positions of standard cells of the same type: the coordinate system used is that corresponding to local type, the IOB type has IOB legal position, such as IOB _ X1Y2, SLICEL and SLICEM correspond to SLICE coordinate system, such as SLICX 8Y9, and the rest types are similar.

Specification of relative positions of heterogeneous standard cells: when specifying the relative positions between different types of cells, only a global coordinate system RPM can be used, e.g. the global positions of cell DSP and cell SLICE are specified as RPM _ X8Y9 and RPM _ X9Y10, which represent relative positions in both X and Y directions as 1.

As shown in fig. 7, the user defines an RLOC constraint shown in the UCF file, that is, the corresponding relationship between the placeable region RLOC _ RANGE of the whole constraint and the relative positions of 5 units, where the 5 units move, the deviation of the relative positions cannot be changed, and the outer boundary of the whole unit cannot exceed RLOC _ RANGE.

The chip-related implicit constraints are converted into dense macro-block (dense macro-block due to no holes in the middle of macro-block) processing: besides the specified relative position constraint displayed by the user, there is also a relative position constraint closely related to the chip structure, such as a shift register for implementing carry of accumulator, a Mux Tree for implementing carry, a RAM Chain for implementing random access memory, etc. As shown in fig. 8, a carry chain consisting of four units, which are cascaded by a plurality of COUT a CIN nets, must be placed next to each other in the vertical direction since the physical realization is that COUT a CIN Net can only be connected by one path. The implicit relative position constraint types are also more, and the types and relative positions of various types of constraint constituent units are different, but the implicit relative position constraint types can be converted into relative position constraints.

The legalization method for the FPGA overall layout provided by the invention has the advantages that the legalization of the unit modules with different types and different constraints is processed in a grading manner, the legalization operation is carried out under the condition of destroying the overall layout result as little as possible through the unit movement in a small range, and the effectiveness of the overall layout is ensured.

The invention has the following advantages:

2. The legalization framework is easily extended by means of a hierarchy.

3. The efficiency of legal layout is obviously improved.

While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.

Claims

1. A legalization method for FPGA overall layout is characterized by comprising the following steps:

the macro module has sparse resources and long distance between legal positions;

the window comprises a plurality of grids;

2. The method according to claim 1, wherein in step S1, while the whole layout is performed, the macro block is legal by means of integer programming and network flow.

3. The method of claim 1, wherein the relative position constraints comprise two broad categories: one type is a user-specified display constraint and the other type is a chip-related implicit constraint, the standard cells of each type of constraint together forming a large macroblock.

4. The method of claim 3, wherein the user-specified display constraints are structured into a sparse macroblock to handle:

5. The FPGA population layout legalization method of claim 3, in which chip-related implicit constraints are converted into dense macroblock processing.

6. The method according to claim 4 or 5, wherein after the legalization operation in each step is finished, it is determined whether the legalization operation has failed, if not, the next step is performed, if the failure number is less than the specified number, the parameters are readjusted, the legalization of the current step is re-executed, and if the failure number is greater than or equal to the specified number, the entire legalization process is restarted.