CN112130050B - IGBT desaturation fault detection device - Google Patents
IGBT desaturation fault detection device Download PDFInfo
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Abstract
The application discloses IGBT desaturation fault's detection device, including logic processing circuit, MOS pipe, first diode and the signal output circuit who is connected with signal channel. The logic processing circuit is connected with the signal channel and is used for outputting a switching-on control signal to a gate pole of the MOS tube when the pulse width modulation signal is at a low level and outputting a switching-off control signal to the gate pole of the MOS tube when the pulse width modulation signal is at a high level; the drain electrode of the MOS tube is connected with the anode of the first diode, and the source electrode of the MOS tube is grounded; the negative electrode of the first diode is connected with the C electrode of the IGBT to be detected, the positive electrode of the first diode is connected with the signal output circuit, and a high-level signal of the positive electrode of the first diode is used as a desaturation fault signal; and the signal output circuit is used for connecting the anode of the first diode with the protection processing unit of the IGBT to be detected through signals. According to the scheme, when the pulse width modulation signal is at a low level, the positive electrode of the diode for outputting the desaturation fault signal is forcibly pulled down through the MOS tube, so that the situation that false alarm cannot occur when the desaturation fault detection is carried out on the IGBT is ensured.
Description
Technical Field
The application relates to the field of electrical technology, more specifically to a detection device for IGBT desaturation fault.
Background
The IGBT normally works in a saturation region and a cut-off region, the IGBT is equivalent to the function of a switch, when the IGBT works in a protection region, Vce is low and changes slightly, when an external circuit is short-circuited, the current flowing between a C level and an E level of the IGBT can be increased to a certain degree, the IGBT can exit the saturation region and reenter a linear region, and when Vce suddenly changes greatly and a large Ice flows through, the loss of the IGBT can be known to be large through a power formula, and the IGBT can be burnt out quickly if not blocked in time. The general IGBT driving module is provided with a protection circuit for turning off the corresponding IGBT when desaturation occurs, so that the IGBT is prevented from being burnt. Of course, the key to desaturation protection of the IGBT is to find the desaturation in time. The inventor of the present application finds a desaturation detection circuit for detecting whether desaturation occurs to a corresponding IGBT through search, and the desaturation detection circuit is specifically shown in fig. 1.
The input signal PWM is transmitted to the secondary side through the optocoupler U2 ', the signal processing unit controls the on and off of the IGBT Q1', when a short circuit occurs to the Q1 'in the Q' conduction stage, the Q1 'is desaturated, the voltage of the C electrode of the Q1' rises to VBUS ', the diode D1' is cut off, the voltage of the A 'point rises to VDD and is higher than VREF, the output of the comparator U5' is turned over to show that desaturation fault occurs at the moment, fault reduction information is transmitted back to the protection processing unit through the protection signal processing circuit and the control optocoupler U1 ', and the protection processing unit timely protects the Q1'. In the Q1' turn-on stage, that is, when PWM is high, the voltage drop of VCE has a certain slope, the VCE drop time is about 1.85us, in the 1.85us, D1 is also in the cut-off state, in order to prevent the false alarm fault of the 1.85us, Q2 is required to be turned on in the 1.85us, and by configuring R6 and C1, Q2 is controlled to be turned off with a certain delay time (more than 1.85us), that is, U1 is ensured to be always in the light state, so as to prevent the false alarm fault, and the false alarm is not generated in a short period of the turn-on stage.
In the Q1 ' turn-off stage, the voltage of the C-electrode is VBUS ', the D1 ' is also cut off, the voltage of the a ' -point is VDD due to the pull-up, and is higher than VREF, and the output of the comparator U5 ' also flips, because at this time, a desaturation fault does not really occur, and the signal processing circuit needs to perform turn-off control on the protection signal processing circuit to avoid outputting fault information to the protection processing unit.
As can be seen from the above description, in the technical scheme, since the circuits need to handle more situations and have a complex structure, false alarm is very easy to occur, thereby affecting the normal operation of the IGBT.
Disclosure of Invention
In view of this, the present application provides a device for detecting a desaturation fault of an IGBT, which is used to avoid the occurrence of false alarm when the desaturation fault of the IGBT is effectively detected.
In order to achieve the above object, the following solutions are proposed:
the utility model provides a detection device that IGBT moves back saturation fault, is applied to and waits to detect the IGBT, wait to detect the IGBT and receive the pulse width modulation signal that control module output through the signal channel, detection device include with logic processing circuit, MOS pipe, first diode and the signal output circuit that the signal channel is connected, wherein:
the logic processing circuit is connected with the signal channel and is used for acquiring the pulse width modulation signal and the reverse pulse width modulation signal from the signal channel, outputting a conduction control signal to a gate pole of the MOS tube when the pulse width modulation signal is at a low level and outputting a cut-off control signal to the gate pole of the MOS tube when the reverse pulse width modulation signal is at a low level;
the drain electrode of the MOS tube is connected with the anode of the first diode, and the source electrode of the MOS tube is grounded;
the negative electrode of the first diode is connected with the C electrode of the IGBT to be detected, the positive electrode of the first diode is connected with the signal output circuit, and a high-level signal of the positive electrode of the first diode is used as a desaturation fault signal;
the input end of the signal output circuit is connected with the anode of the first diode, and the output end of the signal output circuit is connected with the protection processing unit of the IGB T to be detected through signals.
Optionally, the signal path includes a first optical coupler, a pull-up resistor, and an inverter, where:
the input end of the first optical coupler is used for receiving the pulse width modulation signal;
the emitter of the first optical coupler is grounded, and the collector of the first optical coupler is connected with one end of the pull-up resistor and used for outputting the reverse pulse width modulation signal;
the other end of the pull-up resistor is used for receiving a pull-up voltage;
the input end of the phase inverter is connected with the collector of the first optocoupler, the output end of the phase inverter is connected with the gate pole of the IGBT to be detected, and the output end of the phase inverter is also used for outputting the pulse width modulation signal.
Optionally, the logic processing circuit includes a first comparator, a first voltage dividing resistor, a second comparator, and an nor gate, where:
the inverting input end of the first comparator is used for receiving a first reference voltage, the non-inverting input end of the first comparator is connected with one end of the first voltage-dividing resistor and one end of the second voltage-dividing resistor, and the output end of the first comparator is connected with one input end of the nor gate;
the other end of the first voltage-dividing resistor is used for receiving a pull-up voltage;
the other end of the second voltage-dividing resistor is used for receiving the pulse width modulation signal output by the signal channel;
the inverting input end of the second comparator is used for receiving a second reference voltage, the non-inverting input end of the second comparator is used for receiving the inverse pulse width modulation signal output by the signal channel, and the output end of the second comparator is connected with the other input end of the NOR gate;
and the output end of the NOR gate is used for outputting the conduction control signal or the cut-off control signal.
Optionally, the output end of the nor gate is connected to the gate of the MOS transistor through a second diode, wherein:
the anode of the second diode is connected with the output end of the NOR gate, and the cathode of the second diode is connected with the gate pole of the MOS tube;
the second diode is connected with a first resistor in parallel.
Optionally, the gate of the MOS transistor is connected to the source thereof through a capacitor.
Optionally, the signal output circuit includes a second resistor, a third resistor, and a second optical coupler, where:
one end of the second resistor is connected with the anode of the first diode, and the other end of the second resistor is connected with the cathode of the input end of the second optocoupler;
the positive electrode of the input end of the second optocoupler is used for receiving driving voltage;
the collector of the second optical coupler is used as the output end of the signal output circuit and is connected with one end of the third resistor, and the emitter of the second optical coupler is grounded;
the other end of the third resistor is used for receiving a driving voltage.
According to the technical scheme, the IGBT desaturation fault detection device is applied to the IGBT to be detected, the IGBT to be detected receives the pulse width modulation signals output by the control module through the signal channel, and the detection device comprises a logic processing circuit, an MOS (metal oxide semiconductor) tube, a first diode and a signal output circuit, wherein the logic processing circuit, the MOS tube, the first diode and the signal output circuit are connected with the signal channel. The logic processing circuit is connected with the signal channel and is used for outputting a switching-on control signal to the gate pole of the MOS tube when the pulse width modulation signal is at a low level and outputting a switching-off control signal to the gate pole of the MOS tube when the reverse pulse width modulation signal is at a low level; the drain electrode of the MOS tube is connected with the anode of the first diode, and the source electrode of the MOS tube is grounded; the negative electrode of the first diode is connected with the C electrode of the IGBT to be detected, the positive electrode of the first diode is connected with the signal output circuit, and a high-level signal of the positive electrode of the first diode is used as a desaturation fault signal; the input end of the signal output circuit is connected with the anode of the first diode, and the output end of the signal output circuit is connected with the protection processing unit of the IGB T to be detected through signals. According to the scheme, when the pulse width modulation signal is at a low level, the positive electrode of the diode for outputting the desaturation fault signal is forcibly pulled down through the MOS tube, so that the situation that false alarm cannot occur when the desaturation fault detection is carried out on the IGBT is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a circuit diagram of an IGBT desaturation fault detection circuit;
fig. 2 is a schematic diagram of a detection apparatus for an IGBT desaturation fault according to an embodiment of the present application;
fig. 3 is a circuit diagram of a detection apparatus for an IGBT desaturation fault according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Examples
Fig. 2 is a schematic diagram of an inspection apparatus for IGBT desaturation failure according to an embodiment of the present application;
as shown in fig. 2, the detection device provided in the present embodiment is used to detect a rectified current using an IGBT or a desaturation fault of an IGBT element in an inverter circuit. The rectifying or inverting circuit is provided with a control module 100, the control module 100 outputs a control signal to a gate G of an IGBT element Q1 through a signal path 101, the control signal is a pulse width modulation signal, and the rectifying or inverting circuit is further provided with a protection processing unit 200 for protecting the IGBT when a desaturation fault occurs.
The detection device in the present embodiment includes a logic processing circuit 10, a MOS transistor Q2, a first diode D1, and a signal output circuit 20.
The logic processing circuit is connected with two output points connected with the signal channel, one output point is used for outputting a pulse width modulation signal, and the other output point is used for outputting an inverse pulse width modulation signal which is a signal with a completely opposite level to the pulse width modulation signal. The logic processing circuit is also provided with an output end which is connected with a gate pole of the MOS tube.
The drain electrode of the MOS tube is connected with the anode of the first diode, and the source electrode of the MOS tube is grounded. The cathode of the anode of the first diode is connected with the C pole of the IGBT to be detected. The input end of the signal output circuit is connected with the anode of the first diode, and the output end of the signal output circuit is connected with the protection processing unit.
The logic processing circuit is used for receiving the pulse width modulation signal and the reverse pulse width modulation signal output by the signal channel, and outputting a conduction control signal to a gate pole of the MOS tube when the pulse width modulation signal is at a low level, namely outputting the conduction control signal to the gate pole of the MOS tube when the IGBT to be detected is in a turn-off stage so as to control the MOS tube to ground the point A; when the reverse pulse width modulation signal is at low level, the logic processing circuit outputs a turn-off control signal to the gate pole of the MOS tube to turn off the MOS tube.
When the reverse pulse width modulation signal is at a low level, the pulse width modulation signal is at a high level, and the IGBT to be detected is in a conducting working state at the moment. At the moment, if the IGBT is in a saturation working area, the voltage of the first diode is the normal voltage drop of the IGBT to be detected, namely point A is grounded through the first diode, and point A is a low-level signal; if the IGBT to be detected is desaturated, the voltage between the CEs can rise to the VBUS voltage, the first diode is cut off reversely, the MOS tube is cut off at the same time, the A electric voltage is turned into a high-level signal, the high-level signal of the point A is taken as a desaturation fault signal, the desaturation fault signal is output to the protection processing unit through the signal output circuit, and the protection processing unit conducts desaturation protection on the IGBT to be detected.
According to the technical scheme, the device for detecting the IGBT desaturation fault is applied to the IGBT to be detected, the IGBT to be detected receives the pulse width modulation signal output by the control module through the signal channel, and the detecting device comprises a logic processing circuit, an MOS (metal oxide semiconductor) tube, a first diode and a signal output circuit, wherein the logic processing circuit, the MOS tube, the first diode and the signal output circuit are connected with the signal channel. The logic processing circuit is connected with the signal channel and is used for outputting a switching-on control signal to the gate pole of the MOS tube when the pulse width modulation signal is at a low level and outputting a switching-off control signal to the gate pole of the MOS tube when the reverse pulse width modulation signal is at a low level; the drain electrode of the MOS tube is connected with the anode of the first diode, and the source electrode of the MOS tube is grounded; the negative electrode of the first diode is connected with the C electrode of the IGBT to be detected, the positive electrode of the first diode is connected with the signal output circuit, and a high-level signal of the positive electrode of the first diode is used as a desaturation fault signal; the input end of the signal output circuit is connected with the anode of the first diode, and the output end of the signal output circuit is connected with the protection processing unit of the IGB T to be detected through signals. According to the scheme, when the pulse width modulation signal is at a low level, the positive electrode of the diode for outputting the desaturation fault signal is forcibly pulled down through the MOS tube, so that the situation that false alarm cannot occur when the desaturation fault detection is carried out on the IGBT is ensured.
In order to ensure that the signal channel transmits the pulse width modulation signal output by the control module to the IGBT to be detected, the signal channel comprises a first optical coupler U1, a pull-up resistor R11 and an inverter U2, as shown in fig. 3. The input end of the first optocoupler is used for connecting the output end of the control module and receiving the pulse width modulation signal output by the control module; the collector of the first optical coupler is connected with one end of a pull-up resistor and is also used for being connected with the input end of an inverter, the emitter of the first optical coupler is grounded, the other end of the pull-up resistor is used for receiving a pull-up voltage VDD, and the input end of the inverter is used for outputting a reverse pulse width modulation signal.
And the output end of the inverter is used for outputting the reverse pulse width modulation signal to perform reverse processing to obtain the original pulse width modulation signal, and outputting the pulse width modulation signal to a gate pole of the IGBT to be detected and a logic processing circuit. The voltage level of the pulse width modulation signal output by the control module can be matched with the voltage required by IGBT driving through the first optical coupler.
As shown in fig. 3, the logic processing circuit of the present embodiment includes a first comparator U3, a first voltage-dividing resistor R21, a second voltage-dividing resistor R22, a second comparator U4, and an nor gate U5. The inverting input end of the first comparator is used for receiving a first reference voltage Vref1, the non-inverting input end of the first comparator is connected with one end of the first voltage-dividing resistor and one end of the second voltage-dividing resistor, and the output end of the first comparator is connected with one input end of the NOR gate; the other end of the first voltage dividing resistor is used for receiving a pull-up voltage VDD; the other end of the second voltage-dividing resistor is used for receiving the pulse width modulation signal output by the inverter in the signal channel.
The inverting input end of the second comparator is used for receiving a second reference voltage Vref2, the non-inverting input end of the second comparator is used for receiving the inverted pulse width modulation signal output by the signal channel, and the output end of the second comparator is connected with the other input end of the NOR gate; the output end of the NOR gate is connected with the gate electrode of the MOS tube and used for outputting a turn-on control signal or a turn-off control signal.
In addition, as shown in fig. 3, the output terminal of the nor gate is connected to the gate of the MOS transistor through a second diode D2, the anode of the second diode is connected to the output terminal of the nor gate, the cathode of the second diode is connected to the gate of the MOS transistor, and the second diode is further connected in parallel with a first resistor R31. The gate of the MOS transistor is connected with the source thereof through a capacitor C.
As shown in fig. 3, the signal output circuit in this embodiment includes a second resistor R32, a third resistor R33, and a second optocoupler U6. One end of the second resistor is connected with the positive electrode of the first diode, and the other end of the second resistor is connected with the negative electrode of the input end of the second optocoupler.
And the positive electrode of the input end of the second optocoupler is used for receiving the driving voltage VDD. The collector of the second optical coupler is used as the output end of the signal output circuit and is connected with one end of the third resistor, and the emitter of the second optical coupler is grounded; the other end of the third resistor is used for receiving the driving voltage VCC.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The technical solutions provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the descriptions of the above examples are only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (4)
1. The utility model provides a detection device that IGBT moves back saturation fault, is applied to and waits to detect the IGBT, wait to detect the IGBT and receive the pulse width modulation signal that control module output through the signal channel, its characterized in that, detection device include with logic processing circuit, MOS pipe, first diode and the signal output circuit that the signal channel is connected, wherein:
the logic processing circuit is connected with the signal channel and is used for acquiring the pulse width modulation signal and the reverse pulse width modulation signal from the signal channel, outputting a conduction control signal to a gate pole of the MOS tube when the pulse width modulation signal is at a low level and outputting a cut-off control signal to the gate pole of the MOS tube when the reverse pulse width modulation signal is at a low level;
the drain electrode of the MOS tube is connected with the anode of the first diode, and the source electrode of the MOS tube is grounded;
the negative electrode of the first diode is connected with the C electrode of the IGBT to be detected, the positive electrode of the first diode is connected with the signal output circuit, and a high-level signal of the positive electrode of the first diode is used as a desaturation fault signal;
the input end of the signal output circuit is connected with the anode of the first diode, and the output end of the signal output circuit is in signal connection with the protection processing unit of the IGB T to be detected;
the logic processing circuit comprises a first comparator, a first voltage-dividing resistor, a second comparator and an OR-NOT gate, wherein:
the inverting input end of the first comparator is used for receiving a first reference voltage, the non-inverting input end of the first comparator is connected with one end of the first voltage-dividing resistor and one end of the second voltage-dividing resistor, and the output end of the first comparator is connected with one input end of the nor gate;
the other end of the first voltage-dividing resistor is used for receiving a pull-up voltage;
the other end of the second voltage-dividing resistor is used for receiving the pulse width modulation signal output by the signal channel;
the inverting input end of the second comparator is used for receiving a second reference voltage, the non-inverting input end of the second comparator is used for receiving the inverse pulse width modulation signal output by the signal channel, and the output end of the second comparator is connected with the other input end of the NOR gate;
the output end of the NOR gate is used for outputting the conduction control signal or the cut-off control signal;
the output end of the NOR gate is connected with the gate electrode of the MOS tube through a second diode, wherein:
the anode of the second diode is connected with the output end of the NOR gate, and the cathode of the second diode is connected with the gate pole of the MOS tube;
the second diode is connected with a first resistor in parallel.
2. The detection apparatus of claim 1, wherein the signal path comprises a first optocoupler, a pull-up resistor, and an inverter, wherein:
the input end of the first optical coupler is used for receiving the pulse width modulation signal;
the emitter of the first optical coupler is grounded, and the collector of the first optical coupler is connected with one end of the pull-up resistor and used for outputting the reverse pulse width modulation signal;
the other end of the pull-up resistor is used for receiving a pull-up voltage;
the input end of the phase inverter is connected with the collector of the first optocoupler, the output end of the phase inverter is connected with the gate pole of the IGBT to be detected, and the output end of the phase inverter is also used for outputting the pulse width modulation signal.
3. The detection device as claimed in claim 1, wherein the gate of the MOS transistor is connected to the source thereof through a capacitor.
4. The detection apparatus of claim 1, wherein the signal output circuit comprises a second resistor, a third resistor, and a second optocoupler, wherein:
one end of the second resistor is connected with the anode of the first diode, and the other end of the second resistor is connected with the cathode of the input end of the second optocoupler;
the positive electrode of the input end of the second optocoupler is used for receiving driving voltage;
the collector of the second optical coupler is used as the output end of the signal output circuit and is connected with one end of the third resistor, and the emitter of the second optical coupler is grounded;
the other end of the third resistor is used for receiving a driving voltage.
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| CN116819264A (en) * | 2022-03-25 | 2023-09-29 | 固赢科技(深圳)有限公司 | Voltage arc detection circuit and control method thereof |
| CN116008769B (en) * | 2023-03-24 | 2023-06-27 | 杭州飞仕得科技股份有限公司 | Self-driven power semiconductor conduction voltage drop detection circuit |
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| CN103022977A (en) * | 2012-11-30 | 2013-04-03 | 复旦大学 | Method for controlling desaturation detection protective circuit in T-shaped three-level inverter |
| CN103595238A (en) * | 2013-09-29 | 2014-02-19 | 深圳市伟创电气有限公司 | Low-power IGBT (insulated gate bipolar transistor) driving interlocking circuit |
| CN204536486U (en) * | 2014-11-19 | 2015-08-05 | 湖南南车时代电动汽车股份有限公司 | A kind of IGBT moves back saturation detection circuit |
| CN106385009A (en) * | 2016-11-30 | 2017-02-08 | 东南大学 | Shaping protection circuit applied to IGBT |
| CN207490887U (en) * | 2017-09-22 | 2018-06-12 | 郑州科创电子有限公司 | IGBT high-frequency soft switch drives thick film |
| CN109672149A (en) * | 2019-01-24 | 2019-04-23 | 上海大学 | A kind of hybrid detection protection circuit and method for NPC three-level current transformer over current fault |
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