CN116819264A - Voltage arc detection circuit and control method thereof - Google Patents
Voltage arc detection circuit and control method thereof Download PDFInfo
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Abstract
The application relates to a voltage arc detection circuit and a control method thereof. The circuit comprises: the device comprises a rectifying circuit, an integrating circuit, an average filter circuit, a NAND gate logic circuit, a NOR gate logic circuit and a comparator; the first signal output end of the NAND gate logic circuit is connected with the power output equipment; the power output equipment is connected with the rectifying circuit; the rectification circuit is respectively connected with the integration circuit and the average filter circuit; the second signal output end of the integrating circuit and the third signal output end of the average filter circuit are connected with the comparator; the NOR gate logic circuit comprises a fourth signal output end, a first time sequence signal input end and a second time sequence signal input end, and a fifth signal output end and the first time sequence signal input end of the comparator are connected with the NAND gate logic circuit; the fourth signal output end is connected with the integrating circuit and used for controlling the working state of the integrating circuit. The scheme provided by the application can detect and inhibit the voltage arc in time, and obviously reduce the occurrence probability of the arc.
Description
Technical Field
The application relates to the technical field of circuits, in particular to a voltage arc detection circuit and a control method thereof.
Background
In a plasma coating system, occasionally, an arc discharge phenomenon is caused due to the fact that the load characteristic is sporadically unstable, a coating product is easy to damage, even the plasma coating system is damaged, the arc discharge phenomenon is generally divided into a current arc phenomenon and a voltage arc phenomenon, wherein after the current arc is generated, the influence on the load is large, but the current arc phenomenon can be found by using overcurrent detection, and the voltage arc phenomenon is difficult to detect. Therefore, it is necessary to design a voltage arc detection circuit to perform voltage arc detection, so as to improve the arc suppression capability of the plasma coating system.
In the prior art, patent publication number CN102621377B (fault arc detection method), based on the general characteristics of an arc, it is proposed to analyze whether the current waveform has zero break, asymmetric positive and negative half cycles, insignificant periodicity and rich high-frequency harmonics by collecting current data of each cycle, so as to determine whether an arc fault occurs, and improve accuracy and precision of fault arc determination.
The above prior art has the following disadvantages:
according to the common characteristic of the arc as a fault arc detection mode, the detection efficiency is low, the timely feedback is poor, the voltage arc cannot be suppressed timely, and the occurrence probability of the arc cannot be reduced.
Disclosure of Invention
In order to overcome the problems in the related art, the application provides a voltage arc detection circuit which can detect and inhibit a voltage arc in time and obviously reduce the occurrence probability of the arc.
A first aspect of the present application provides a voltage arc detection circuit comprising:
the device comprises a rectifying circuit, an integrating circuit, an average filter circuit, a NAND gate logic circuit, a NOR gate logic circuit and a comparator;
the first signal output end of the NAND gate logic circuit is connected with the power output equipment and used for controlling the start and stop of the power output equipment;
the power output equipment is connected with the rectifying circuit;
the rectification circuit is respectively connected with the integration circuit and the average filter circuit;
the second signal output end of the integrating circuit and the third signal output end of the average filter circuit are connected with the comparator;
the NOR gate logic circuit comprises a fourth signal output end, a first time sequence signal input end and a second time sequence signal input end, and a fifth signal output end and the first time sequence signal input end of the comparator are connected with the NAND gate logic circuit;
the fourth signal output end is connected with the integrating circuit and used for controlling the working state of the integrating circuit, wherein the working state comprises an integrating state and a zero clearing state.
In one embodiment, the integrating circuit includes a first operational amplifier U1, a resistor R1, a capacitor C1, and a MOS transistor Q1;
one end of a resistor R1 is connected with the rectifying circuit, and the other end of the resistor R1 is connected with a first inverting input end of a first operational amplifier U1;
the capacitor C1 is connected between the first inverting input end and the second signal output end, the second signal output end is a first signal output end of the first operational amplifier U1, and the first signal output end is connected with the first input end of the comparator;
the MOS tube Q1 is connected with the capacitor C1 in parallel, and the fourth signal output end is connected with the grid electrode of the MOS tube Q1.
In one embodiment, the average filter circuit includes a second op-amp U3, a resistor R4, a resistor R5, a capacitor C2, and a capacitor C3;
one end of a resistor R4 is connected with the rectifying circuit, and the other end of the resistor R4 is connected with a second inverting input end of a second operational amplifier U3;
the capacitor C2 is connected between the second inverting input end and the second signal output end of the second operational amplifier U3;
one end of the resistor R5 is connected with the second signal output end, and the other end of the resistor R5 is connected with the second input end of the comparator;
one end of the capacitor C3 is connected with the second input end, and the other end of the capacitor C3 is grounded; the node where the resistor R5 is connected and intersected with the capacitor C3 is a third signal output end;
resistor R3 is connected in parallel with capacitor C2.
In one embodiment, a parasitic diode is disposed between the source and drain of the MOS transistor Q1.
In one embodiment, the first signal output is connected to a device control circuit for controlling the start and stop of the power output device.
A second aspect of the present application provides a control method of a voltage arc detection circuit, including:
collecting output voltage of power output equipment, and inputting the rectified voltage obtained by rectifying the output voltage into an integrating circuit and an average filter circuit;
inputting a first time sequence signal to a first time sequence signal input end of the NOR gate logic circuit, inputting a second time sequence signal value to a second time sequence signal input end of the NOR gate logic circuit, and outputting a first level signal by a fourth signal output end of the NOR gate logic circuit;
controlling the working state of the integrating circuit according to the first level signal, and outputting zero at the second signal output end of the integrating circuit when the working state is a zero clearing state;
when the working state is an integral state and the first timing signal is high level, comparing the first voltage signal output by the second signal output end with the second voltage signal output by the third signal output end of the average filter circuit through the comparator, and determining a second level signal output by the first signal output end of the NAND gate logic circuit according to the comparison result;
and controlling the start and stop of the power output equipment according to the second level signal.
In one embodiment, controlling an operating state of the integrating circuit according to the first level signal includes:
if the first level signal is a high level signal, the MOS transistor Q1 of the integrating circuit is controlled to be conducted.
In one embodiment, determining the second level signal output by the first signal output terminal of the nand gate logic circuit according to the comparison result includes:
if the first voltage signal is larger than the second voltage signal, the comparator outputs a low level, and the second level signal is a high level signal;
if the first voltage signal is less than or equal to the second voltage signal, the comparator outputs a high level, and the second level signal is a low level signal.
In one embodiment, controlling the start-stop of the power output device according to the second level signal includes:
if the second level signal is a low level signal, the power output equipment is controlled to be shut down by the equipment control circuit;
if the second level signal is a high level signal, the start-up state of the power output device is maintained.
In one embodiment, the first voltage signal is calculated by a first formula:
V＝(U1+U2+U3+....+Un-1+Un)/n
v is a first voltage signal, U1, U2 and U3.. Un-1 and Un are each rectified voltage corresponding to each collected output voltage, and n is the number of the collected output voltages in one collection period;
the second voltage signal is obtained by calculation through a second formula, wherein the second formula is as follows:
P＝(V1+V2+V3+....+Vm-1+Vm)/m
wherein P is a second voltage signal, V1, V2, V3..
The technical scheme provided by the application can comprise the following beneficial effects:
the voltage arc detection circuit is provided with a rectification circuit, an integration circuit, an average filter circuit, a NAND gate logic circuit, a NOR gate logic circuit and a comparator, wherein the power output equipment is connected with the rectification circuit to rectify the output voltage of the power output equipment, the rectification circuit is respectively connected with the integration circuit and the average filter circuit, and the rectified voltage signal can be input into the integration circuit and the average filter circuit; in addition, the nor gate logic circuit comprises a fourth signal output end, a first time sequence signal input end and a second time sequence signal input end, so that an output signal of the fourth signal output end can be controlled based on signals input by the first time sequence signal input end and the second time sequence signal input end, the fourth signal output end is connected with the integrating circuit and used for controlling the working state of the integrating circuit, wherein the working state comprises an integrating state and a zero clearing state, and the phenomenon that the integrating circuit is over saturated in integration is prevented, and the detection of a voltage arc is influenced; the second signal output end of the integrating circuit and the third signal output end of the average filter circuit are connected with a comparator, the fifth signal output end and the first time sequence signal input end of the comparator are connected with a NAND gate logic circuit, so that the signal output by the fifth signal output end can be determined by comparing the voltage signal output by the integrating circuit and the voltage signal output by the average filter circuit, the signal output by the fifth signal output end and the time sequence signal input by the first time sequence signal input end jointly determine the signal output by the first signal output end of the NAND gate logic circuit, and when the time sequence signal input by the first time sequence signal input end is formulated to avoid the zero clearing state of the voltage signal output by the integrating circuit, the voltage signal output by the integrating circuit can be smaller than the voltage signal output by the average filter circuit, so that the voltage arc detection is misjudged, and the voltage arc detection accuracy is improved; the first signal output end of the NAND gate logic circuit is connected with the power output equipment and used for controlling the start and stop of the power output equipment, detecting voltage arcs in time and executing protection measures in time, so that the occurrence probability of the arcs is remarkably reduced, the power output equipment is prevented from being damaged by the voltage arcs, even the power output equipment is prevented from being damaged, and the production efficiency and the production quality are improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The foregoing and other objects, features and advantages of the application will be apparent from the following more particular descriptions of exemplary embodiments of the application as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the application.
Fig. 1 is a schematic circuit diagram of a voltage arc detection circuit according to an embodiment of the present application;
FIG. 2 is a flow chart of a control method of a voltage arc detection circuit according to an embodiment of the present application;
FIG. 3 is a schematic signal diagram of a voltage arc detection circuit according to an embodiment of the present application when an arc is detected;
FIG. 4 is a schematic signal diagram showing an embodiment of the present application when the voltage arc detection circuit does not detect an arc occurrence;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the application. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Example 1
In a plasma coating system, occasionally, an arc discharge phenomenon is caused due to the fact that the load characteristic is sporadically unstable, a coating product is easy to damage, even the plasma coating system is damaged, the arc discharge phenomenon is generally divided into a current arc phenomenon and a voltage arc phenomenon, wherein after the current arc is generated, the influence on the load is large, but the current arc phenomenon can be found by using overcurrent detection, and the voltage arc phenomenon is difficult to detect. The prior art is based on the common characteristics of the arc as a fault arc detection mode, has lower detection efficiency and poorer timely feedback, can not timely inhibit the voltage arc, and can not reduce the occurrence probability of the arc.
Aiming at the problems, the embodiment of the application provides a voltage arc detection circuit which can detect a voltage arc in time and remarkably reduce the occurrence probability of the arc.
The following describes the technical scheme of the embodiment of the present application in detail with reference to the accompanying drawings.
Referring to fig. 1, an embodiment of a voltage arc detection circuit according to the present application includes:
the device comprises a rectifying circuit, an integrating circuit, an average filter circuit, a NAND gate logic circuit, a NOR gate logic circuit and a comparator, wherein the NAND gate logic circuit is U5 in fig. 1, the NOR gate logic circuit is U4 in fig. 1, and the comparator is U2 in fig. 1. Specifically, the power output device is connected to the rectifying circuit, so that the output voltage of the power output device, that is, the Uac in fig. 1, can be collected and input into the rectifying circuit, where the rectifying circuit is connected to the integrating circuit and the average filtering circuit, respectively, so that the rectified voltage, that is, urec in fig. 1, can be input into the integrating circuit and the average filtering circuit, respectively, for processing, in the embodiment of the present application, the integrating circuit is used for performing average processing on the voltage collected in each collection period, the average filtering circuit is used for performing average processing on the voltage collected in each collection period, and the collection period may be set as a period of half a sinusoidal alternating current corresponding to the output voltage of the power output device, or may be set as another form, where the period is not limited only, and in the embodiment of the present application, the rectifying circuit is required to rectify the output voltage into a direct current pulse signal and then perform average processing.
In addition, the nor gate logic circuit includes a fourth signal output end, a first timing signal input end and a second timing signal input end, wherein the fourth signal output end is a point C in fig. 1, the first timing signal input end is a point a in fig. 1, and the second timing signal input end is a point B in fig. 1, so that an output signal of the fourth signal output end can be controlled based on signals input by the first timing signal input end and the second timing signal input end, the fourth signal output end is connected with the integrating circuit and is used for controlling an operating state of the integrating circuit, and the operating state includes an integrating state and a zero clearing state. In the embodiment of the present application, a half period of sinusoidal ac is used as the acquisition period, and it can be understood that if zero clearing is not performed, the integration circuit continuously performs integration, so that the second signal output end of the integration circuit, i.e. the point E in fig. 1, is excessively saturated with the output voltage signal, and the voltage arc detection and judgment of the next acquisition period is affected, and the waveform change corresponding to each half period of sinusoidal ac cannot be represented, so that it is necessary to properly switch the working state of the integration circuit to the zero clearing state.
Further, the second signal output end of the integrating circuit and the third signal output end of the averaging filter circuit, i.e. the point F in fig. 1, are connected to the comparator, specifically, the second signal output end is connected to the inverting input end of the comparator, the third signal output end is connected to the non-inverting input end of the comparator, which is not limited only, the fifth signal output end of the comparator, i.e. the point G in fig. 1, and the first timing signal input end are connected to the nand gate logic circuit, and the first signal output end of the nand gate logic circuit, i.e. the point D in fig. 1, is connected to the power output device for controlling the start and stop of the power output device.
It can be understood that, by comparing the voltage signal of the second signal output terminal with the voltage signal of the third signal output terminal, the signal output by the fifth signal output terminal is determined, so that the output signal of the first signal output terminal of the nand gate logic circuit can be determined by the timing signal input by the first timing signal input terminal and the signal output by the fifth signal output terminal together, and the start and stop of the power output device can be controlled according to the signals. The voltage signal of the third signal output end is a voltage signal obtained by averaging the voltages collected in each acquisition period, which is relatively stable, and can be regarded as a constant value, the voltage signal of the second signal output end is cleared after each acquisition period is finished, then the integration task of the next acquisition period is re-executed, when the clear state is finished, even in a certain time, the voltage signal of the second signal output end is likely to be smaller than the voltage signal of the third signal output end, and in the moment, the situation that voltage arc detection errors are easily caused is not caused, in order to avoid the situation, the time sequence signal input by the first signal input end is required to be judged, the time sequence signal input by the first signal input end is formulated, and the signal output by the fifth signal output end can be effective when the time sequence signal input by the first signal input end is at a high level, and the time sequence signal input by the first signal input end is not influenced by the first signal output end, therefore the first signal input end is not influenced by the fact that the first signal output is not limited, and the output of the device is not required to be interpreted when the time sequence signal is at the first signal output.
The following advantages can be seen from the first embodiment described above:
the voltage arc detection circuit is provided with a rectification circuit, an integration circuit, an average filter circuit, a NAND gate logic circuit, a NOR gate logic circuit and a comparator, wherein the power output equipment is connected with the rectification circuit to rectify the output voltage of the power output equipment, the rectification circuit is respectively connected with the integration circuit and the average filter circuit, and rectified voltage signals can be input into the integration circuit and the average filter circuit; in addition, the nor gate logic circuit comprises a fourth signal output end, a first time sequence signal input end and a second time sequence signal input end, so that an output signal of the fourth signal output end can be controlled based on signals input by the first time sequence signal input end and the second time sequence signal input end, the fourth signal output end is connected with the integrating circuit and used for controlling the working state of the integrating circuit, wherein the working state comprises an integrating state and a zero clearing state, and the phenomenon that the integrating circuit is over saturated in integration is prevented, and the detection of a voltage arc is influenced; the second signal output end of the integrating circuit and the third signal output end of the average filter circuit are connected with a comparator, the fifth signal output end and the first time sequence signal input end of the comparator are connected with a NAND gate logic circuit, so that the signal output by the fifth signal output end can be determined by comparing the voltage signal output by the integrating circuit and the voltage signal output by the average filter circuit, the signal output by the fifth signal output end and the time sequence signal input by the first time sequence signal input end jointly determine the signal output by the first signal output end of the NAND gate logic circuit, and when the time sequence signal input by the first time sequence signal input end is formulated to avoid the voltage signal output by the integrating circuit in the ending zero clearing state, the voltage signal output by the integrating circuit is necessarily smaller than the voltage signal output by the average filter circuit, so that the voltage arc detection is misjudged, and the voltage arc detection accuracy is improved; the first signal output end of the NAND gate logic circuit is connected with the power output equipment and used for controlling the start and stop of the power output equipment, detecting voltage arcs in time and executing protection measures in time, so that the occurrence probability of the arcs is remarkably reduced, the power output equipment is prevented from being damaged by the voltage arcs, even the power output equipment is prevented from being damaged, and the production efficiency and the production quality are improved.
Example two
For ease of understanding, one embodiment of the voltage arc detection circuit is provided below for illustration, and in practical applications, the integrating circuit and the averaging filter circuit are further designed.
Referring to fig. 1, 3 and 4, an embodiment of a voltage arc detection circuit according to the present application includes:
the integrating circuit comprises a first operational amplifier U1, a resistor R1, a capacitor C1 and a MOS tube Q1, one end of the resistor R1 is connected with the rectifying circuit, the other end of the resistor R1 is connected with a first inverting input end of the first operational amplifier U1, the capacitor C1 is connected between the first inverting input end and a second signal output end, the second signal output end is a first signal output end of the first operational amplifier U1, the first signal output end is connected with a first input end of a comparator, the MOS tube Q1 is connected with the capacitor C1 in parallel, a fourth signal output end is connected with a grid electrode of the MOS tube Q1, a first in-phase input end of the first operational amplifier U1 is grounded, and a parasitic diode is arranged between a source electrode and a drain electrode of the MOS tube Q1.
It can be understood that the output signal of the fourth signal output end can control the on or off of the MOS transistor Q1, for example, as shown in fig. 3 and fig. 4, if the first timing signal input end and the second timing signal input end simultaneously input the low level signal, resulting in the output signal of the fourth signal output end being the high level signal, the MOS transistor Q1 is turned on, and at this time, the voltage at the point E in fig. 1, that is, the voltage signal of the second signal output end is 0V; if the first time sequence signal input end and the second time sequence signal input end input different level signals, the output signal of the fourth signal output end is a low level signal, the MOS tube Q1 is disconnected, and the working state of the integrating circuit is in an integrating state.
The average filter circuit comprises a second operational amplifier U3, a resistor R4, a resistor R5, a capacitor C2 and a capacitor C3, wherein one end of the resistor R4 is connected with the rectifying circuit, the other end of the resistor R4 is connected with a second inverting input end of the second operational amplifier U3, the capacitor C2 is connected between the second inverting input end and a second signal output end of the second operational amplifier U3, one end of the resistor R5 is connected with the second signal output end, the other end of the resistor R5 is connected with a second input end of the comparator, one end of the capacitor C3 is connected with the second input end, and the other end of the capacitor C3 is grounded; the node where the resistor R5 is connected and intersected with the capacitor C3 is a third signal output end, the resistor R3 is connected with the capacitor C2 in parallel, and a second non-inverting input end of the second operational amplifier U3 is grounded. It can be understood that the averaging filter circuit may be represented by a low-pass filter circuit configured in the above manner, which is actually to perform the accumulation and then average processing on the average voltages corresponding to the multiple acquisition periods, which is equivalent to performing the average calculation on the rectified voltage signal Urec to obtain the voltage signal of the third signal output end.
In the embodiment of the application, an equipment control circuit is also arranged, and the first signal output end is connected with the equipment control circuit to guide the equipment control circuit to control the start and stop of the power output equipment.
Example III
Corresponding to the embodiment of the voltage arc detection circuit, the application also provides a control method of the voltage arc detection circuit and a corresponding embodiment.
Fig. 2 is a flow chart of a control method of the voltage arc detection circuit according to an embodiment of the application.
Referring to fig. 2, a control method of a voltage arc detection circuit according to an embodiment of the application includes:
301. collecting output voltage of power output equipment, and inputting the rectified voltage obtained by rectifying the output voltage into an integrating circuit and an average filter circuit;
the power output device is connected with the rectifying circuit and then is respectively connected with the integrating circuit and the average filter circuit, so that the output voltage of the power output device can be acquired and rectified into a direct current pulse signal, and the rectified voltage corresponding to the direct current pulse signal is input to the integrating circuit and the average filter circuit for processing.
302. Inputting a first time sequence signal to a first time sequence signal input end of the NOR gate logic circuit, inputting a second time sequence signal value to a second time sequence signal input end of the NOR gate logic circuit, and outputting a first level signal by a fourth signal output end of the NOR gate logic circuit;
in the embodiment of the present application, the first timing signal and the second timing signal are specific timing signals, which may be frequency-doubled signals of Uac and have the same frequency as Urec, and are not limited only. In an acquisition period, namely a period of half sine alternating current corresponding to the output voltage of the power output device, the first time sequence signal is firstly kept in a low level signal and then is changed into a high level signal, and finally falls back to the low level signal, wherein the first start of keeping the low level signal is to consider the comparison result between the first voltage signal output by the second signal output end of the integrating circuit and the second voltage signal output by the third signal output end of the average filter circuit in a preset time, and because the first voltage signal is still in a continuous integration and lifting stage, the situation that the first voltage signal is smaller than the second voltage signal is likely to occur, so that erroneous judgment is caused, the first time sequence signal is required to be kept in the low level signal, the second level signal output by the NAND gate logic circuit is kept in the high level, and the comparison result between the first voltage signal and the second voltage signal is shielded or not considered, so that the normal operation of the power output device is not affected by the comparison result. When the first timing signal is changed to the high level signal, as shown in fig. 3 and 4, the second level signal is determined by the comparison result between the first voltage signal and the second voltage signal, and the time for the first timing signal to keep the high level signal can be regarded as the arc detection time T1. When the first timing signal falls back to the low level signal, and the second timing signal is converted from the high level signal which is originally maintained to the low level signal, the fourth signal output end of the nor gate logic circuit outputs the first level signal, that is, the high level signal, then the MOS transistor Q1 of the integrating circuit is controlled to be turned on, and the voltage at the point E in fig. 1, that is, the voltage signal at the output end of the second signal is 0V, so before the collection period ends, the time when the first timing signal falls back to the low level signal can be regarded as the E signal clearing time T2, and as each collection period is continuously performed, then the like.
303. Controlling the working state of the integrating circuit according to the first level signal, and outputting zero at the second signal output end of the integrating circuit when the working state is a zero clearing state;
if the zero clearing is not performed, the integrating circuit continuously integrates, so that the second signal output end of the integrating circuit, i.e. the point E in fig. 1, is over saturated with the output voltage signal, which affects the voltage arc detection judgment of the next acquisition period, and the waveform change corresponding to each half period of the sinusoidal alternating current cannot be represented, so that it is necessary to properly switch the working state of the integrating circuit to the zero clearing state.
304. Controlling the working state of the integrating circuit according to the first level signal, comparing the first voltage signal output by the second signal output end with the second voltage signal output by the third signal output end of the average filter circuit through the comparator when the working state is the integrating state and the first time sequence signal is high level, and determining the second level signal output by the first signal output end of the NAND gate logic circuit according to the comparison result;
in the embodiment of the present application, it is specified that when the first voltage signal is greater than the second voltage signal, the comparator outputs a low level signal, it is considered that no voltage arc is generated at this time, and because the first timing signal is high, the second level signal output from the first signal output terminal of the nand gate logic circuit is high, no protection measures need to be performed, and when the first voltage signal is less than or equal to the second voltage signal, as shown in fig. 3, the reason why the first voltage signal is less than or equal to the second voltage signal is because the generation of the voltage arc causes the waveform drop of Urec, resulting in the reduction of the signal amplification of the E signal when the arc occurs, and therefore, it is considered that there is a risk of generating a voltage arc or that a voltage arc has been generated at this time, the comparator outputs a high level signal, and because the first timing signal is high, the second level signal output from the first signal output terminal of the nand gate logic circuit is low, and protection measures need to be performed. It can be understood that the high level or the low level of the level signal triggering the execution of the protection measure can be determined according to the actual application situation, and the level signal output by the comparator is matched correspondingly, which is not limited only herein.
Specifically, the first voltage signal is obtained by performing equivalent calculation through a first formula, where the first formula is:
V＝(U1+U2+U3+....+Un-1+Un)/n
v is a first voltage signal, U1, U2 and U3.. Un-1 and Un are each rectified voltage corresponding to each collected output voltage, and n is the number of the collected output voltages in one collection period;
the second voltage signal is obtained through equivalent calculation through a second formula, wherein the second formula is as follows:
P＝(V1+V2+V3+....+Vm-1+Vm)/m
wherein P is a second voltage signal, V1, V2, V3..
It can be understood that the above equivalent calculation manners of the first voltage signal and the second voltage signal are only better understood, and in practical application, the determination manners of the first voltage signal and the second voltage signal are various, and the voltage signals of the corresponding output ends of the integrating circuit and the average filter circuit can be directly obtained, so that the determination manners of the first voltage signal and the second voltage signal need to be determined according to the practical application situation, which is not limited only herein.
It will also be appreciated that in practical applications, the second voltage signal may be multiplied by a preset coefficient, and then compared with the first voltage signal, where the preset coefficient may be, for example, 20%,40%,50%,60%,80%, 100%, etc., and the determination of the preset coefficient may be determined according to the practical application, which is not limited herein.
It should be further understood that the execution sequence between the step 303 and the step 304 is not strictly defined, and the step 303 or the step 304 needs to be determined according to the actual judgment, which is not limited herein.
305. And controlling the start and stop of the power output equipment according to the second level signal.
In the embodiment of the application, if the second level signal is a low level signal, the power output device is controlled to be turned off by the device control circuit, and if the second level signal is a high level signal, the starting state of the power output device is maintained.
Example IV
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Referring to fig. 5, the electronic device 1000 includes a memory 1010 and a processor 1020.
The processor 1020 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Memory 1010 may include various types of storage units, such as system memory, read Only Memory (ROM), and persistent storage. Where the ROM may store static data or instructions that are required by the processor 1020 or other modules of the computer. The persistent storage may be a readable and writable storage. The persistent storage may be a non-volatile memory device that does not lose stored instructions and data even after the computer is powered down. In some embodiments, the persistent storage device employs a mass storage device (e.g., magnetic or optical disk, flash memory) as the persistent storage device. In other embodiments, the persistent storage may be a removable storage device (e.g., diskette, optical drive). The system memory may be a read-write memory device or a volatile read-write memory device, such as dynamic random access memory. The system memory may store instructions and data that are required by some or all of the processors at runtime. Furthermore, memory 1010 may comprise any combination of computer-readable storage media including various types of semiconductor memory chips (DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), magnetic disks, and/or optical disks may also be employed. In some implementations, memory 1010 may include readable and/or writable removable storage devices such as Compact Discs (CDs), digital versatile discs (e.g., DVD-ROMs, dual-layer DVD-ROMs), blu-ray discs read only, super-density discs, flash memory cards (e.g., SD cards, min SD cards, micro-SD cards, etc.), magnetic floppy disks, and the like. The computer readable storage medium does not contain a carrier wave or an instantaneous electronic signal transmitted by wireless or wired transmission.
The memory 1010 has stored thereon executable code that, when processed by the processor 1020, can cause the processor 1020 to perform some or all of the methods described above.
The aspects of the present application have been described in detail hereinabove with reference to the accompanying drawings. In the foregoing embodiments, the descriptions of the embodiments are focused on, and for those portions of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. Those skilled in the art will also appreciate that the acts and modules referred to in the specification are not necessarily required for the present application. In addition, it can be understood that the steps in the method of the embodiment of the present application may be sequentially adjusted, combined and pruned according to actual needs, and the modules in the device of the embodiment of the present application may be combined, divided and pruned according to actual needs.
Furthermore, the method according to the application may also be implemented as a computer program or computer program product comprising computer program code instructions for performing part or all of the steps of the above-described method of the application.
Alternatively, the application may also be embodied as a non-transitory machine-readable storage medium (or computer-readable storage medium, or machine-readable storage medium) having stored thereon executable code (or a computer program, or computer instruction code) which, when executed by a processor of an electronic device (or electronic device, server, etc.), causes the processor to perform part or all of the steps of the above-described method according to the application.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the application herein may be implemented as electronic hardware, computer software, or combinations of both.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The foregoing description of embodiments of the application has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (10)
1. A voltage arc detection circuit, comprising:
the device comprises a rectifying circuit, an integrating circuit, an average filter circuit, a NAND gate logic circuit, a NOR gate logic circuit and a comparator;
the first signal output end of the NAND gate logic circuit is connected with the power output equipment and is used for controlling the start and stop of the power output equipment;
the power output device is connected with the rectifying circuit;
the rectification circuit is respectively connected with the integrating circuit and the average filter circuit;
the second signal output end of the integrating circuit and the third signal output end of the average filter circuit are connected with the comparator;
the NOR gate logic circuit comprises a fourth signal output end, a first time sequence signal input end and a second time sequence signal input end, wherein the fifth signal output end and the first time sequence signal input end of the comparator are connected with the NAND gate logic circuit;
the fourth signal output end is connected with the integrating circuit and used for controlling the working state of the integrating circuit, and the working state comprises an integrating state and a zero clearing state.
2. The voltage arc detection circuit of claim 1 wherein,
the integrating circuit comprises a first operational amplifier U1, a resistor R1, a capacitor C1 and a MOS tube Q1;
one end of the resistor R1 is connected with the rectifying circuit, and the other end of the resistor R1 is connected with the first inverting input end of the first operational amplifier U1;
the capacitor C1 is connected between the first inverting input end and the second signal output end, the second signal output end is a first signal output end of the first operational amplifier U1, and the first signal output end is connected with the first input end of the comparator;
the MOS tube Q1 is connected with the capacitor C1 in parallel, and the fourth signal output end is connected with the grid electrode of the MOS tube Q1.
3. The voltage arc detection circuit of claim 1 wherein,
the average filter circuit comprises a second operational amplifier U3, a resistor R4, a resistor R5, a capacitor C2 and a capacitor C3;
one end of the resistor R4 is connected with the rectifying circuit, and the other end of the resistor R4 is connected with the second inverting input end of the second operational amplifier U3;
the capacitor C2 is connected between the second inverting input end and the second signal output end of the second operational amplifier U3;
one end of the resistor R5 is connected with the second signal output end, and the other end of the resistor R5 is connected with the second input end of the comparator;
one end of the capacitor C3 is connected with the second input end, and the other end of the capacitor C3 is grounded; a node, at which the resistor R5 is connected and intersected with the capacitor C3, is the third signal output end;
the resistor R3 is connected in parallel with the capacitor C2.
4. The voltage arc detection circuit of claim 2 wherein,
a parasitic diode is arranged between the source electrode and the drain electrode of the MOS tube Q1.
5. The voltage arc detection circuit of claim 1 wherein,
the first signal output end is connected with an equipment control circuit, and the equipment control circuit is used for controlling the start and stop of the power output equipment.
6. A control method of the voltage arc detection circuit, for controlling the voltage arc detection circuit according to any one of claims 1 to 5 to perform voltage arc detection, comprising:
collecting output voltage of power output equipment, and inputting the rectified voltage obtained by rectifying the output voltage into an integrating circuit and an average filter circuit;
inputting a first time sequence signal to a first time sequence signal input end of a NOR gate logic circuit, inputting a second time sequence signal value to a second time sequence signal input end of the NOR gate logic circuit, and outputting a first level signal by a fourth signal output end of the NOR gate logic circuit;
controlling the working state of the integrating circuit according to the first level signal, and outputting zero by the second signal output end of the integrating circuit when the working state is a zero clearing state;
when the working state is an integral state and the first timing signal is high level, comparing the first voltage signal output by the second signal output end with the second voltage signal output by the third signal output end of the average filter circuit through a comparator, and determining a second level signal output by the first signal output end of the NAND gate logic circuit according to a comparison result;
and controlling the start and stop of the power output equipment according to the second level signal.
7. The method for controlling a voltage arc detection circuit according to claim 6, wherein,
the controlling the working state of the integrating circuit according to the first level signal includes:
and if the first level signal is a high level signal, controlling the MOS tube Q1 of the integrating circuit to be conducted.
8. The method for controlling a voltage arc detection circuit according to claim 6, wherein,
the determining the second level signal output by the first signal output end of the NAND gate logic circuit according to the comparison result comprises the following steps:
if the first voltage signal is greater than the second voltage signal, the comparator outputs a low level, and the second level signal is a high level signal;
and if the first voltage signal is smaller than or equal to the second voltage signal, the comparator outputs a high level, and the second level signal is a low level signal.
9. The method for controlling a voltage arc detection circuit according to claim 6, wherein,
the controlling the start and stop of the power output device according to the second level signal includes:
if the second level signal is a low level signal, controlling the power output equipment to be shut down through an equipment control circuit;
and if the second level signal is a high level signal, maintaining the starting state of the power output equipment.
10. The method for controlling a voltage arc detection circuit according to claim 6, wherein,
the first voltage signal is obtained by calculation through a first formula, and the first formula is as follows:
V＝(U1+U2+U3+....+Un-1+Un)/n
wherein V is the first voltage signal, U1, U2, U3.. Un-1 and Un are each rectified voltage corresponding to each collected output voltage, n is the number of collected output voltages in one collection period;
the second voltage signal is obtained by calculation through a second formula, and the second formula is as follows:
P＝(V1+V2+V3+....+Vm-1+Vm)/m
wherein P is the second voltage signal, V1, V2, V3..
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