CN1121059C - Method for makig fork-type lower electrode of capacitor - Google Patents

Abstract

The present invention relates to a method for making a fork-shaped lower electrode of a capacitor. The capacitor is positioned in a substrate. The method comprises: a first dielectric layer, a nitride layer and a second dielectric layer are orderly formed on the substrate, the layers are patterned and etched until the substrate is exposed to form a window opening, and an electric conduction male contact is formed in the opening; the second dielectric layer beside the electric conduction male contact is patterned and etched to form two regions, wherein the regions are surrounded by the nitride layer, the electric conduction male contact and the second dielectric layer to form a conformal electric conduction layer; a part of the electric conduction layer, which are on the second dielectric layer and the electric conduction male contact, is removed, and the residual part of the second dielectric layer is removed.

Description

Make the method for the forked type bottom electrode of capacitor

(dynamic random accessmemory, method DRAM) particularly relate to the method for the forked type bottom electrode of the capacitor among a kind of DRAM of manufacturing to the present invention relates to a kind of manufacturing dynamic random access memory.

Reduce the size of the wafer of DRAM, making its integrated level and memory capacity increase is present trend.The size of DRAM reduces, and the capacitor among the DRAM also can correspondingly dwindle.

Generally speaking the memory cell of DRAM comprises holding capacitor and access transistor.Along with the appearance of the DRAM of height integrated level, size of component becomes littler and littler, and the related area that makes each independent memory cell to use becomes very little.Also make the capacitance of memory cell reduce along with the minimizing of the area of capacitor.

The long-pending capacitor of bigger lower electrode surface that has of prior art comprises manufacturing stacked capacitor and crown capacitor.But a kind of surface area is bigger, and structure still has it to need than the manufacture method of the crown constitutionally stable capacitor of prior art.

The invention provides a kind of method of in substrate, making the forked type bottom electrode of capacitor.This method comprises: form one first dielectric layer in substrate; On first dielectric layer, form one deck nitride layer; On nitride layer, form one second dielectric layer; To first dielectric layer, nitride layer, carry out composition and etched step, expose up to substrate, with the formation contact window with second dielectric layer; In contact window with on second dielectric layer, form first conductive layer; Remove the some of first conductive layer on second dielectric layer, in contact window, to form conductive plunger; The part of second dielectric layer to next-door neighbour's conductive plunger is carried out composition and etched operation, till arriving nitride layer, forming two zones, is nitride layer bottom it, Yi Bian be conductive plunger, another side is second dielectric layer; Second dielectric layer, nitride layer, with conductive plunger on form and the second conformal conductive layer of its area surrounded; Remove the some of second conductive layer on second dielectric layer and the conductive plunger; And the remainder that removes second dielectric layer.

For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborates.In the accompanying drawing:

What Fig. 1 illustrated to Fig. 7 is the profile at the semiconductor-based end, demonstrates the step that forms the DRAM memory cell among the present invention respectively;

Fig. 8 A and Fig. 8 B illustrate the stacked electrode and the crown electrode of prior art respectively.

Then, will elaborate in conjunction with the accompanying drawings to the present invention.The invention provides a kind of manufacture method of fork-shaped capacitor, the memory cell capacitor amount of this capacitor is big and applicability is better.

Please refer to Fig. 1, what wherein illustrate is semi-conductive substrate 100.Substrate 100 can be semi-conductive wafer, has active element and passive component on the wafer, and has various materials on the wafer and pile many layers." substrate " this speech also comprises element and each layer on wafer on the semiconductor crystal wafer.

Please refer to Fig. 1, in substrate 100, form one deck first dielectric layer 102, can use traditional chemical vapour deposition technique.The material of first dielectric layer 102 can be silica, boron-phosphorosilicate glass (borophosilicate, BPSG), spin-on glasses (spin-on-glass, SOG), or other composite material of above-mentioned material.The thickness of first dielectric layer uses about 1000 dusts between about 2000 dusts in the present embodiment.

Then, use the mode of prior art on first dielectric layer 102, to form one deck silicon nitride layer 104.In the present embodiment, silicon nitride layer 104 is to use Low Pressure Chemical Vapor Deposition (LPCVD) to deposit, and the gas source of deposition is SiH ₂Cl ₂, temperature then is between about 700 ℃ to about 800 ℃, pressure then is between about 1 torr at about 0.1 torr.The thickness of silicon nitride layer 104 then is between about 200 dusts at about 50 dusts.Silicon nitride layer is in order to be used as etch stop layer.

Then, deposition one deck second dielectric layer 106 on silicon nitride layer 104.Second dielectric layer 106 can use silica, boron-phosphorosilicate glass, spin-on glasses or comprise other composite material of above-mentioned material.The thickness of second dielectric layer uses about 4000 dusts between about 15000 dusts in the present embodiment.

Please refer to Fig. 2, a contact window 108 is wherein arranged, be to use traditional photoetching and etching step to do.Second dielectric layer 106 wherein, the silicon nitride layer 104 and first dielectric layer 102 all are etched back, to form this contact window 108.Can by on second dielectric layer 106 deposition one deck for example the photoresist layer to realize this step.Then, again with photoresist layer composition and development, so that contact window 108 exposes.At last, to second dielectric layer 106, silicon nitride layer 104, and first dielectric layer 102 makes one or more anisotropic etching steps, till etching into substrate 100.Contact window 108 generally can be held on the drain electrode of the access transistor of DRAM memory cell.

Please refer to Fig. 3, in contact window 108, deposition and one deck doped polycrystalline silicon layer of mixing simultaneously on second dielectric layer 106.In the present embodiment, this polysilicon layer is formed by traditional chemical vapour deposition technique.Then, can use reactive ion-etching (reactive ion etching, RIE) or chemical mechanical milling method (chemical mechanical polishing CMP) comes the etching polysilicon layer.Etched step can stop when etching into second dielectric layer 106, and stays the polysilicon plug 110 of the doping in the contact window 108.

Please refer to Fig. 4, use traditional photoetching corrosion step, and with silicon nitride layer 104 be etching end point remove second dielectric layer 106 around polysilicon plug 110 with the part on next door.Like this, will come out in the top of polysilicon plug 110.So just, forming one can be the zone in two U-shaped districts 112 by cross sectional side view, and is silicon nitride layer 104 bottom it, be the polysilicon plug 110 that expose on one side, another side is second dielectric layer 106.And the width in U-shaped district arrives between about 3000 dusts at about 1500 dusts.

Please refer to Fig. 5, in the part that polysilicon plug 110 comes out, silicon nitride layer 104 and re-uses traditional chemical deposition in addition and forms one deck doped polycrystalline silicon layer 114 on second dielectric layer 106.This floor polysilicon layer 114 can not fill up U-shaped district 112 fully.This layer polysilicon layer 114 is best when about 400 dusts.

Please refer to Fig. 6, use traditional photoetching and etch process or chemical mechanical milling method that second dielectric layer 106 is worn with the polysilicon layer 114 on the polysilicon plug 110.

Please refer to Fig. 7, second dielectric layer, 106 rest parts are removed with traditional etching step.Second dielectric layer 106 can be with removing as traditional oxide wet etch method.Etchant can be with diluent hydrofluoric acid solution or gas.

So just, can form the fork-shaped bottom electrode of capacitor.Stacked electrode 116 among this fork-shaped bottom electrode and Fig. 8 A and the crown electrode 118 among Fig. 8 B have the area of bigger store charge by comparison.In addition, the fork-shaped bottom electrode is because the sedimentation time of required polysilicon layer 114 is short, so output is big

Usually on polysilicon layer 114, can deposit the thin dielectric layer of one deck as nitride/oxide (NO) or oxide/nitride/oxide (ONO).And then one deck polysilicon layer is deposited on the thin dielectric layer, to form the top electrode of capacitor.Other subsequent step of the present invention just no longer describes in detail at this.

Though the present invention discloses as above in conjunction with a preferred embodiment; but it is not in order to limit the present invention; those skilled in the art can make various changes and retouching without departing from the spirit and scope of the present invention, so protection scope of the present invention should be defined by appended claim.

Claims (4)

1. method of making the forked type bottom electrode of capacitor, this capacitor is positioned at a substrate, and this method comprises:

On this substrate, form one first dielectric layer;

On this first dielectric layer, form the mononitride layer;

On this nitride layer, form one second dielectric layer;

To this first dielectric layer, this nitride layer, this second dielectric layer carries out composition and etched step, exposes up to this substrate, thereby forms a contact window;

In this contact window, form a conductive plunger;

Second dielectric layer other to this conductive plunger carries out composition and etched step, and to form two zones, wherein this zone is by this nitride layer, this conductive plunger, is centered on this second dielectric layer;

On this second dielectric layer, this nitride layer, this conductive plunger, form and the conformal conductive layer of this regional shape;

Remove this conductive layer on this second dielectric layer with the part of this conductive plunger; And

Remove this second dielectric layer rest parts.

2. the method for the forked type bottom electrode of manufacturing capacitor as claimed in claim 1, wherein, this first dielectric layer and this second dielectric layer are silica, boron-phosphorosilicate glass, spin-on glasses, or other composite material of above-mentioned material.

3. the method for the forked type bottom electrode of manufacturing capacitor as claimed in claim 1, wherein, this conductive plunger and this conductive layer are formed by instant doped polycrystalline silicon.

4. the method for the forked type bottom electrode of manufacturing capacitor as claimed in claim 1, wherein this nitride layer is a silicon nitride.

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