CN112103296A - Method for manufacturing semiconductor structure - Google Patents

Method for manufacturing semiconductor structure Download PDF

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Publication number
CN112103296A
CN112103296A CN202010797993.5A CN202010797993A CN112103296A CN 112103296 A CN112103296 A CN 112103296A CN 202010797993 A CN202010797993 A CN 202010797993A CN 112103296 A CN112103296 A CN 112103296A
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dielectric layer
thickness
opening
layer
forming
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CN112103296B (en
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艾义明
杨永刚
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02343—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

The embodiment of the invention provides a semiconductor structure manufacturing method, which comprises the steps of providing a substrate structure; the base structure comprises a first opening; the first opening depth is greater than a preset depth; forming a first dielectric layer with a first thickness on the side wall of the first opening; oxidizing the first dielectric layer to form an oxide layer on part of the first dielectric layer; in the first opening, the distribution of the second gas decreases with increasing opening depth; removing the oxide layer to obtain a first dielectric layer with a second thickness; the second thickness is less than the first thickness. Therefore, when the film is deposited in the opening with the deeper depth, the form of the deposited dielectric layer can be improved, and the adverse effect on the electrical performance of the semiconductor device caused by the poor form of the dielectric layer is reduced.

Description

Method for manufacturing semiconductor structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor structure.
Background
In the fabrication of semiconductor devices, it is often necessary to form a dielectric layer in High Aspect Ratio (HAR) openings. The step coverage of a dielectric layer is generally measured by the ratio of the thickness of the dielectric layer at the bottom of the opening (Btop) to the thickness of the dielectric layer at the top of the opening (Ttop). Ideally, the thickness of the dielectric layer remains unchanged with the increase of the opening depth, i.e. the step coverage (english expression may be expressed as step coverage) is 1, and in practical applications, since the density distribution of the gas introduced to form the dielectric layer in the opening decreases with the increase of the depth as shown in fig. 1a, the thickness of the dielectric layer decreases with the increase of the opening depth, i.e. the step coverage is less than 1, and the dielectric layer is in a form of being thick at the top and thin at the bottom (as shown in fig. 1 b). However, when the step coverage is small, the electrical performance of the semiconductor device is affected, for example, when the opening is a Channel Hole (CH) of a three-dimensional memory, and the step coverage of the charge trapping layer in the CH is less than 95%, the electrical difference between the top and bottom of the CH is large, and the process requirement cannot be met.
Therefore, an effective method for manufacturing a semiconductor structure is needed to improve the morphology of the deposited dielectric layer when depositing a thin film in a deep opening, thereby reducing the adverse effect on the electrical performance of the semiconductor device due to the poor morphology of the dielectric layer.
Disclosure of Invention
In order to solve the related technical problems, the method for manufacturing the semiconductor structure provided by the embodiment of the invention can improve the form of the deposited dielectric layer when the thin film is deposited in the opening with the deeper depth, thereby reducing the adverse effect on the electrical performance of the semiconductor device caused by the poor form of the dielectric layer.
The embodiment of the invention also provides a manufacturing method of the semiconductor structure, which comprises the following steps:
providing a substrate structure; the base structure comprises a first opening; the first opening depth is greater than a preset depth;
forming a first dielectric layer with a first thickness on the side wall of the first opening;
oxidizing the first dielectric layer to form an oxide layer on part of the first dielectric layer;
removing the oxide layer to obtain a first dielectric layer with a second thickness; the second thickness is less than the first thickness.
In the above aspect, the providing a substrate structure includes:
providing a semiconductor substrate, wherein a stacked structure formed by alternately stacking an insulating layer and a sacrificial layer is formed on the semiconductor substrate;
forming a plurality of channel holes penetrating through the stacked structure;
the forming a first dielectric layer with a first thickness on the sidewall of the first opening of the channel hole includes:
and forming a first dielectric layer with a first thickness on the side wall of the channel hole.
In the above scheme, the method further comprises:
forming a second dielectric layer on the side wall of the channel hole before forming a first dielectric layer with a first thickness on the side wall of the channel hole;
the forming of the first dielectric layer with the first thickness on the side wall of the channel hole comprises the following steps:
and forming a first dielectric layer with a first thickness on the surface of the second dielectric layer.
In the above scheme, a first dielectric layer with a first thickness is formed on the sidewall of the first opening;
forming a first dielectric layer with a first thickness on the side wall of the first opening by using a low-pressure deposition process;
the step of oxidizing the first dielectric layer comprises the following steps:
and carrying out oxidation treatment on the first dielectric layer by utilizing an In-Situ Steam Generation (ISSG) process.
In the above scheme, the material of the first dielectric layer includes silicon nitride or polysilicon.
In the above scheme, the forming a first dielectric layer with a first thickness on at least the sidewall of the first opening includes:
a first dielectric Layer with a first thickness is formed on at least the sidewall of the first opening by using a Chemical Vapor Deposition (CVD) method or an Atomic Layer Deposition (ALD) method.
In the foregoing scheme, the removing the oxide layer includes:
removing the oxide layer by using a wet etching process; wherein; the wet etching process utilizes a hydrofluoric acid solution to remove the oxide layer.
In the above aspect, a ratio of the first thickness to the second thickness is in a range of 2:1 to 3: 1.
The manufacturing method of the semiconductor structure provided by the embodiment of the invention comprises the steps of providing a substrate structure; the base structure comprises a first opening; the first opening depth is greater than a preset depth; forming a first dielectric layer with a first thickness on the side wall of the first opening; oxidizing the first dielectric layer to form an oxide layer on part of the first dielectric layer; in the first opening, the distribution of the second gas decreases with increasing opening depth; removing the oxide layer to obtain a first dielectric layer with a second thickness; the second thickness is less than the first thickness. In the embodiment of the invention, when a film is deposited in the opening with deeper depth, a dielectric layer with a thickness thicker than that to be deposited is deposited firstly, and the thickness of the dielectric layer with the thicker thickness is reduced along with the increase of the depth of the opening; then carrying out oxidation treatment on the thicker dielectric layer, wherein the concentration distribution of the gas introduced for oxidation in the opening and the concentration distribution of the gas introduced for deposition in the opening are similar to each other and are reduced along with the increase of the depth of the opening when carrying out oxidation treatment, namely the form of the oxidized part in the thicker dielectric layer and the form of the thicker dielectric layer are similar to each other and are reduced along with the increase of the depth of the opening; and when the oxide layer is removed later, the thickness of the removed part of the dielectric layer with the thicker thickness is reduced along with the increase of the opening depth, so that the uniformity of the thickness of the obtained dielectric layer to be deposited is well improved. Therefore, when the film is deposited in the opening with the deeper depth, the manufacturing method of the semiconductor structure provided by the embodiment of the invention can improve the form of the deposited dielectric layer, thereby reducing the adverse effect on the electrical performance of the semiconductor device caused by the poor form of the dielectric layer.
Drawings
FIG. 1a is a schematic view of the density distribution of the gas for forming the dielectric layer in the opening according to the embodiment of the present invention;
FIG. 1b is a schematic diagram illustrating a dielectric layer deposited during a deposition of a thin film in a high HAR opening according to the related art;
fig. 2 is a schematic flow chart illustrating an implementation of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.
FIGS. 3 a-3 d are schematic cross-sectional views illustrating a process for fabricating a semiconductor structure according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating the distribution of thin films in an ONOP structure of a three-dimensional memory in an embodiment of the present invention;
FIGS. 5a-5d are schematic cross-sectional views illustrating the fabrication process of a charge trapping layer in an ONOP structure of a three-dimensional memory in an embodiment of the invention.
Description of reference numerals:
30-a base structure; 301-a first opening; 302-a first dielectric layer having a first thickness; 303-complete oxide layer; 302' -a first dielectric layer having a second thickness; 304-a semiconductor substrate; 305-a stacked structure; 3051-an insulating layer; 3052-a sacrificial layer; 306-CH; 307-a second dielectric layer; 308-epitaxial layer; 309-initial charge trapping layer; 310-oxidized oxide layer of charge trapping layer; 309' -final charge trapping layer.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the following will describe specific technical solutions of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention.
In each embodiment of the invention, when a film is deposited in an opening with deeper depth, a dielectric layer with a thickness thicker than that to be deposited is deposited firstly, and the thickness of the dielectric layer with the thicker thickness is reduced along with the increase of the depth of the opening; then carrying out oxidation treatment on the thicker dielectric layer, wherein the concentration distribution of the gas introduced for oxidation in the opening and the concentration distribution of the gas introduced for deposition in the opening are similar to each other and are reduced along with the increase of the depth of the opening when the oxidation treatment is carried out, namely the oxidized part in the thicker dielectric layer is similar to the form of the thicker dielectric layer and is reduced along with the increase of the depth of the opening; and when the oxide layer is removed later, the thickness of the removed part of the dielectric layer with the thicker thickness is reduced along with the increase of the opening depth, so that the uniformity of the thickness of the obtained dielectric layer to be deposited is well improved.
The embodiment of the invention provides a manufacturing method of a semiconductor structure, and fig. 2 is a schematic flow chart of an implementation process of an etching method according to the embodiment of the invention. As shown in fig. 2, the method comprises the steps of:
step 201: providing a substrate structure; the base structure comprises a first opening; the first opening depth is greater than a preset depth;
step 202: forming a first dielectric layer with a first thickness on the side wall of the first opening;
step 203: oxidizing the first dielectric layer to form an oxide layer on part of the first dielectric layer;
step 204: removing the oxide layer to obtain a first dielectric layer with a second thickness; the second thickness is less than the first thickness.
FIGS. 3 a-3 d are schematic cross-sectional views illustrating a semiconductor structure manufacturing process according to an embodiment of the present invention. A method of forming the semiconductor structure of the present embodiment is described below in conjunction with fig. 2 and 3 a-3 d.
In step 201, as shown in fig. 3a, the base structure 30 may include a substrate and a thin film structure formed on the substrate, where the specific composition material of the thin film structure is not limited. The first opening 301 may be a trench or hole structure etched in the base structure 30. In practical applications, the cross section of the opening may be circular, oval, elongated, etc. Here, the first opening 301 having a depth greater than a predetermined depth may be understood as the first opening 301 having a deeper depth. It can be understood that in the case of a deep opening, especially in a deep HAR opening, the dense distribution of the gas introduced into the opening in the opening is more obvious as the depth of the opening increases, and at the same time, the thickness of the film deposited on the side wall of the opening is more obvious as the thickness decreases.
In practical applications, the perpendicularity of the sidewall of the first opening 301 is better, that is, the opening size of the first opening 301 is kept substantially constant with the increase of the depth.
In practical applications, the first opening 301 with better perpendicularity can be obtained by various methods, and the method for obtaining the first opening 301 with better perpendicularity is not limited herein. A specific implementation method comprises the following steps: performing a first etching on the base structure 30 to remove a portion of the base structure 30, thereby forming a first opening 301 having a first depth in the base structure 30; forming a protective layer, wherein the protective layer at least covers the side wall of the first opening 301; performing a second etching on the first opening 301, so that the depth of the first opening 301 is increased to a second depth; wherein, in the second etching process, the etching effect perpendicular to the sidewall direction of the first opening 301 is compensated by consuming the protection layer. In this way, a first opening 301 having a greater depth and an opening size that remains substantially constant with increasing depth can be obtained.
In step 202, as shown in fig. 3b, a first gas is introduced into the first opening 301, and a first dielectric layer 302 with a first thickness is formed on a sidewall of the first opening 301; it will be appreciated that at the first opening 301, the distribution of the first gas decreases with increasing opening depth.
In practical applications, the deposition process parameters need to be controlled such that the first dielectric layer 302 with the first thickness is formed on the sidewall of the first opening 301. The first thickness is larger than the thickness of the finally desired dielectric layer, and in practical applications, the first thickness may be 2 to 3 times the thickness of the finally desired dielectric layer. For example, when the thickness of the final desired dielectric layer is 30 angstroms, the first thickness may be 60 to 90 angstroms.
In an embodiment of the present invention, the material of the first dielectric layer 302 includes a material capable of being oxidized. In practical applications, in an embodiment, the material of the first dielectric layer 302 may include silicon nitride or polysilicon.
In an embodiment, the material of the first dielectric layer 302 includes silicon nitride; the first gas comprises dichlorosilane and ammonia gas.
In practical application, dichlorosilane gas and ammonia gas are introduced into the first opening, dichlorosilane and ammonia gas react to generate silicon nitride under the reaction condition of 700-800 ℃, and the silicon nitride is deposited on the side wall of the first opening to form a first dielectric layer.
In practice, the first dielectric layer 302 may be formed with a first thickness using CVD, or ALD.
It should be noted that, in practical applications, when the first dielectric layer is formed on the sidewall of the first opening 301, the first dielectric layer is also deposited on the bottom of the first opening 301, and since the improvement involved in the embodiment of the present invention does not focus on the bottom deposition of the first opening 301, the bottom deposited first dielectric layer is not shown in fig. 3 a.
It is understood that, here, the density distribution of the first gas in the first opening 301 decreases with increasing opening depth, i.e. there is more first gas at the top of the first opening 301 and less first gas at the bottom of the first opening 301, so that the first dielectric layer 302 with the first thickness is formed to show a decreasing thickness with increasing opening depth.
In step 203, as shown in fig. 3c, a second gas is introduced into the first opening 301, and a portion of the first dielectric layer 302 is oxidized, so that an oxide layer 303 is formed on a portion of the first dielectric layer 302; in said first opening 301 the distribution of said second gas decreases with increasing opening depth.
In practical applications, the complete oxide layer 303 obtained after the oxidation reaction generally includes a first portion and a second portion; the first part is an oxidation layer part formed by oxidizing part of the first dielectric layer with the first thickness; the second portion covers the oxide layer portion on the surface of the first portion. In practical application, the first portion and the second portion have a certain proportional relationship, and the first portion with the preset thickness can be obtained by controlling oxidation process parameters.
In practical applications, the oxidation process may be implemented by a thermal oxidation process.
In practical applications, considering that the first gas and/or the second gas can be introduced into the low-pressure environment to enable the first gas and/or the second gas to enter the bottom of the first opening 301 more, that is, the low pressure can reduce the difference in the distribution of the two gases at different positions of the opening, so that the first dielectric layer with the first thickness can be formed on the sidewall of the first opening 301 by using a low-pressure deposition process, and simultaneously, the distribution of the first gas and the second gas in the first opening can be improved by using a low-pressure thermal oxidation process, such as an ISSG process, so as to further optimize the improvement of the morphology of the deposited dielectric layer.
Based on this, in an embodiment, the forming a first dielectric layer 302 with a first thickness on the sidewall of the first opening 301 includes:
forming a first dielectric layer 302 with a first thickness on the sidewall of the first opening 301 by using a low-pressure deposition process;
the oxidizing process performed on the first dielectric layer 302 includes:
and carrying out oxidation treatment on the first dielectric layer 302 by utilizing an ISSG (in-situ steam generation) process.
Wherein the second gas comprises oxygen and hydrogen.
In practical application, the ISSG process is a rapid thermal annealing process, can heat and cool the wafer in a short time, has less thermal budget and better temperature uniformity. The ISSG process generally involves adding a small amount of hydrogen as a catalyst in an oxygen atmosphere and a chemical reaction similar to combustion at high temperature on the front side of the wafer. The first reaction generates a large amount of gas phase reactive radicals, i.e., atomic oxygen, which participate in the oxidation process of the silicon wafer. The oxidation process is fast, but the quality of the oxide layer is general. In the subsequent steps of the present invention, the oxide layer needs to be removed, and therefore, the quality of the oxide layer is not of great concern.
It is understood that here the concentration distribution of the second gas in the first opening 301 decreases with increasing opening depth, i.e. there is more second gas at the top of the first opening 301 and less first gas at the bottom of the first opening 301, so that the formed oxide layer also shows a decreasing thickness with increasing opening depth.
In step 204, as shown in fig. 3d, in practical applications, in an embodiment, the removing the oxide layer 303 includes: removing the oxide layer 303 by using a wet etching process; wherein; the wet etching process utilizes a hydrofluoric acid solution to remove the oxide layer.
Here, the second thickness is the thickness of the first dielectric layer 302 that is actually ready to be deposited. Obviously, the second thickness is smaller than the first thickness. In practical applications, in an embodiment, a ratio of the first thickness to the second thickness is in a range of 2:1 to 3: 1.
It can be understood that after the oxide layer is removed, the thickness of the removed portion of the first dielectric layer 302 with the first thickness decreases with the increase of the opening, and the removed portion makes up for the original morphological difference of the first dielectric layer with the first thickness, so that the uniformity of the obtained first dielectric layer 302' with the second thickness is improved.
In practical applications, the embodiment of the present invention may also be an improvement on the morphology of the dielectric layer that is deposited again in the first opening where the dielectric layer has been deposited.
Based on this, in an embodiment, the method further comprises:
forming a second dielectric layer on the sidewall of the first opening 301; the forming of the first dielectric layer with a first thickness on the sidewall of the first opening 301 includes:
a first dielectric layer 302 having a first thickness is formed on a surface of the second dielectric layer.
Here, the step coverage of the second dielectric layer is good, i.e., the thickness of the second dielectric layer remains substantially constant with increasing depth. When the material of the second dielectric layer is a material capable of being oxidized, the method of the embodiment of the invention can be adopted to obtain the second dielectric layer with good step coverage; when the material of the second dielectric layer is a material which can not be oxidized, other schemes suitable for the material which can not be oxidized can be adopted to obtain the second dielectric layer with good step coverage.
It should be noted that, in the manufacturing method of the semiconductor structure provided in the embodiment of the present invention, the first gas is different from the second gas, and it is difficult to control the gas inlet parameters of the first gas and the second gas to be completely consistent in practical application, so that the shapes of the oxidized portion of the first deposited thick thin film layer and the thick thin film layer are completely consistent, and further, the thicknesses of the finally obtained deposition layer above and below the opening are completely consistent, but as long as both gases present similar distributions of more than the gases, the uniformity of the thickness of the finally obtained dielectric layer in the present invention is certainly better than that of the dielectric layer directly deposited, that is, the shape of the dielectric layer is improved.
The manufacturing method of the semiconductor structure provided by the embodiment of the invention comprises the steps of providing a substrate structure; the base structure comprises a first opening; the first opening depth is greater than a preset depth; forming a first dielectric layer with a first thickness on the side wall of the first opening; oxidizing the first dielectric layer to form an oxide layer on part of the first dielectric layer; removing the oxide layer to obtain a first dielectric layer with a second thickness; the second thickness is less than the first thickness. In the embodiment of the invention, when a film is deposited in the opening with deeper depth, a dielectric layer with a thickness thicker than that to be deposited is deposited firstly, and the thickness of the dielectric layer with the thicker thickness is reduced along with the increase of the depth of the opening; then carrying out oxidation treatment on the thicker dielectric layer, wherein the concentration distribution of the gas introduced for oxidation in the opening and the concentration distribution of the gas introduced for deposition in the opening are similar to each other and are reduced along with the increase of the depth of the opening when carrying out oxidation treatment, namely the form of the oxidized part in the thicker dielectric layer and the form of the thicker dielectric layer are similar to each other and are reduced along with the increase of the depth of the opening; and when the oxide layer is removed later, the thickness of the removed part of the dielectric layer with the thicker thickness is reduced along with the increase of the opening depth, so that the uniformity of the thickness of the obtained dielectric layer to be deposited is well improved. Therefore, the manufacturing method of the semiconductor structure provided by the embodiment of the invention can improve the form of the dielectric layer when the film is deposited in the opening with the deeper depth, thereby reducing the adverse effect on the electrical performance of the semiconductor device caused by the poor form of the dielectric layer.
In practical applications, the first opening 301 may be used to form a CH structure of a three-dimensional memory, the second dielectric layer may be used to form a blocking dielectric layer of the three-dimensional memory, and the first dielectric layer 302' with the second thickness may be used to form a charge trapping layer of the three-dimensional memory. Specifically, the method comprises the following steps:
an application scenario of the embodiment of the invention is to form a charge trapping layer in a CH of a three-dimensional memory. In the manufacturing process of the three-dimensional memory, it is necessary to form an ONOP structure in CH. Here, the distribution of the film in the ONOP structure is shown in fig. 4. As can be seen from fig. 4, the ONOP structure includes four layers of thin films, specifically including a blocking dielectric layer, a charge trapping layer, a tunneling dielectric layer, and a channel layer, which are sequentially stacked in the CH radial direction; the blocking dielectric layer covering the sidewall surface of the CH is used to reduce the probability that charges in the memory cell move to the gate of the memory cell, and the material of the blocking dielectric layer may include: an Oxide (OX); a charge trapping layer covering the surface of the blocking dielectric layer for trapping charges, wherein the charge trapping layer may be made of materials including: silicon nitride (SIN); a tunneling dielectric layer covering the surface of the charge trapping layer for tunneling charges between the channel region and the charge trapping layer under the action of an applied voltage, wherein the tunneling dielectric layer is made of a material including: an Oxide (OX); a channel layer covering the surface of the tunneling dielectric layer, wherein the channel layer is used for playing a supporting role, and the material of the channel layer can comprise: polysilicon (Poly).
The step coverage rate of each layer of film in the ONOP film structure is very critical, the step coverage rate is required to be more than 95%, otherwise, the electrical property difference between the upper part and the lower part in the CH is larger along with the depth change of the hole, so that the yield or the reliability of the three-dimensional memory is influenced. The charge trapping layer is used as a sandwich layer of an ONOP structure, and deposition of SIN is generally achieved by a single-step ALD process, however, as the number of stacked layers in a three-dimensional memory is higher (greater than or equal to 128 layers), the step coverage of the charge trapping layer is difficult to be ensured to be greater than 95% by the single-step ALD process.
Based on this, in the present application example, the single-step ALD process was changed to three steps to ensure that the step coverage of the charge trapping layer was > 95%. The three-step scheme will be described in detail below with reference to fig. 5a to 5 d.
It should be noted that, in this application embodiment, as shown in fig. 5a, the step of providing the substrate structure includes:
providing a semiconductor substrate 304, wherein a stacked structure 305 in which insulating layers 3051 and sacrificial layers 3052 are alternately stacked is formed on the semiconductor substrate 304;
forming a number of CH 306 through the stacked structure 305;
the forming of the first dielectric layer 302 with the first thickness on the sidewall of the first opening 301 includes:
a first dielectric layer 302 of a first thickness is formed on the sidewalls of the channel hole 306. The method further comprises the following steps:
forming a second dielectric layer 307 on the sidewall of the CH 306 before forming the first dielectric layer 302 with the first thickness on the sidewall of the CH;
the forming of the first dielectric layer 302 with the first thickness on the sidewall of the channel hole 306 includes:
and forming a first dielectric layer 302 with a first thickness on the surface of the second dielectric layer 307.
In practical applications, the semiconductor substrate 304 may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one organic semiconductor material, or other semiconductor materials known in the art. Well regions may also be formed in the semiconductor substrate. The stacked structure 305 includes insulating layers 3051 and sacrificial layers 3052 arranged at intervals. The material of the insulating layer 3051 includes, but is not limited to, one or more of an oxide layer, a nitride layer and a silicon carbide layer; the sacrificial layer 3052 may also be referred to as a dummy gate layer, and the material of the sacrificial layer 3052 includes, but is not limited to, one or more of silicon oxide, silicon nitride layer, and silicon oxynitride; in a subsequent process, the sacrificial layer 3052 may be removed and filled with a gate material (e.g., metal tungsten (W)) at the removed position, and after the gate material is filled, the corresponding position of the sacrificial layer 3052 is referred to as a gate layer.
Here, the CH is the first opening 301, and the CH is used to form a memory layer; the second dielectric layer 307 is a blocking dielectric layer, the blocking dielectric layer is used for blocking charges in the storage layer from flowing out, and the blocking dielectric layer may be made of: an oxide. Here, the thickness consistency of the barrier dielectric layer on the CH side wall is better; the first dielectric layer 301 is a charge trapping layer.
In some embodiments, the epitaxial layer 308 may be formed in the CH first, and then the second dielectric layer 307 may be formed on the sidewalls of the CH. Here, the epitaxial layer 308 serves to electrically connect the channel layer with a well region in the substrate.
In practical application, the steps of forming the final charge trapping layer of the three-dimensional memory are as follows:
step a: as shown in fig. 5b, using ALD process to deposit SIN film 309 (initial charge trapping layer) on the sidewall of the channel hole formed with the blocking dielectric layer; wherein the thickness 302 of the deposited SIN film is larger than the thickness of the final charge trapping layer;
step b: as shown in fig. 5c, a portion of the deposited SIN film is oxidized to OX by using an ISSG process to form an oxide layer 310;
step c: as shown in fig. 5d, a wet etching process is used to remove the portion of the deposited SIN film oxidized to OX to form the final charge trapping layer 309'.
In the embodiment of the invention, when an SIN film is deposited in CH, an SIN deposition layer with a thickness thicker than that to be deposited is deposited; then oxidizing the thicker deposition layer to partially oxidize the SIN deposition layer; and removing the oxidized part in the SIN deposition layer, so that the thickness consistency of the finally obtained SIN deposition layer is good, namely the step coverage rate of the finally obtained charge trapping layer can well meet the process requirement.
It should be noted that: "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In addition, the technical solutions described in the embodiments of the present invention may be arbitrarily combined without conflict.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (8)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate structure; the base structure comprises a first opening; the first opening depth is greater than a preset depth;
forming a first dielectric layer with a first thickness on the side wall of the first opening;
oxidizing the first dielectric layer to form an oxide layer on part of the first dielectric layer;
and removing the oxide layer to obtain a first dielectric layer with a second thickness, wherein the second thickness is smaller than the first thickness.
2. The method of claim 1, wherein the providing a base structure comprises:
providing a semiconductor substrate, wherein a stacked structure formed by alternately stacking an insulating layer and a sacrificial layer is formed on the semiconductor substrate;
forming a plurality of channel holes penetrating through the stacked structure;
the forming a first dielectric layer with a first thickness on the sidewall of the first opening of the channel hole includes:
and forming a first dielectric layer with a first thickness on the side wall of the channel hole.
3. The method of claim 2, further comprising:
forming a second dielectric layer on the side wall of the channel hole before forming a first dielectric layer with a first thickness on the side wall of the channel hole;
the forming of the first dielectric layer with the first thickness on the side wall of the channel hole comprises the following steps:
and forming a first dielectric layer with a first thickness on the surface of the second dielectric layer.
4. The method of claim 1,
forming a first dielectric layer with a first thickness on the side wall of the first opening;
forming a first dielectric layer with a first thickness on the side wall of the first opening by using a low-pressure deposition process;
the step of oxidizing the first dielectric layer comprises the following steps:
and carrying out oxidation treatment on the first dielectric layer by utilizing an ISSG (in-situ steam generation) process.
5. The method of claim 1, wherein the material of the first dielectric layer comprises silicon nitride or polysilicon.
6. The method of claim 1, wherein forming a first dielectric layer of a first thickness on sidewalls of the first opening comprises:
and forming a first dielectric layer with a first thickness on at least the side wall of the first opening by using a chemical vapor deposition method or an atomic layer deposition method.
7. The method of claim 1, wherein the removing the oxide layer comprises:
removing the oxide layer by using a wet etching process; wherein; the wet etching process utilizes a hydrofluoric acid solution to remove the oxide layer.
8. The method of claim 1, wherein a ratio of the first thickness to the second thickness is in a range of 2:1 to 3: 1.
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