CN112909013B

CN112909013B - Three-dimensional memory and method for preparing three-dimensional memory

Info

Publication number: CN112909013B
Application number: CN202110290700.9A
Authority: CN
Inventors: 许波; 严龙翔; 刘力恒; 徐伟; 郭亚丽
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-03-18
Filing date: 2021-03-18
Publication date: 2022-02-18
Anticipated expiration: 2041-03-18
Also published as: CN112909013A

Abstract

The application provides a three-dimensional memory and a method for preparing the same. The method for preparing the three-dimensional memory comprises the following steps: forming a stacked structure on one side of a substrate, and forming a channel structure penetrating the stacked structure and a common source hole having a distance from the channel structure; removing the gate sacrificial layer of the laminated structure through the common source hole to form a gate gap; and sequentially forming a high-resistance material layer, a barrier layer and a conducting layer on the inner wall of the grid gap through the common source hole. The method further comprises the following steps: before forming the barrier layer, the high-resistance material layer is subjected to surface activation treatment. According to the preparation method, the high-resistance material layer is subjected to surface activation treatment before the barrier layer is formed, so that the continuity of the subsequent barrier layer can be increased, the barrier effect of the barrier layer is improved, and the performance of the three-dimensional memory is improved.

Description

Three-dimensional memory and method for preparing three-dimensional memory

Technical Field

The present application relates to the field of semiconductors, and more particularly, to a method for fabricating a three-dimensional memory.

Background

With applications such as solid state drives, the demand for storage capacity of three-dimensional memory is increasing. For three-dimensional memories, increasing the storage capacity often requires increasing the storage density of the memory, which means increasing the density and depth of the channel holes corresponding to the storage regions of the three-dimensional memory.

In practical fabrication processes, an increase in the density of channel holes results in a decrease in the spacing between channel holes. In the step of forming each layer of the gate structure in the gate gap after the subsequent etching of the gate sacrificial layer, the decrease in the distance between the trench holes and the increase in the depth of the trench holes will result in the deterioration of the gas fluidity, and the deposition process of each layer of the film is affected, so that the quality of the film is deteriorated, and the performance of the memory is affected.

Disclosure of Invention

The present application provides a method of fabricating a three-dimensional memory that can at least partially solve the above-mentioned problems in the prior art.

According to an aspect of the present application, there is provided a method of fabricating a three-dimensional memory, the method including: forming a stacked structure on one side of a substrate, and forming a channel structure penetrating the stacked structure and a common source hole having a distance from the channel structure; removing the gate sacrificial layer of the laminated structure through the common source hole to form a gate gap; and sequentially forming a high-resistance material layer, a barrier layer and a conducting layer on the inner wall of the grid gap through the common source hole. The method further comprises the following steps: before forming the barrier layer, the high-resistance material layer is subjected to surface activation treatment.

In an embodiment, sequentially forming the high-resistance material layer, the blocking layer, and the conductive layer on the inner wall of the gate gap may include: sequentially forming a high-resistance material layer, a barrier layer and a conducting layer on the inner wall of the grid gap, the side wall of the common source hole and the part of the substrate overlapped with the common source hole; and removing the high-resistance material layer, the barrier layer and the conductive layer on the side wall of the common source hole and the part of the substrate overlapped with the common source hole.

In an embodiment, the method may further comprise: and forming a common source structure in the common source hole.

In an embodiment, the method may further comprise: through the common source hole, a portion of the substrate overlapping the common source hole is ion-doped to form a common source region.

In an embodiment, the method may further comprise: removing parts of the high-resistance material layer, the barrier layer and the conducting layer, which are positioned on the side wall of the common source hole, and parts of the high-resistance material layer, the barrier layer and the conducting layer, which are positioned at the position of the substrate, which is overlapped with the common source hole; and forming a common source in the position of the substrate overlapped with the common source hole with the high-resistance material layer, the barrier layer and the conducting layer removed and the side wall of the common source hole with the high-resistance material layer, the barrier layer and the conducting layer removed.

In an embodiment, the method may further comprise: and before the common source is formed, forming a dielectric layer on the side wall of the common source hole, from which the high-resistance material layer, the barrier layer and the conducting layer are removed, wherein the dielectric layer is positioned between the side wall of the common source hole and the common source.

In an embodiment, forming a dielectric layer on sidewalls of the common source hole may include: forming a dielectric layer on the side wall of the common source hole and the part of the substrate overlapped with the common source hole; and removing the dielectric layer at the position of the substrate overlapped with the common source electrode hole.

In an embodiment, the surface activation treatment may be performed by soaking the at least high-resistance material layer in a treatment agent, wherein the treatment agent comprises H₂O、H₂O₂、H₂SO₄And HF, or comprise HF and H₂And O. When the treating agent comprises H₂SO₄、H₂O₂、H₂O and HF, and the treatment reagents include: 95 to 98 mol% of H₂O; 1 to 3 mol% of H₂O₂(ii) a 1 to 3 mol% of H₂SO₄(ii) a And HF in a mole percent of 0.02% to 0.1%, wherein the soaking is performed at room temperature and the time of the soaking is 8 seconds to 85 seconds. When the treating agent comprises HF and H₂O, the treating agent comprises: 40 to 60 mole percent HF; and 40 to 60 mole percent of H₂O, wherein the soaking is performed at room temperature, and the time of the soaking is 3 to 40 seconds.

In an embodiment, the number of atoms in a steady state among all the atoms at the surface of the high resistance material layer after the surface activation treatment is larger than the number of atoms in a steady state among all the original values at the surface of the high resistance material layer before the surface activation treatment.

In an embodiment, the energy levels at which all the atoms at the surface of the high resistance material layer are located after the surface activation treatment are closer to each other than the energy levels at which all the atoms at the surface of the high resistance material layer are located before the surface activation treatment.

In an embodiment, the high resistance material layer may include HfO₂Or Al₂O₃. The conductive layer may comprise tungsten. The barrier layer may comprise TiN.

In the implementation method, the Chinese medicine composition can be usedBy using SiH as a reaction gas₄And WF₆Forming a thin tungsten layer and then by using a reaction gas H₂And WF₆To form a final tungsten layer as a conductive layer.

In an embodiment, the method may further comprise: an oxide layer is formed on the exposed substrate prior to forming the high resistance material.

According to another aspect of the present application, there is provided a method of forming a three-dimensional memory based on an interposer, the interposer may include a substrate, a stack structure formed on one side of the substrate, a channel structure penetrating the stack structure, and a common source hole having a spacing from the channel structure, a gate gap being formed in the stack structure, the method including: forming a high-resistance material layer, a barrier layer and a conducting layer in sequence on the inner wall of the gate gap through the common source hole, wherein the method further comprises the following steps: before forming the barrier layer, the high-resistance material layer is subjected to surface activation treatment.

In an embodiment, the substrate may include a common source region at a position corresponding to the common source.

In an embodiment, a dielectric layer may be formed between the stacked structure and the common source.

In an embodiment, an energy level of atoms at a surface of the high resistance material layer in contact with the barrier layer may be substantially uniform.

In an embodiment, an oxide layer is further formed between the channel structure and a conductive layer closest to the substrate among the plurality of conductive layers, and the oxide layer is located between the channel structure and the high-resistance material layer.

According to the method for manufacturing the three-dimensional memory and the three-dimensional memory of the above embodiments, as the high barrier layer is subjected to the surface activation treatment, the energy levels of the atoms at the surface of the high barrier layer are closer to each other (i.e., the surface atoms are at the similar energy levels) and a greater number of atoms are in a stable state (e.g., at least half of the surface atoms are in the stable state or in the vicinity of the stable state), the surface active sites are effectively increased, so that the continuity of the subsequent barrier layer can be increased, the barrier effect of the barrier layer is improved, and the performance of the three-dimensional memory is improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the application and together with the description serve to explain the concepts of the application. In the drawings:

FIG. 1 is a flow chart of a method of fabricating a three-dimensional memory according to an exemplary embodiment of the present application; and

fig. 2 to 11 are schematic views of a process for fabricating a three-dimensional memory according to an exemplary embodiment of the present application.

Detailed Description

The present application will hereinafter be described in detail with reference to the accompanying drawings, and the exemplary embodiments mentioned herein are only for explaining the present application and do not limit the scope of the present application.

The use of cross-hatching and/or shading is typically provided in the figures to clarify the boundaries between adjacent elements. Thus, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, proportions, commonality between illustrated elements, and/or any other characteristic, attribute, property, etc., of an element, unless otherwise specified. Further, in the drawings, the size and relative sizes and shapes of elements may be adjusted for the purpose of clarity and/or description. It is to be understood that the drawings are merely exemplary and are not drawn to scale.

Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, the terms "approximately," "about," and the like are used as approximations, not as degrees of expression, and are intended to account for inherent deviations in measured or calculated values that will be recognized by those of ordinary skill in the art. It should be understood that the expressions first, second, etc. in the present description are only used for distinguishing one feature from another feature, and do not indicate any limitation of the features, particularly any order of precedence.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing" are used in this specification in an open-ended as opposed to a closed-ended fashion, and that such terms are intended to specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to mean exemplary or illustrative.

Further, in this application, when expressions such as "connected," "covered," and/or "formed at …" are used, direct or indirect contact between the respective components may be meant, unless there is an explicit other limitation or can be inferred from the context.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Furthermore, unless otherwise indicated herein, words defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

The various exemplary embodiments may be different, but are not necessarily exclusive. For example, particular shapes, configurations and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the concept of the present application.

Unless otherwise indicated, the illustrated exemplary embodiments should be understood as providing exemplary features of varying detail of some ways in which the inventive concepts may be practiced. Thus, unless otherwise specified, features, molecules, components, modules, layers, films, panels, regions, and/or aspects and the like (individually or collectively, "elements" hereinafter) of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the concepts of the present application.

Various embodiments are described herein with reference to cross-sectional views that are schematic illustrations of embodiments and/or intermediate structures (intermediate pieces). Likewise, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. In addition, the specific structural or functional descriptions disclosed herein are merely illustrative for the purposes of describing embodiments according to the disclosed concept. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes of regions specifically illustrated, but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to be limiting. Moreover, as will be recognized by those of skill in the art, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention

It is to be understood that the specific steps included in the methods described herein are not necessarily limited to the order described, e.g., a particular process order may be performed differently than the order described, unless explicitly defined or contradicted by context. For example, two processes described in succession may be executed substantially concurrently or in the reverse order to that described. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 is a flow chart of a method 1000 of fabricating a three-dimensional memory according to an exemplary embodiment of the present application.

As shown in fig. 1, a method 1000 of fabricating a three-dimensional memory according to an exemplary embodiment of the present application includes the steps of:

s1: a stacked structure is formed on one side of a substrate, and a channel structure and a common source hole having a spacing from the channel structure are formed through the stacked structure. The substrate, the stack structure, the channel structure, and the common source hole form an intermediate for constituting the memory.

S2: removing the gate sacrificial layer of the laminated structure through the common source hole to form a gate gap;

s3: forming a high-resistance material layer on the inner wall of the gate gap through the common source hole;

s4: carrying out surface activation treatment on the high-resistance material layer;

s5: forming a barrier layer on the high-resistance material layer subjected to surface activation treatment;

s6: a conductive layer is formed on the barrier layer.

The stacked structure in the above steps may include a plurality of dielectric layers and a plurality of gate sacrificial layers, but the intermediate member in the present application is not limited thereto. For example, in another example, the stack structure of the above-mentioned intermediate may be a stack structure in which the gate sacrificial layer has been removed through the processing of step S2 to form a gate gap.

The above-described steps S1 to S6 will be described in detail below with reference to the process drawings shown in fig. 2 to 11. For ease of understanding, the structure of the NAND memory is described as an example hereinafter, however, the present application is not limited thereto. As will be appreciated by those skilled in the art, the above-described method may also be applied to other three-dimensional memories having similar structures.

Step S1

The intermediate formed in step S1 may include a substrate 100, a stack structure 110 formed on one side of the substrate 100, a channel structure 120 (which may also extend into the substrate 100) extending through the stack structure 110, and a common source hole 130 spaced apart from the channel structure 120, as shown in fig. 2.

The substrate 100 may, for example, comprise at least one of a silicon (Si) substrate, a germanium substrate (Ge), a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, or other semiconductor materials known in the art. The substrate 100 may be a substrate where a common source region is not formed, but the present application is not limited thereto. For example, the substrate 100 may be a substrate that has been formed with a common source region. Hereinafter, description will be made taking an example in which the common source region is not formed yet in the substrate 100.

The stacked structure 110 includes a plurality of dielectric layers 111 and a plurality of gate sacrificial layers 112 alternately stacked. Multiple purposeThe plurality of dielectric layers 111 are spaced apart from each other by a plurality of gate sacrificial layers 112. Dielectric layer 111 includes, but is not limited to, silicon oxide (SiO)₂) The gate sacrificial layer 112 may be any material having a higher etch selectivity than the dielectric layer 111, such as silicon nitride (SiN), but the embodiment is not limited thereto. The stack structure 110 may be formed on the substrate 100 by a Deposition process such as Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or the like.

The number of layers of the dielectric layer 111 and the gate sacrificial layer 112 is not limited to the number of layers shown in fig. 2, but may be additionally provided as needed, for example, 32 layers, 64 layers, 128 layers, and the like. The dielectric layer 111 and the gate sacrificial layer 112 may be formed by one or more deposition processes. The deposition processes described herein include, but are not limited to, Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or any combination thereof.

It is to be understood that the intermediate may also be a structure in which the gate sacrificial layer 112 has been removed from the stack structure 110 shown in fig. 2 to form a gate gap (for example, refer to "140" in fig. 3). In the case where the stacked structure of the intermediate member includes the dielectric layer and the gate gap, according to another embodiment of the present application, the step S2 may be omitted. Hereinafter, description will be made taking an example in which a gate gap is not formed in the stacked structure 110 (i.e., the stacked structure 110 includes the gate sacrificial layer 112).

Referring to fig. 2, the channel structure 120 may include: an epitaxial structure 121 formed at the bottom of a plurality of channel holes (not shown) extending through the stacked structure 110 and to the substrate 100, an epitaxial dielectric layer (not shown) formed on a surface of the epitaxial structure 121 remote from the substrate 100, and a channel column 122 formed by filling the channel holes.

A trench hole may be formed in the stack 110 by an anisotropic etch (e.g., dry etch such as ion mill etch, plasma etch, reactive ion etch, laser ablation, etc.) process and stopped near below the surface of the substrate 100 (which may be achieved by controlling the etch time).

The epitaxial structure 121 may be, for example, polycrystalline silicon or monocrystalline silicon, and the epitaxial dielectric layer may be, for example, silicon oxide, but the embodiment is not limited thereto.

The channel pillar 122 may include, for example: a blocking dielectric layer 123, a charge storage layer 124, a tunneling dielectric layer 125, and a channel layer 126 formed in sequence on sidewalls of the channel hole. Channel layer 126 may be comprised of doped polysilicon and barrier dielectric layer 123 and tunnel dielectric layer 125 may include, but are not limited to, silicon oxide (SiO)₂) The charge storage layer 124 may be composed of an insulating material containing quantum dots or nanocrystals, for example, silicon nitride (SiN) containing metal or semiconductor particles.

The channel pillar 122 may also include a core insulation layer 127. In an alternative embodiment, the core insulating layer may be omitted from the channel pillar 122. The channel pillar 122 may further include a channel plug 128 at an end away from the substrate 100, and the material of the channel plug 128 may be selected from the same material as the channel layer, but the embodiment is not limited thereto.

It is to be understood that the structure of the channel structure 120 shown above is merely exemplary, and the structure of the channel structure 120 in the method according to the embodiment of the present application is not limited to the above-described structure.

The common-source hole 130 may be formed by employing, for example, an anisotropic etch (e.g., a dry etch such as ion mill etch, plasma etch, reactive ion etch, laser ablation, etc.) process and stops near below the surface of the substrate 100 (which may be achieved by controlling the etch time).

It should be understood that the middleware in the above step S1 is only exemplary, and the semiconductor structure provided in the method according to the embodiment of the present application is not limited thereto. Various other layers for improving the performance of the three-dimensional memory may also be formed over the intermediate member of fig. 2, for example, as long as the intermediate member exists or can form a gate gap.

Step S2

In step S2, the gate sacrificial layer 112 of the stacked structure 110 is removed via the common source hole 130 to form a gate gap 140, as shown in fig. 3.

In this step, the gate sacrificial layer 112 in the stacked structure 110 is removed using, for example, an isotropic etch to form the gate gap 140, using the common source hole 130 as a channel for an etchant. Specifically, the etching is performed with an etchant that has a high etching removal rate for the gate sacrificial layer 112 and hardly removes the dielectric layer 111.

The isotropic etching may be selective wet etching or vapor etching. In wet etching, an etching solution is used as an etchant, and the semiconductor structure is immersed in the etching solution. In vapor phase etching, an etching gas is used as an etchant, and the semiconductor structure is exposed to the etching gas.

The dielectric layer 111 and the gate sacrificial layer 112 in the stacked structure 110 are respectively silicon oxide (SiO)₂) And silicon nitride (SiN), a phosphoric acid solution may be used as an etchant in wet etching, and C may be used in vapor etching₄F₈、C₄F₆、H₂F₂And O₂As an etchant. In the etching step, the common source hole 130 is filled with an etchant, and the gate sacrificial layer 112 is gradually etched toward the inside of the stacked structure 110. Due to the selectivity of the etchant, the etching removes the gate sacrificial layer 112 in the stacked structure 110 and leaves the dielectric layer 111 to form the gate gap 140.

It should be understood that, according to the embodiment of the present application, the middleware in step S1 may also be an middleware having a three-dimensional memory shown in fig. 3. In this case, the above-described step S2 may be omitted.

The intermediate in step S1 may also have a structure as shown in fig. 4, i.e., the oxide layer 150 is formed on the portion of the epitaxial structure 121 of the channel structure 120 exposed by the gate gap 140 and the portion of the substrate 100 exposed by the common source hole. In this embodiment, the above step S2 may be omitted. In the case where the middleware in step S1 is as shown in fig. 2 or 3, in order to prevent bottom select gate leakage, the method of fabricating the three-dimensional memory device may perform an oxidation process on the portion of the substrate 100 exposed by the common source hole 130 and the portion of the epitaxial structure 121 of the channel structure 120 exposed by the gate gap 140 to form the oxide layer 150 before step S3. The oxidation treatment can be carried out, for example, by oxidizing the entire intermediate member in the presence of water (or water vapor) in a high-temperature environment. For example, in the case where the substrate 100 is a silicon substrate, the oxide layer may be a silicon oxide layer.

Referring to fig. 5, according to still another exemplary embodiment of the present application, the intermediate piece in step S1 may also have a structure as shown in fig. 5, that is, an N-type doped common source region 160 may be formed at a portion where the substrate 100 overlaps the common source hole 130. In this embodiment, the above step S2 may be omitted. In the case where the middleware in step S1 is as shown in fig. 2, 3, or 4, the method of fabricating the three-dimensional memory may perform N-type ion implantation on a portion of the substrate 100 overlapping the common source hole 130 using an ion implantation process to form a common source region before step S3.

Step S3

Step S3 is performed on the middleware having or already formed with the gate gap 140, that is, the high resistance material layer 141 is formed on the inner wall of the gate gap 140 via the common source hole 130. In one embodiment, step S3 may be performed on the middleware having or already formed with the gate gap 140, that is, forming a high resistance material layer 141 on the inner wall of the gate gap 140, the sidewall of the common source hole 130, and the portion of the substrate 100 overlapping the common source hole 130 via the common source hole 130, as shown in fig. 6.

The high resistance material layer 141 may be formed by one or more deposition processes. The high-resistance material layer 141 may be, for example, hafnium oxide (HfO)₂) And alumina (Al)₂O₃) But is not limited thereto. The high-resistance material is alumina (Al)₂O₃) In the case of (2), alumina (Al) is formed₂O₃) The aluminum source of (A) may be, for example, Trimethylaluminum (TMA), aluminum chloride (AlCl)₃) Etc., the oxygen source may be, for example, water (H)₂O), ozone (O)₃) And the like. In an exemplary embodiment of the present application, aluminum chloride (AlCl) is used₃) As an aluminum source and employing ozone (O)₃) As an oxygen source, alumina is deposited as the high-resistance material layer 141 by a chemical vapor deposition method at a deposition temperature of, for example, 500 deg.CAnd annealing the formed initial high-resistance material layer after the deposition is completed, for example, at 900 to 1200 c, but the present application is not limited thereto.

Steps S4 and S5

After the high-resistance material layer 141 is formed, step S4, i.e., surface activation processing of the high-resistance material layer 141, may be performed. The surface activation treatment in the present exemplary embodiment may be performed, for example, by immersing at least the high-resistance material layer 141 (or an intermediate member formed with the high-resistance material layer 141) in a treatment agent (the treatment agent is, for example, DSP (which includes H) including H₂SO₄、H₂O₂、H₂O and HF) or DHF (which includes HF and H)₂O)), the DSP or DHF is made to enter into the entire resistive material layer 141 by a siphon effect, so that the surface of the resistive material layer 141 can be cleaned by soaking, so that the energy levels of the atoms at the surface of the treated resistive material layer 141 are closer to each other, and a greater number of surface atoms are in a steady state (for example, at least half of the number of surface atoms are in or near the steady state).

In embodiments of the present application, the DSP may comprise 95 to 98 mole percent H₂O; 1 to 3 mol% of H₂O₂(ii) a 1 to 3 mol% of H₂SO₄(ii) a And 0.02 to 0.1 mole percent HF. In the case of performing the surface activation treatment using DSP, the soaking may be performed at room temperature, and the time of soaking is 8 seconds to 85 seconds, but the present invention is not limited thereto.

In embodiments herein, DHF may include 40 to 60 mole percent HF; and 40 to 60 mole percent of H₂And O. In the case of performing the surface activation treatment using DHF, the soaking may be performed at room temperature, and the time of the soaking is 3 seconds to 40 seconds.

After the high-resistance material layer 141 is subjected to the surface activation process, step S5 may be performed, i.e., the barrier layer 142 is formed on the high-resistance material layer 141 located on the inner wall of the gate gap 140. In one embodiment, referring to fig. 7, a blocking layer 142 may be formed on the high resistance material layer 141 on the inner wall of the gate gap 140, the sidewall of the common source hole 130, and the portion of the substrate 100 overlapping the common source hole 130.

The barrier layer 142 is, for example, but not limited to, at least one of tantalum nitride (TaN), titanium nitride (TiN), or TaN/TiN. The barrier layer 142 may be formed by one or more deposition processes. In an exemplary embodiment of the present application, TiN is deposited as the barrier layer 142 using a chemical vapor deposition method, but the present application is not limited thereto. According to an exemplary embodiment of the present application, TiN is deposited as the barrier layer 142 at a temperature of 400 to 500 c using titanium tetrachloride (TiCl4) and ammonia (NH3) as reaction gases, but the present application is not limited thereto.

Step S6

After forming the barrier layer 142, step S6 may be performed, i.e., the conductive layer 143 is formed as a gate electrode on the barrier layer 142 located on the inner wall of the gate gap 140. In one embodiment, a conductive layer 143 may be formed as a gate on the barrier layer 142 located on the inner wall of the gate gap 140, the sidewall of the common source hole 130, and the portion of the substrate 100 overlapping the common source hole 130, as shown in fig. 8. Conductive layer 143 can be, for example, but not limited to, tungsten, cobalt, copper, nickel, polysilicon, doped silicon, and the like. Conductive layer 143 can be formed by one or more deposition processes. In one exemplary embodiment of the present application, tungsten (W) is formed as the conductive layer 143 using a chemical vapor deposition method, but the present application is not limited thereto. When the conductive layer 143 serving as a gate electrode is formed of tungsten (W), a reducing substance (e.g., SiH, silane) is introduced at an initial stage of forming the conductive layer 143₄Diborane B₂H₆Hydrogen, etc.) with a tungsten source (e.g., tungsten hexafluoride WF)₆Etc.) to allow the two to react. During the reaction, a thin tungsten (W) layer and hydrogen (H) gas are formed₂). The thin tungsten layer can be used as a seed layer for subsequent deposition of a large amount of tungsten (W), and the specific reaction process is as follows:

3SiH₄+2WF₆→2W(s)+3SiF₄+6H₂

after the initial stage, hydrogen (H) may be passed mainly₂) Reduction of tungsten hexafluoride (WF)₆) To deposit the conductive layer 143, the specific reaction process is as follows:

WF₆+3H₂→W(s)+6HF

with hydrogen (H)₂) The reduced product is mainly explained by the radius ratio of hydrogen molecule to Silane (SiH)₄) Is small, and thus, an equiangular deposition and a better step coverage and filling performance can be obtained, but the present application is not limited thereto.

When step S5 is directly performed after step S3 (i.e., the surface activation treatment is not performed on the high-resistance material layer 141, which will be hereinafter referred to as a comparative example), the continuity of the deposited barrier layer 142 is poor, and the barrier effect of the barrier layer 142 is affected. When step S4 is performed immediately after step S3 according to an exemplary embodiment of the present application, continuity of the subsequent barrier layer 142 is improved, thereby improving the blocking effect of the barrier layer 142. With titanium nitride as an example of the barrier layer 142, the porosity of the barrier layer 142 prepared according to an exemplary embodiment of the present application and the barrier layer 142 of the above comparative example under a transmission electron microscope were measured, respectively. The void ratio of the barrier layer 142 in the comparative example (where the high-resistance material layer 141 was not subjected to the surface activation treatment) was approximately 8%. The barrier layer 142 prepared according to the present exemplary embodiment (the surface activation treatment is performed on the high-resistance material layer 141) has a void ratio of approximately 1.5%. As can be seen, after the surface activation treatment is performed on the high-resistance material layer 141, the porosity of the barrier layer 142 formed subsequently is significantly reduced, which also indicates that the continuity of the barrier layer 142 is improved.

The inventors found that, due to surface defects, atoms of the surface of the high-resistance material layer 141 that is not subjected to the surface activation treatment are at energy levels that are not close to each other (surface active sites are small) and the number of atoms in a stable state is small, so that when the barrier layer 142 is subsequently formed on the high-resistance material layer 141, the material constituting the barrier layer 142 may preferentially gather at surface positions where the energy levels are low, thereby causing the nucleation sites of the material constituting the barrier layer 142 to be unevenly distributed, macroscopically appearing as uneven (i.e., poor continuity) of the barrier layer 142. In addition, in the case where the conductive layer 143 is tungsten (W), the conductive layer is formed by reverseResponsive gases (e.g. WF)₆) Fluorine (F) is contained so that fluorine (F) is introduced into the overall structure, especially in some regions where there are few voids. These fluorine (F) may penetrate through the discontinuous locations of the barrier layer 142 (e.g., TiN layer) in subsequent high temperature processes, causing damage to the interlayer thin film oxide layer (e.g., silicon oxide layer), resulting in interlayer leakage. However, the energy levels of the atoms at the surface of the high-resistance material layer 141 subjected to the surface activation treatment are closer to each other (i.e., the surface atoms are at similar energy levels), and a greater number of atoms are in a stable state (e.g., at least half of the number of the surface atoms are in or near the stable state), so that the surface active sites are effectively increased, thereby being capable of increasing the continuity of the subsequent barrier layer 142 and improving the barrier effect of the barrier layer 142.

As is apparent from the above description, when the high-resistance material layer 141, the barrier layer 142, and the conductive layer 143 are formed on the inner wall of the gate gap 140 via the common-source hole 130, in some embodiments, the high-resistance material layer 141, the barrier layer 142, and the conductive layer 143 deposited in the above steps are inevitably formed also on the sidewall of the common-source hole 130, the portion of the substrate 100 overlapping with the common-source hole 130. Therefore, in order to form the final three-dimensional memory, it is also necessary to remove the excess portions of the high-resistance material layer 141, the barrier layer 142, and the conductive layer 143 (the portions located on the sidewalls of the common-source hole 130 and the portion of the substrate 100 overlapping with the common-source hole 130), and then form a common source in the common-source hole 130 (refer to "172" in fig. 11).

An exemplary process of removing the sidewalls of the common source hole 130 and the high resistance material layer 141, the barrier layer 142, and the conductive layer 143 on the portion of the substrate 100 overlapping the common source hole 130 to form the common source will be described below with reference to fig. 9 to 11. According to an exemplary embodiment of the invention, the barrier layer 142 and the conductive layer 143 on the sidewall of the common source hole 130 and the portion of the substrate 100 overlapping the common source hole 130 may be removed by wet etching (e.g., etching back the sidewall of the common source hole 130 and the portion of the substrate 100 overlapping the common source hole 130 by a high temperature mixed acid). Alternatively, in other embodiments, when the conductive layer 143 is formed of tungsten (W), the intermediate piece on which the high-resistance material layer 141, the barrier layer 142, and the conductive layer 143 are formed may be placed in a furnace tube to perform oxygen-containing annealing, so that tungsten oxide is formed on the surface of the tungsten, the oxidized tungsten is removed by an acid solution (e.g., hydrofluoric acid), and the conductive layer 143 and the barrier layer 142 on the sidewall of the common-source hole 130 and the portion of the substrate 100 overlapping the common-source hole 130 are removed by using a solution having a high selectivity to the conductive layer 143 and the barrier layer 142. The process may also cause portions of conductive layer 143 and barrier layer 142 in gate gap 140 adjacent to common source hole 130 to be removed to form a recessed shape.

Next, the high blocking material layer 141 on the sidewall of the common source hole 130 and the portion of the substrate 100 overlapping the common source hole 130 may be removed by dry etching (for example, etching back the sidewall of the common source hole 130 and the portion of the substrate 100 overlapping the common source hole 130 by a high-temperature mixed acid). The process may also cause portions of the high blocking material layer 141 in the gate gap 140 adjacent to the common source hole 130 to be removed to form a recessed shape, as shown in fig. 9.

According to an exemplary embodiment of the present application, a common source located on a portion of the substrate 100 overlapping the common source hole 130 and a sidewall of the common source hole 130 may be formed in the common source hole 130 (refer to "172" in fig. 11), for example, using a chemical vapor deposition process or a high temperature furnace growth process.

Referring to fig. 10 and 11, according to an exemplary embodiment of the present application, before forming the common source 172, a dielectric layer 171 may be further formed on the sidewall of the common source hole 130 from which the high resistance material layer 141, the barrier layer 142, and the conductive layer 143 are removed, wherein the dielectric layer 171 is located between the sidewall of the common source hole 130 and the common source 172. The dielectric layer 171 is, for example, a silicon oxide layer. The conductive layer of the common source 172 is, for example, the same material as or a different material from the material of the conductive layer 143 as the gate.

In an exemplary embodiment of the present application, forming the dielectric layer 171 on the sidewall of the common source hole 130 may be achieved, for example, by the following process: forming a dielectric layer 171 on the sidewall of the common source hole 130 and a portion of the substrate 100 overlapping the common source hole 130; and removing the dielectric layer 171 on the portion of the substrate 100 overlapping the common source hole 130. The dielectric layer 171 on the portion of the substrate 100 overlapping the common source hole 130 may be removed, for example, by dry etching. In the dry etching, the oxide layer 150 on the portion of the substrate 100 overlapping the source hole 130 may also be removed together with the dielectric layer 171, but the present application is not limited thereto.

It should be understood that the common source region 160 may also be formed after removing the redundant high resistance material layer 141, the blocking layer 142, and the conductive layer 143, and before forming the common source electrode 172 or the dielectric layer 171, and the forming sequence of the common source region 160 in the present application is not limited by the above-described processes.

The three-dimensional memory manufactured by the above process includes: a substrate 100; a stacked structure on one side of the substrate, the stacked structure including a plurality of conductive layers 143 and a plurality of dielectric layers 111 alternately stacked; a channel structure 120 extending through the stack; a common source 172 extending through the stack structure and into the substrate 100, the common source 172 being spaced apart from the channel structure 120. A high-resistance material layer 141 and a barrier layer 142 are formed between the conductive layer 143 and the dielectric layer 111 and between the conductive layer 143 and the channel structure 120, the barrier layer 142 is located between the high-resistance material layer 141 and the conductive layer 143, and a surface of the high-resistance material layer 141, which is in contact with the barrier layer 142, is subjected to surface activation processing.

A dielectric layer 171 may be formed between the stacked structure and the common source 172. The energy level of atoms at the surface of the high-resistance material layer 141 in contact with the barrier layer 142 may be approximately uniform.

An oxide layer 150 may also be formed between the channel structure 120 and the conductive layer 142 closest to the substrate 110 among the plurality of conductive layers 143, and the oxide layer 150 is located between the channel structure 120 and the high-resistance material layer 141.

It should also be understood that the structure between the sidewall of the common source hole 130 and the common source 172 is not limited to the above-described structure, for example, the layer between the sidewall of the common source hole 130 and the common source 172 is not limited to the above-described dielectric layer 171, and may also include other layers having a blocking function or a protection function.

In addition, the structures in the process diagrams illustrated above with reference to fig. 2 to 11 are applied to the three-dimensional memory described above, and further description of the respective components for the three-dimensional memory illustrated in the drawings is omitted here for the sake of brevity.

In the above embodiments, the three-dimensional memory device of a single stack structure is described as an example, but it should be understood that the concept of the present application can be applied to a three-dimensional memory device of a multi-stack structure, for example, a three-dimensional memory device of a dual stack structure.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A method of fabricating a three-dimensional memory, the method comprising:

forming a stacked structure on one side of a substrate and forming a channel structure penetrating the stacked structure and a common source hole having a spacing from the channel structure;

removing the gate sacrificial layer of the laminated structure to form a gate gap through the common source hole;

sequentially forming a high-resistance material layer, a barrier layer and a conductive layer on the inner wall of the gate gap through the common source hole,

wherein the method further comprises:

before forming the barrier layer, subjecting the high-resistance material layer to a surface activation treatment so that at least one of:

the number of atoms in a steady state among all atoms at the surface of the high-resistance material layer after the surface activation treatment is larger than the number of atoms in a steady state among all atoms at the surface of the high-resistance material layer before the surface activation treatment; and

all the atoms at the surface of the high-resistance material layer after the surface activation treatment are located at energy levels closer to each other than the energy levels at the surface of the high-resistance material layer before the surface activation treatment.

2. The method of claim 1, wherein the first and second light sources are selected from the group consisting of,

wherein, form high resistant material layer, barrier layer and conducting layer in proper order on the inner wall in grid clearance includes:

sequentially forming a high-resistance material layer, a barrier layer and a conducting layer on the inner wall of the grid gap, the side wall of the common source hole and the part of the substrate overlapped with the common source hole; and

removing the high-resistance material layer, the barrier layer and the conductive layer on the side wall of the common source hole and the part of the substrate overlapped with the common source hole, and

wherein the method further comprises forming a common source structure within the common source hole.

3. The method according to claim 1, wherein the surface activation treatment is performed by soaking at least the high resistance material layer in a treatment agent, wherein the treatment agent comprises H₂O、H₂O₂、H₂SO₄And HF, or comprise HF and H₂O。

4. The method of claim 3, wherein when the treatment agent comprises H₂O、H₂O₂、H₂SO₄And HF, the treatment reagents include:

95 to 98 mol% of H₂O；

1 to 3 mol% of H₂O₂；

1 to 3 mol% of H₂SO₄(ii) a And

0.02 to 0.1 mole percent HF.

5. The method of claim 4, wherein the soaking is performed at room temperature and the time of the soaking is 8 to 85 seconds.

6. The method of claim 3, wherein when the treatment agent comprises HF and H₂O, the treatment reagent comprises:

40 to 60 mole percent HF; and

40 to 60 mol% of H₂O。

7. The method of claim 6, wherein the soaking is performed at room temperature and the soaking time is 3 to 40 seconds.

8. The method of claim 1, wherein the high resistance material layer comprises HfO₂Or Al₂O₃The barrier layer comprises TiN.

9. The method of claim 1, wherein the conductive layer comprises tungsten.

10. The method of claim 9, wherein the SiH is generated by using a reaction gas₄And WF₆Forming a thin tungsten layer and then by using a reaction gas H₂And WF₆To form a final tungsten layer as the conductive layer.

11. A method of forming a three-dimensional memory based on an interposer, the interposer comprising a substrate, a stack structure formed on one side of the substrate, a channel structure extending through the stack structure, and a common source hole having a spacing from the channel structure, the stack structure having a gate gap formed therein, the method comprising:

wherein the method further comprises:

12. A three-dimensional memory, the three-dimensional memory comprising:

a substrate;

a stacked structure on one side of the substrate, the stacked structure including a plurality of conductive layers and a plurality of dielectric layers alternately stacked;

a channel structure penetrating the stacked structure;

a common source extending through the stack structure and into the substrate, the common source spaced from the channel structure, an

Wherein a high resistance material layer and a barrier layer are formed between the conductive layer and the dielectric layer and between the conductive layer and the channel structure,

wherein the barrier layer is located between the high-resistance material layer and the conductive layer, and a surface of the high-resistance material layer in contact with the barrier layer is subjected to surface activation treatment so as to satisfy at least one of:

13. The three-dimensional memory according to claim 12, wherein at least half of the number of atoms at the surface of the high resistance material layer in contact with the barrier layer are in a steady state.

14. The three-dimensional memory of claim 12, wherein the high resistance material layer comprises HfO₂Or Al₂O₃The barrier layer comprises TiN and the conductive layer comprises tungsten.