CN105514100B - Semiconductor element and its manufacturing method - Google Patents
Semiconductor element and its manufacturing method Download PDFInfo
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- CN105514100B CN105514100B CN201410497745.3A CN201410497745A CN105514100B CN 105514100 B CN105514100 B CN 105514100B CN 201410497745 A CN201410497745 A CN 201410497745A CN 105514100 B CN105514100 B CN 105514100B
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Abstract
The invention discloses a kind of manufacturing methods of semiconductor element.In forming multiple gate structures in substrate, and the first dielectric layer is formed between two neighboring gate structure；The upper surface of first dielectric layer is lower than the upper surface of gate structure, and has groove；The middle layer of covering gate structure, the first dielectric layer and groove is re-formed, and in wherein forming multiple openings；Each opening removes the first dielectric layer between two neighboring gate structure, and via opening；Then, in forming the second dielectric layer in middle layer, to define the air gap between two neighboring gate structure.The present invention also proposes a kind of semiconductor element.
Description
Technical field
The invention relates to a kind of semiconductor element and its manufacturing methods.
Background technique
Under the trend for improving semiconductor element integrated level at present, the size of element can be reduced according to design rule.However,
As size is more and more small, capacitance-resistance postpones (resistor-capacitor delay, RC delay) and respectively forms structure
Electrical property between part interferes the limited speed so that integrated circuit, and influences its reliability and stability.Therefore, capacitance-resistance
The problem of semiconductor element working efficiency caused by delay reduces, is current urgent need to resolve.
Summary of the invention
The present invention provides a kind of manufacturing method of semiconductor element, forms the air gap between gate structure, and energy
The capacitance-resistance delay being enough effectively prevented between gate structure, and improve the electrical interference between each composition component, with into one
Step promotes the efficiency of semiconductor element.
The manufacturing method of semiconductor element of the invention is as follows.In forming multiple gate structures in substrate, and in adjacent two
The first dielectric layer is formed between a gate structure, upper surface is lower than the upper surface of gate structure, and has the first groove.It connects
, the middle layer of covering gate structure, the first dielectric layer and the first groove is formed, and in wherein forming multiple openings, Mei Yikai
Mouth is between two neighboring gate structure.Via opening to remove the first dielectric layer between two neighboring gate structure.Most
Afterwards, in forming the second dielectric layer in middle layer, to define the air gap between two neighboring gate structure.
In one embodiment of this invention, the manufacturing method of the semiconductor element, wherein on every one first groove
Interbed has the second groove.At this point, between the side wall that the method for forming opening in middle layer is included in every one second groove is formed
Gap wall, to expose middle layer.Part middle layer is removed as mask using clearance wall, to form these openings, then removes gap
Wall.
In one embodiment of this invention, the manufacturing method of the semiconductor element, wherein forming the method packet of middle layer
It includes in forming the first intermediate layer of material on gate structure and the first dielectric layer, and in being formed among second in the first intermediate layer of material
Material layer, wherein the material of the second intermediate layer of material is different from the first intermediate layer of material, and different from the material of clearance wall.
In one embodiment of this invention, the manufacturing method of the semiconductor element, wherein being removed via a little openings adjacent
When the first dielectric layer between two gate structures, the first intermediate layer of material of part removed on the first dielectric layer is further included.
In one embodiment of this invention, the manufacturing method of the semiconductor element, wherein forming the first intermediate materials
Before layer, further includes and carry out a silication technique for metal, in forming metal silicide layer on the gate conductor layer of each gate structure, and
The height of the air gap is higher than the upper surface of gate conductor layer.
The present invention also proposes a kind of structure of semiconductor element, including the multiple gate structures being configured in substrate, is located at
The middle layer above substrate on gate structure and between two neighboring gate structure, and the dielectric in middle layer
Layer.Wherein there is between two neighboring gate structure the air gap.
In one embodiment of this invention, the structure of the semiconductor element, wherein each the air gap includes by adjacent
The side walls of two gate structures, principal space defined in substrate surface and middle layer, and be located on principal space, by
Protrusion space defined in middle layer and dielectric layer.
In one embodiment of this invention, the structure of the semiconductor element, wherein middle layer includes being located at gate structure
Surface and side wall on the first intermediate layer of material, and the second intermediate layer of material in the first intermediate layer of material, Yu Xiang
There is opening between adjacent two gate structures, wherein the material of the second intermediate layer of material is different from the first intermediate layer of material.
In one embodiment of this invention, the structure of the semiconductor element, wherein each gate structure includes that grid is led
Body layer and metal silicide layer, the height of principal space are greater than the height of grid conductor layer surface.
In one embodiment of this invention, the structure of the semiconductor element, wherein the volume of each the air gap is phase
5% to 95% of gap between adjacent two gate structures.
It, can be between two neighboring gate structure based on the manufacturing method of above-mentioned, proposed by the invention semiconductor element
The height for forming the air gap, and being formed by the air gap is higher than the upper surface of the gate conductor layer of gate structure, therefore can
The capacitance-resistance delay being effectively prevented between gate structure, and improve the electrical interference between each composition component, and it is further
Promote the efficiency of semiconductor element.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and cooperate institute's accompanying drawings
It is described in detail below.
Detailed description of the invention
Figure 1A to Fig. 1 K is the manufacturing process diagrammatic cross-section according to semiconductor element depicted in the embodiment of the present invention.
[symbol description]
10: substrate
12: dielectric materials layer
12a, 16,28: dielectric layer
13rd: the first area
15th: the second area
14: stop-layer
20: middle layer
22: the first intermediate layer of material
24: the second intermediate layer of material
26: material layer
26a: clearance wall
30,50: gate structure
32,52: gate conductor layer
34,54: electric charge storage layer
36,56: hard mask layer
38,58: metal silicide layer
40: the first grooves
42: the air gap
42a: principal space
42b: raised space
44: the second grooves
46: opening
48: hole
Specific embodiment
Figure 1A to Fig. 1 J is the manufacturing process diagrammatic cross-section according to semiconductor element depicted in the embodiment of the present invention.
Figure 1A is please referred to, substrate 10 is provided, substrate 10 is, for example, semiconductor base, semiconducting compound substrate or insulation
There is semiconductor base (Semiconductor Over Insulator, SOI) on layer.Semiconductor is, for example, the atom of IVA race, example
Such as silicon or germanium.Semiconducting compound is, for example, that the atom of IVA race is formed by semiconducting compound, e.g. silicon carbide or silicon
Change germanium or Group IIIA atom and VA race atom is formed by semiconducting compound, e.g. GaAs.Substrate 10 includes first
Area 13 and the second area 15.In one embodiment, the first area 13 is, for example, memory cell areas, and the second area 15 is, for example, peripheral circuit
Area.
Then, please continue to refer to Figure 1A, in forming multiple gate structures 30,50 in substrate 10.Gate structure 30,50 is at least
Including gate conductor layer 32,52.The material of gate conductor layer 32 can be conductor, e.g. DOPOS doped polycrystalline silicon.In addition, such as Figure 1A
Shown, gate structure 30,50 can further include dielectric layer 34,54, positioned at corresponding grid conducting layer 32,52 and substrate 10 it
Between.In one embodiment, semiconductor element is, for example, memory element, and dielectric layer 34,54 is, for example, electric charge storage layer.Charge storage
Depositing layer can be laminated construction, e.g. ONO (oxide-nitride-oxide) layer, that is, including silica/nitridation
Three layers of silicon/oxidative silicon.On the other hand, as shown in Figure 1A, gate structure 30,50 can further include hard mask layer 36,56, be located at and correspond to
Gate conductor layer 32,52 on.The material of hard mask layer 36,56 may, for example, be silica, silicon oxynitride or silicon nitride.
Then, please continue to refer to Figure 1A, dielectric materials layer 12 is formed, on the substrate 10 to cover on gate structure 30,50
Hard mask layer 36,56.There is hole 48 in dielectric materials layer 12 between the two neighboring gate structure 30 in the first area 13.?
In one embodiment, the height of hole 48 is greater than the height on 32 surface of gate conductor layer.The material of dielectric materials layer 12 is, for example, oxygen
SiClx, phosphorosilicate glass, boron-phosphorosilicate glass or combinations thereof.The forming method of dielectric materials layer 12 is, for example, high-density plasma
It learns vapour deposition process (HDP-CVD).
Next, please referring to Figure 1A and Figure 1B, anisotropic etching is carried out to dielectric materials layer 12, to remove part dielectric
Material layer 12 exposes the top of hard mask layer 36 and 56.Later, stopping is sequentially formed on etched dielectric materials layer 12
Layer 14 and dielectric layer 16.The material of stop-layer 14 is different from dielectric materials layer 12, and different from dielectric layer 16.The material of stop-layer 14
Material e.g. silicon nitride, silicon oxynitride, carbon silicon oxynitride or silicon carbide, forming method is, for example, chemical vapour deposition technique or atom
Layer sedimentation (ALD).The material of dielectric layer 16 is, for example, silica, and forming method is, for example, high-density plasma chemical gas phase
Sedimentation.
Figure 1B and Fig. 1 C are please referred to, a flatening process is carried out to dielectric layer 16, until exposing stop-layer 14.It is described flat
Chemical industry skill is, for example, chemical mechanical milling method.Next, Fig. 1 C and Fig. 1 D are please referred to, removal stop layer 14 and hard mask layer
36,56, to expose gate conductor layer 32,52.The method of removal is, for example, wet type etch method or Siconi etching method, but not with
This is limited.Later, Fig. 1 D and Fig. 1 E are please referred to, the dielectric materials layer 12 between two neighboring gate structure 30,50 is returned
Etching, to form dielectric layer 12a.The upper surface of dielectric layer 12a is lower than the upper surface of gate conductor layer 32,52, and the first area 13
Two neighboring gate structure 30 between dielectric layer 12a in have the first groove 40.
Then, please refer to Fig. 1 F, carry out silication technique for metal, in the gate conductor layer 32 of each gate structure 30,50,
Metal silicide layer 38,58 is formed on 52.The material of metal silicide layer 38,58 may, for example, be titanium, tungsten, cobalt, nickel, copper, molybdenum, tantalum,
The silicide of erbium, zirconium or platinum.In one embodiment, the material of metal silicide layer 38,58 is, for example, cobalt silicide (Cobalt
Silicide, CoSi).At this point, the silication technique for metal e.g. first deposits one layer of cobalt, later, the first quick thermal technology is carried out
Skill (Rapid Thermal Process, RTP) then carries out cobalt silicide selective etch, removes unreacted cobalt, Zhi Houzai
The second rapid hot technics are carried out, so that the pasc reaction in cobalt and gate conductor layer 32,52, using forming material as the silication of cobalt silicide
Metal layer 38,58.
Fig. 1 G is please referred to, middle layer 20 is formed.Middle layer 20 cover dielectric layer 12a, the first groove 40 with gate structure
30, the metal silicide layer 38,58 on 50, and the middle layer 20 on every one first groove 40 has the second groove 44.Later, it is formed
Material layer 26, to be covered in middle layer 20.In one embodiment, middle layer 20 is a laminated construction, by the first intermediate materials
Layer 22 is formed with the second intermediate layer of material 24.The forming method of middle layer 20 and material layer 26 is included in gate structure 30,50
On metal silicide layer 38,58 and dielectric layer 12a on be initially formed the first intermediate layer of material 22, in the first intermediate layer of material 22
Form the second intermediate layer of material 24 and then forming material layer 26.First intermediate layer of material 22 and the second intermediate layer of material 24
Material is different.The material of first intermediate layer of material 22 is, for example, silica, phosphorosilicate glass, boron-phosphorosilicate glass or combinations thereof, is formed
Method be, for example, chemical vapour deposition technique.The material of second intermediate layer of material 24 is, for example, silicon nitride, silicon oxynitride, carbon nitrogen oxygen
SiClx or silicon carbide, forming method are, for example, chemical vapour deposition technique or atomic layer deposition method.In an exemplary embodiment, first
The material of intermediate layer of material 22 is, for example, silica, and the material of the second intermediate layer of material 24 is, for example, silicon nitride, material layer 26
It is identical as the material of the first intermediate layer of material 22, such as be all silica, but the present invention is not limited thereto.
Fig. 1 G and Fig. 1 H is please referred to, anisotropic etching is carried out to material layer 26, in the side of every one second groove 44
Wall forms clearance wall 26a, exposes middle layer 20.Later, Fig. 1 H and Fig. 1 I are please referred to, due to being covered on the first groove 40
The thickness of middle layer 20 (the second intermediate layer of material 24) is very thin, therefore using clearance wall 26a as mask, can be with easy removal
The middle layer 20 exposed, to form multiple openings 46 in the middle layer 20 in the first area 13, and each opening 46 is positioned at adjacent
Between two gate structures 30.Later, the first area 13 is removed via opening 46 is formed by please continue to refer to Fig. 1 I and Fig. 1 J
Two neighboring gate structure 30 between dielectric layer 12a.In another embodiment, as shown in figure I and Fig. 1 J, via opening 46
When removing the dielectric layer 12a between the two neighboring gate structure 30 in the first area 13, while it can also remove the dielectric in the first area 13
The first intermediate layer of material of part 22 and clearance wall 26a on layer 12a.Remove clearance wall 26a, two neighboring gate structure 30 it
Between dielectric layer 12a and the first area 13 dielectric layer 12a on the method for the first intermediate layer of material of part 22 may, for example, be
Wet type etch method or Siconi etching method, but not limited to this.
Fig. 1 J and Fig. 1 K are please referred to, in forming dielectric layer 28 in middle layer 20, in the two neighboring grid in the first area 13
The air gap 42 is defined between structure 30.The material of dielectric layer 28 be, for example, silica, phosphorosilicate glass, boron-phosphorosilicate glass or its
Combination.And the forming method of dielectric layer 28 is, for example, high density plasma CVD method.
Fig. 1 K is please referred to, the structure of semiconductor element according to an embodiment of the present invention includes substrate 10, multiple gate structures
30 and 50, middle layer 20, dielectric layer 28 and the air gap 42.Multiple gate structures 30,50 are configured in substrate 10, and each
Gate structure 30,50 includes at least gate conductor layer 32,52 and metal silicide layer 38,58.Middle layer 20 is located at gate structure
30,10 top of substrate on 50 and between two neighboring gate structure 30,50.Dielectric layer 28 is located in middle layer 20.
Please continue to refer to Fig. 1 K, an embodiment according to the present invention, middle layer 20 is a laminated construction, by the first intermediate wood
The bed of material 22 is formed with the second intermediate layer of material 24.First intermediate layer of material 22 is located at the surface and part of gate structure 30,50
On side wall.Second intermediate layer of material 24 is then located in the first intermediate layer of material 22.First intermediate layer of material 22 and the second intermediate wood
The material of the bed of material 24 is different.
Please continue to refer to Fig. 1 K, the air gap 42 is between two neighboring gate structure 30, wherein each the air gap
42 volume is, for example, 5% to 95% of the gap between two neighboring gate structure 30.An embodiment according to the present invention, it is empty
Gas gap 42 is for example including principal space 42a and protrusion space 42b.Principal space 42a is by two adjacent gate structures 30
It is defined with the side wall of metal silicide layer 38, the surface of substrate 10 and middle layer 20, and the height of principal space 42a is greater than grid
The height on 32 surface of pole conductor layer.Raised space 42b is located on principal space 42a, by middle layer 20 and dielectric layer 28
It is defined.The shape of principal space 42a is, for example, rectangle, ladder type or combinations thereof；The shape of raised space 42b is, for example, triangle
Shape, arch or combinations thereof, but not limited to this.In one embodiment, the shape of principal space 42a is, for example, rectangle；It is raised empty
Between the shape of 42b be, for example, arch.Since the height of the principal space 42a of the air gap 42 is greater than 32 surface of gate conductor layer
Highly, therefore, it can be effectively prevented from and caused interference is connected between gate structure.
In conclusion the manufacturing method of semiconductor element provided by the invention, it can be between two adjacent gate structures
The air gap is formed, moreover, the height for being formed by the air gap is greater than the height of the gate conductor layer of gate structure.Therefore,
It can prevent the capacitance-resistance between gate structure from postponing, and improve the electrical interference between each composition component, and sufficiently be promoted
The efficiency of semiconductor element.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any technical field
Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, thus it is of the invention
Protection scope subject to be defined depending on appended claims range.
Claims (9)
1. a kind of manufacturing method of semiconductor element, comprising:
In forming multiple gate structures in a substrate；
One first dielectric layer is formed between two neighboring gate structure, the upper surface of first dielectric layer is lower than these grid knots
The upper surface of structure, and there is one first groove；
In forming a middle layer in substrate, these gate structures, first dielectric layer and these first grooves, the middle layer are covered
With one second groove on first groove；
In forming a material layer in the middle layer, anisotropic etching is carried out to the material layer, in the side wall of second groove
Clearance wall is formed, which exposes the middle layer；
With clearance wall as mask, the middle layer exposed is removed, forms multiple openings, each opening is located at two neighboring grid
Between the structure of pole；
Via these openings, first dielectric layer and these clearance walls between two neighboring gate structure are removed；And
In forming one second dielectric layer in the middle layer, wherein two neighboring gate structure, the second dielectric layer and the middle layer
A air gap is defined, and the height of the air gap is higher than the upper surface of the gate conductor layer of gate structure.
2. the manufacturing method of semiconductor element according to claim 1, wherein the method for forming the middle layer includes:
In one first intermediate layer of material of formation on these gate structures and first dielectric layer；And
In forming one second intermediate layer of material in first intermediate layer of material, wherein the material of second intermediate layer of material and this
One intermediate layer of material is different, and different from the material of the clearance wall.
3. the manufacturing method of semiconductor element according to claim 2, wherein removing two neighboring grid via these openings
When first dielectric layer between the structure of pole, part first intermediate layer of material removed on first dielectric layer is further included.
4. the manufacturing method of semiconductor element according to claim 3, wherein before forming first intermediate layer of material,
It further includes and carries out a silication technique for metal, in forming a metal silicide layer on a gate conductor layer of each gate structure.
5. a kind of semiconductor element, comprising:
Multiple gate structures are configured in a substrate；
One middle layer, above the substrate on these gate structures and between two neighboring gate structure, the middle layer
Including one first intermediate layer of material, on the surface of these gate structures and side wall and one second intermediate layer of material, it is located at
In first intermediate layer of material, first intermediate layer of material and second intermediate layer of material are between two neighboring gate structure
With an opening；And
One dielectric layer is located in the middle layer,
Wherein, two neighboring gate structure, dielectric layer and the middle layer define a air gap, and the height of the air gap
Degree is higher than the upper surface of the gate conductor layer of gate structure.
6. semiconductor element according to claim 5, wherein each the air gap includes:
One principal space is defined by the side wall, the substrate surface and the middle layer of two adjacent gate structures；And
One raised space, is located on the principal space, is defined by the middle layer and the dielectric layer.
7. semiconductor element according to claim 6, the wherein material of second intermediate layer of material and first intermediate wood
The bed of material is different.
8. semiconductor element according to claim 5, wherein each gate structure includes a gate conductor layer and a silication
Metal layer.
9. the manufacturing method of semiconductor element according to claim 5, wherein the volume of each the air gap is adjacent two
5% to 95% of gap between a gate structure.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1791974A (en) * | 2003-05-21 | 2006-06-21 | 桑迪士克股份有限公司 | Use of voids between elements in semiconductor structures for isolation |
| TW201417188A (en) * | 2012-10-25 | 2014-05-01 | Macronix Int Co Ltd | Airgap structure and method of manufacturing thereof |
| US8765572B2 (en) * | 2010-06-25 | 2014-07-01 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
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| KR20120031667A (en) * | 2010-09-27 | 2012-04-04 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing semiconductor devices |
| KR101692403B1 (en) * | 2010-12-16 | 2017-01-04 | 삼성전자주식회사 | Methods of manufacturing a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1791974A (en) * | 2003-05-21 | 2006-06-21 | 桑迪士克股份有限公司 | Use of voids between elements in semiconductor structures for isolation |
| US8765572B2 (en) * | 2010-06-25 | 2014-07-01 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
| TW201417188A (en) * | 2012-10-25 | 2014-05-01 | Macronix Int Co Ltd | Airgap structure and method of manufacturing thereof |
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