CN112103267A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
CN112103267A
CN112103267A CN202011154069.1A CN202011154069A CN112103267A CN 112103267 A CN112103267 A CN 112103267A CN 202011154069 A CN202011154069 A CN 202011154069A CN 112103267 A CN112103267 A CN 112103267A
Authority
CN
China
Prior art keywords
dielectric layer
active region
layer
top surface
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011154069.1A
Other languages
Chinese (zh)
Inventor
韦仕贡
谢小明
陈兆震
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Yandong Microelectronic Technology Co ltd
Original Assignee
Beijing Yandong Microelectronic Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Yandong Microelectronic Technology Co ltd filed Critical Beijing Yandong Microelectronic Technology Co ltd
Priority to CN202011154069.1A priority Critical patent/CN112103267A/en
Publication of CN112103267A publication Critical patent/CN112103267A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor device and a method for manufacturing the same are disclosed, the semiconductor device includes a substrate, an active region is arranged in the substrate, and the active region is positioned on the top of the substrate; further comprising: the dielectric layer is positioned on the top surface of the substrate, a through hole is formed in the dielectric layer and positioned on the top surface of the active region, and the thickness of the part, far away from the active region, of the dielectric layer is larger than that of the part, close to the active region, of the dielectric layer; and the metal layer is positioned on the top surface of the dielectric layer, extends downwards to the upper part of the active area through the side surface of the dielectric layer and fills the through hole to form electric connection with the active area. According to the semiconductor device and the manufacturing method thereof, the dielectric layer is arranged on the surface of the substrate, the through hole is formed in the position, corresponding to the active region, of the dielectric layer, the thickness of the part, close to the active region, of the dielectric layer is smaller than that of the part, far away from the active region, of the dielectric layer, so that the metal layer can extend to the active region through the side surface of the dielectric layer, the through hole is filled to form electric connection, the structure and the manufacturing process of the device are simplified, the processing difficulty of the.

Description

Semiconductor device and manufacturing method thereof
Technical Field
The invention relates to the technical field of microelectronics, in particular to a semiconductor device and a manufacturing method thereof.
Background
The structure of the conventional semiconductor device generally includes a semiconductor substrate, an active region located in the semiconductor substrate, a metal layer (a metal wiring layer or an extraction electrode) located above the semiconductor substrate, and an insulating dielectric layer located between the semiconductor substrate and the metal layer. The insulating medium layer is also provided with a through hole, and conductive materials such as titanium, titanium nitride, tungsten and the like are filled in the through hole so as to realize the electric connection between the source region and the metal layer. In such a semiconductor structure, a parasitic MOS capacitor is often formed between the semiconductor substrate and the metal layer. The size of the parasitic capacitance is determined by the thickness of the insulating dielectric layer, the dielectric constant of the insulating dielectric layer and the area of the metal layer. When the parasitic capacitance is large to a certain extent, parameters such as frequency response of the semiconductor device can be affected, and the performance of the product is reduced.
In order to solve the above problems, it is common to increase the thickness of the insulating dielectric layer to reduce the parasitic capacitance. However, the increase of the thickness of the insulating medium layer can also cause the depth-to-width ratio of the through hole to be increased, on one hand, the etching difficulty of the through hole can be increased, and etching residues can be easily caused; on the other hand, the filling difficulty of the through hole is increased, complete filling is difficult to realize, a cavity is easy to form, and the yield of the device is reduced.
Of course, there is also a method of reducing the process difficulty by fabricating a plurality of thin insulating dielectric layers and forming through holes for a plurality of times, and then filling conductive materials in the through holes to electrically connect the through holes, but the process is complicated and the cost is high.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which can simplify the structure and the manufacturing process of the device, reduce the processing difficulty of the device and improve the yield of products while reducing parasitic capacitance.
In order to achieve the above object, according to a first aspect of the present invention, there is provided a semiconductor device comprising a substrate having an active region disposed therein, the active region being located on top of the substrate; further comprising:
the dielectric layer is positioned on the top surface of the substrate, a through hole is formed in the dielectric layer and positioned on the top surface of the active region, and the thickness of the part, far away from the active region, of the dielectric layer is larger than that of the part, close to the active region, of the dielectric layer;
and the metal layer is positioned on the top surface of the dielectric layer, extends downwards to the upper part of the active area through the side surface of the dielectric layer and fills the through hole to form electric connection with the active area.
Further, the dielectric layer is stepped, the side surface of the step comprises an inclined surface, and the metal layer extends downwards from the top surface of the step to the position above the active region through the inclined surface.
Further, the medium layer has two steps, wherein the side surface of the upper step comprises the inclined surface; the metal layer extends from the top surface of the upper step down onto the top surface of the lower step through the inclined surface and fills the through-hole to be electrically connected with the active region.
Further, the top of the inclined plane is connected with the top surface of the upper step, and the bottom of the inclined plane is connected with the top surface of the lower step; the total height of the two steps is 100%, and the height of the upper step is 70-95% of the total height.
Furthermore, the height of the lower step is 0.6-1.5 μm.
Further, the metal layer in the through hole is in direct contact with the top surface of the active region.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising:
forming a dielectric layer on the top surface of a substrate, wherein an active region is arranged in the substrate and is positioned on the top of the substrate;
forming a first mask layer on the top surface of the dielectric layer, wherein the opening of the first mask layer exposes the dielectric layer positioned above the active region;
etching the dielectric layer for the first time through the opening of the first mask layer to enable the thickness of the part, far away from the active region, of the residual dielectric layer to be larger than the thickness of the part, close to the active region, of the residual dielectric layer;
forming a second mask layer on the top surface of the dielectric layer, wherein the opening of the second mask layer exposes a part of the dielectric layer above the active layer;
etching the dielectric layer for the second time through the opening of the second mask layer, and etching a through hole at the position of the dielectric layer corresponding to the active region; and
and forming a metal layer on the surface of the dielectric layer, wherein the metal layer extends from the top surface of the dielectric layer to the upper part of the active region through the side surface, fills the through hole and is electrically connected with the active region.
Further, the dielectric layer is etched for the first time, the dielectric layer below the opening of the first mask layer is partially removed, and the side surface of the exposed dielectric layer extends towards the active region to form an inclined surface.
Further, the first etching is wet etching.
Further, the thickness of the dielectric layer below the opening of the first mask layer is 0.6-1.5 μm through the first etching.
The invention has the beneficial effects that: the invention provides a semiconductor device and a method of manufacturing the same. By forming the dielectric layer into a specific shape, the thickness of the dielectric layer far away from the active region is larger than that of the dielectric layer near the active region, so that the distance between the metal layer corresponding to the active region and the substrate is smaller, and the larger distance is kept between the rest of the metal layer and the substrate. Therefore, compared with the traditional semiconductor device adopting a single-layer thicker insulating medium layer and a plurality of layers of thinner insulating medium layers, the parasitic capacitance of the semiconductor device provided by the invention is slightly increased but can be ignored.
On the basis, the structure of the dielectric layer is specially arranged, so that the metal layer can extend to the position above the active region through the side surface of the dielectric layer and is electrically connected with the active region through filling the through hole in the dielectric layer, the depth-to-width ratio of the through hole can be effectively controlled, and the conductive plug is manufactured and chemical mechanical polishing is carried out without filling a conductive material in the through hole. Therefore, compared with a semiconductor device adopting a single-layer thicker insulating medium layer, the difficulty in etching and filling the through hole can be reduced, and the problems of incomplete etching of the through hole and filling of a cavity are avoided; compared with the traditional semiconductor device adopting multiple layers of thin insulating medium layers, the process difficulty can be reduced, the processing steps can be reduced, the processing cost can be reduced, and the yield of products can be improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a schematic cross-sectional structure of a conventional semiconductor device;
fig. 2 shows a schematic cross-sectional structure of a semiconductor device according to an embodiment of the present invention;
fig. 3 shows a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 4a to 4j respectively show schematic cross-sectional structures of stages in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
In order to facilitate understanding of the present invention, the technical solutions of the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the technical solution of the present invention may be realized in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. The features in the embodiments described below may be combined with each other without conflict.
When a layer, a region or a layer is referred to as being "on" or "over" another layer, another region, or a layer or a region may be directly on or over the other layer, the other region, or another layer or a region may be included between the layer and the other layer or the other region in describing the structure of the device. And, if the device is turned over, that layer, region, or regions will be "under" or "beneath" another layer, region, or regions. If for the purpose of describing the situation directly above another layer, another region, the expressions "a is directly above B", "a is above and adjacent to B", or "a is above B and a is in direct contact with B" and the like will be used herein. Wherein, the upper part and the upper part refer to the right upper part; when one layer, one region is located obliquely above the other layer, the other region will be described.
In order to reduce the parasitic capacitance generated between a substrate and a top metal layer (a metal wiring layer or an extraction electrode) in a semiconductor device and solve the problems that the etching difficulty of a through hole is high and a cavity is easily formed when a conductive material is filled in the through hole due to the overlarge thickness of an insulating medium layer between the substrate and the top metal layer, the prior art generally adopts the following solution thought: a plurality of relatively thin insulating medium layers are arranged between the substrate and the top metal layer, through holes and conductive plugs are manufactured in each insulating medium layer, and metal layers are arranged between adjacent through holes to electrically connect the conductive plugs. Fig. 1 shows a schematic cross-sectional structure of a typical semiconductor device at present.
As shown in fig. 1, a conventional semiconductor device 100 includes a substrate 101, and a first dielectric layer 103, a second dielectric layer 104, and a top metal layer 108 sequentially stacked on a surface of the substrate 101. Wherein an active region 102 is provided in the substrate 101 and a top surface of the active region 102 is provided as a part of the top surface of the substrate 101. Through holes are formed in the two dielectric layers at positions corresponding to the active region 102, and conductive materials such as tungsten are filled in each through hole to form a first conductive plug 105 and a second conductive plug 107 respectively. An intermediate metal layer 106 is arranged between two adjacent through holes. In this way, the active region 102 in the semiconductor substrate 101 may be electrically connected to the top metal layer 108 through the first conductive plug 105, the intermediate metal layer 106, and the second conductive plug 107 in this order.
Accordingly, the semiconductor device 100 shown in fig. 1 is manufactured by a process that generally includes the following steps:
s1, forming a first dielectric layer 103 on the substrate 101 with the active region 102;
s2, etching a through hole (the through hole directly contacting the active region 102 is also referred to as a contact hole) at a position of the first dielectric layer 103 corresponding to the active region 102 by dry etching; filling a conductive material such as titanium, titanium nitride, or tungsten into the contact hole, and then performing Chemical Mechanical Polishing (CMP) to form a first conductive plug 105;
s3, forming a metal layer on the surface of the first dielectric layer 103 through sputtering, deposition and other modes, then etching, and only reserving the metal layer covering the surface of the contact hole to obtain an intermediate metal layer 106;
s4, forming a second dielectric layer 104 on the surfaces of the first dielectric layer 103 and the middle metal layer 106, and then polishing the surfaces by chemical mechanical polishing;
s5, performing photolithography and dry etching on the second dielectric layer 104 to form a through hole in a region corresponding to the contact hole, filling conductive materials such as titanium, titanium nitride, and tungsten in the through hole, and performing chemical mechanical polishing to form a second conductive plug 107;
s6, forming a metal layer on the second dielectric layer 104, and then etching the metal layer according to the functional requirements to obtain the top metal layer 108. The top metal layer 108 may serve as a metal wiring or a lead-out electrode.
The semiconductor device 100 changes a single thicker insulating dielectric layer into two relatively thinner insulating dielectric layers, and can keep a smaller parasitic capacitance between the top metal layer 108 and the substrate 101 by controlling the total thickness of the insulating dielectric layers. On the basis, the thickness of each insulating medium layer is not large, so that the etching difficulty and the filling difficulty of the through hole can be reduced, and the problem of incomplete etching or cavity filling is avoided.
However, since each insulating dielectric layer needs to be provided with a through hole and filled with a conductive material, and multiple times of CMP are performed, the manufacturing cycle of the semiconductor device 100 is long, and the complicated steps may affect the yield of the product and result in high cost of the semiconductor device 100.
In addition, as the feature size of the current device is smaller and smaller, and the radial size of the through hole is smaller and smaller, even if two layers of relatively thin insulating dielectric layers are used, the aspect ratio of the through hole is still kept at a high level, and therefore, the opening and filling of the through hole is still an important challenge in the device manufacturing process. If three or more insulating dielectric layers are arranged, although the depth-width ratio of the through hole can be reduced to a certain extent by further reducing the thickness of each insulating dielectric layer, the processing steps are more complicated, the manufacturing period is longer, the yield is lower, and the cost is higher.
In view of this, the embodiments of the present invention further improve the structure and process of the conventional semiconductor device, so as to reduce the processing steps, reduce the process difficulty, reduce the processing cost, and improve the yield of the product on the premise of not changing the parasitic capacitance basically. The technical solution of the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Fig. 2 shows a schematic cross-sectional structure of a semiconductor device according to an embodiment of the present invention. As shown in fig. 2, the semiconductor device 200 provided in the present embodiment includes a substrate 201, and a dielectric layer 204 and a metal layer 208 sequentially stacked on a top surface of the substrate 201.
The substrate 201 is a semiconductor substrate in a broad sense, and may be a common semiconductor substrate doped with N-type or P-type impurities, or a semiconductor substrate with an epitaxial layer. An active region 202 is formed in the substrate 201, and the active region 202 is generally located on top of the substrate 201, i.e., the top surface of the active region 202 is a portion of the top surface of the substrate 201. And if the substrate 201 is provided with an epitaxial layer, the active region 202 is typically located in the epitaxial layer.
A through hole 209 is formed in the dielectric layer 204, the through hole 209 is located above the active region 202, and an orthographic projection of the through hole 209 on the substrate 201 is located in a top surface of the active region 202. In this embodiment, the thickness of the dielectric layer 204 is greater at the portion away from the active region 202 than at the portion near the active region 202.
Metal layer 208 is located on the top surface of dielectric layer 204, extends in a height-to-height direction over active region 202 through the side surface of dielectric layer 204, and is electrically connected to active region 202 by filling through-hole 209. Metal layer 208 may serve as an extraction electrode or metal wiring layer depending on device functional requirements.
The present embodiment provides a semiconductor device 200, wherein the insulating dielectric layer includes a dielectric layer 204, the dielectric layer 204 near the active region 202 has a relatively small thickness, and the dielectric layer 204 far from the active region 202 has a relatively large thickness. Accordingly, the distance between the metal layer 208 corresponding to the active region 202 and the substrate 201 is smaller, and the distance between the metal layer 208 distant from the active region 202 and the substrate 201 is larger. Therefore, if the total thickness of the insulating dielectric layer above the active region 202 is the same as or equivalent to the total thickness of the insulating dielectric layer in the conventional semiconductor device (e.g., the semiconductor device 100 shown in fig. 1), the parasitic capacitance of the semiconductor device 200 of the present embodiment is slightly increased. However, considering that the metal layer 208 corresponding to the portion of the active region 202 occupies a very small proportion of the entire metal layer 208, generally not more than 5%, the increase in parasitic capacitance is substantially negligible and is allowed and acceptable in device design.
Further, the dielectric layer 204 may be stepped and the side surface thereof includes an inclined surface a, so that the dielectric layer 204 correspondingly forms a slope extending toward the active region 202. The slope is not only beneficial to forming the metal layer 208 on the dielectric layer 204, but also enables the metal layer 208 to be firmly attached to the surface of the dielectric layer 204, and avoids falling off.
Further, in the present embodiment, the dielectric layer 204 has two steps, i.e., an upper step and a lower step. Wherein, the top surface of the upper step is the top surface of the dielectric layer 204, and the side surface of the upper step comprises an inclined surface a connected with the top surface thereof; the top surface of the lower step is connected to the inclined surface a of the upper step, and the side surface of the lower step is the sidewall of the through hole 209, i.e., the depth of the through hole 209 is the thickness/height of the lower step. The metal layer 208 extends from the top and side surfaces of the upper step and the top surface of the lower step to the through hole 209, and fills the through hole 209 to be electrically connected to the active region 202. Thus, the metal layer 208 extends from the top surface of the upper step to the upper side of the active region 202 through the inclined surface a and the top surface of the lower step in this order, and is electrically connected to the active region 202 by filling the through hole 209. Therefore, the aspect ratio of the through hole 209 can be effectively controlled by controlling the height of the lower step, and the conductive plug is not required to be manufactured by filling the through hole 209 with a conductive material, and the CMP is not required, so that compared with the conventional semiconductor device, the device structure and the device manufacturing process can be simplified, the processing difficulty is reduced, the manufacturing cost is reduced, and the product yield is improved. In addition, the upper step has the inclined surface a, which facilitates the formation of the metal layer 208 and the firm attachment on the surface of the dielectric layer 204.
Referring further to fig. 2, in the present embodiment, the metal layer 208 located in the through hole 209 may be in direct contact with the top surface of the active region 202, i.e., the metal layer 208 is adjacent to the active region 202 for electrical connection.
A method for manufacturing the semiconductor device 200 according to the present embodiment will be described below with reference to the drawings. Wherein fig. 3 shows a flowchart of a method of manufacturing the semiconductor device 200 according to the present embodiment; fig. 4 a-4 j show schematic cross-sectional structures at various stages of the manufacturing method, respectively. Referring to fig. 3, 4 a-4 j in combination with fig. 2, the manufacturing method comprises the steps of:
step S101: a dielectric layer is formed on a top surface of the substrate.
As shown in fig. 4a, an active region 202 is disposed in the substrate 201, the active region 202 is located on top of the substrate 201, and a top surface of the active region 202 is a portion of the top surface of the substrate 201. The substrate 201 may be a doped semiconductor substrate or a semiconductor substrate with an epitaxial layer. When the substrate 201 is provided with an epitaxial layer, the active region 202 is typically located in the epitaxial layer.
Referring to fig. 4b, a dielectric layer 204 is formed on the substrate 201 by deposition, sputtering, or the like, wherein the material is an insulating material such as silicon dioxide, silicon nitride, or the like, and silicon dioxide is generally selected.
Step S102: a first masking layer is formed on a top surface of the dielectric layer, and an opening of the first masking layer exposes the dielectric layer over the active region.
As shown in fig. 4c, a first mask layer 207 is formed on the top surface of the dielectric layer 204, and the opening of the first mask layer 207 exposes the dielectric layer 204 directly above the active region 202. For example, the area of the opening of the first mask layer 207 is slightly larger than the cross-sectional area of the active region 202 in a direction parallel to the top surface of the substrate 201.
The first mask layer 207 may be specifically obtained by coating a photoresist on the surface of the dielectric layer 204, and exposing and developing the photoresist, or may be formed by using other materials and matching processes in the semiconductor field.
Step S103: and etching the dielectric layer for the first time through the opening of the first mask layer, so that the thickness of the part, far away from the active region, in the residual dielectric layer is larger than that of the part, close to the active region, in the residual dielectric layer.
Specifically, the steps include:
s1031, performing primary etching on the dielectric layer, partially removing the dielectric layer below the opening, and enabling the side surface of the correspondingly exposed dielectric layer to be an inclined surface A;
s1032, the first mask layer 207 is removed.
As shown in fig. 4d, the dielectric layer 204 is etched for the first time through the opening of the first mask layer 207. The first etch uses a partial etch, i.e., an incomplete etch, to reduce the thickness of the dielectric layer 204 under the opening, rather than completely etching the dielectric layer 204 under the opening. In this embodiment, the first etching is wet etching. Since the wet etch is an isotropic etch, the dielectric layer 204 under the edge of the first mask layer 207 is also etched (colloquially referred to as "undercutting") during the etch, so that the dielectric layer 204 forms a shallow slope therein, which extends from the top surface of the dielectric layer 204 under the first mask layer 207 towards the active region 202.
After the first etching is completed, the first mask layer 207 is removed to expose the surface of the dielectric layer 204, as shown in fig. 4 e. How to remove the first mask layer 207 is not particularly limited in this embodiment, and conventional technical means in the art may be specifically adopted, which is not described herein again. After the first etching, the exposed side surface of the dielectric layer 204 includes an inclined surface a extending from the top surface of the dielectric layer 204 toward the active region 202.
Step S104: a second masking layer is formed on the top surface of the dielectric layer, and an opening of the second masking layer exposes a portion of the dielectric layer that is located over the active layer.
As shown in fig. 4f and fig. 4g, a second mask layer 203 is formed on the surface of the dielectric layer 204, and the second mask layer 203 may be formed by coating a photoresist on the surface of the dielectric layer 204, exposing and developing, or by using other materials and matching processes in the semiconductor field.
As shown in fig. 4g, the opening 206 of the second mask layer 203 exposes a portion of the dielectric layer 204 directly above the active region 202. The orthographic projection of this opening 206 on the substrate 201 lies within the top surface of the active region 202.
Step S105: and etching the dielectric layer through the opening of the second mask layer, and etching a through hole at the position of the dielectric layer corresponding to the active region.
As shown in fig. 4h, a through hole 209 is etched in the dielectric layer 204 by the second etching, and the through hole 209 is located right above the active region 202 and corresponds to the position of the opening 206. The through hole 209, which is in direct contact with the active region 201, is also referred to as a contact hole, if the dielectric layer 204 is located above the substrate 201 and adjacent to the substrate 201.
If the requirement on the dimensional accuracy of the through hole 209 is not high, a dry etching process or a wet etching process may be used. If the requirement for the dimensional accuracy of the through-hole 209 is high, dry etching is preferable.
Referring to fig. 4i, the second mask layer 203 on the surface of the dielectric layer 204 is removed to expose the dielectric layer 204.
After the above two times of etching, the obtained dielectric layer 204 has two steps, wherein the side surface of the upper step includes the inclined surface a obtained by the first etching, the top of the inclined surface a is connected with the top surface of the dielectric layer 204, and the bottom of the inclined surface a is connected with the top surface of the lower step.
The inventor researches and discovers that if the first etching amount is too small, the residual dielectric layer 204 above the active region 202 is thicker, so that the etching difficulty and the filling difficulty of the through hole 209 in the subsequent steps can be increased; on the contrary, if the first etching amount is too large, the remaining dielectric layer 204 is too thin, and the upper step is too steep, which is not favorable for the subsequent formation of the metal layer 208, and the parasitic capacitance is increased along with the increase of the area of the inclined surface, which brings unfavorable influence to the device performance. In the specific implementation process, the first etching amount is generally controlled to be 70% to 95%. Specifically, the thickness of the dielectric layer 204 remaining above the active region 202 after the first etching is 5% to 30% of the thickness before etching, based on 100% of the thickness of the dielectric layer 204 before etching.
Furthermore, after the first etching along the thickness direction, the thickness of the dielectric layer 204 under the opening of the first mask layer 207 is 0.6 to 1.5 μm. The selection of the etching thickness is not only beneficial to the subsequent formation of the through hole 209, but also beneficial to the subsequent formation of the metal layer 208 on the surface of the dielectric layer and the effective filling of the metal layer 208 to the through hole 209.
Step S106: and forming a metal layer on the surface of the dielectric layer, wherein the metal layer extends from the top surface of the dielectric layer to the upper part of the active region through the side surface, fills the through hole and is electrically connected with the active region.
As shown in fig. 4j, a metal layer is formed on the surface of the dielectric layer 204 by sputtering, deposition, etc., and then photolithography and etching are performed to form a metal layer 208 having a distribution required by the function of the semiconductor device 200, where the metal layer 208 is also referred to as a top metal layer and can be used as a metal wiring or a lead-out electrode. The metal layer 208 extends from the top surface of the upper step of the dielectric layer 204 to the upper side of the active region 202 via the inclined side surface, and fills the through hole 209 to directly contact the top surface of the active region 202 to form an electrical connection.
Compared with the manufacturing method of the conventional semiconductor device 100 shown in fig. 1, in the manufacturing method of the semiconductor device 200 provided in this embodiment, only one dielectric layer 204 needs to be arranged, and the through hole 209 is manufactured once, and it is not necessary to fill a conductive material into the through hole 209 and perform CMP, so that the manufacturing steps are reduced, the manufacturing difficulty is reduced, the processing efficiency is improved, and risks of incomplete etching and cavity filling in the manufacturing and filling processes of the through hole 209 are avoided, thereby being beneficial to reducing the product cost and improving the product yield.
In addition, compared with the conventional semiconductor device 100 shown in fig. 1, the second metal layer 106 is not required, so the device structure and the process flow are further simplified.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.

Claims (10)

1. A semiconductor device comprises a substrate, wherein an active region is arranged in the substrate and is positioned on the top of the substrate; wherein, still include:
the dielectric layer is positioned on the top surface of the substrate, a through hole is formed in the dielectric layer and positioned on the top surface of the active region, and the thickness of the part, far away from the active region, of the dielectric layer is larger than that of the part, close to the active region, of the dielectric layer;
and the metal layer is positioned on the top surface of the dielectric layer, extends downwards to the position above the active area through the side surface of the dielectric layer, and fills the through hole to form electric connection with the active area.
2. The semiconductor device of claim 1, wherein the dielectric layer is stepped, a side surface of the step includes an inclined surface, and the metal layer extends from a top surface of the step downward over the active region through the inclined surface.
3. The semiconductor device of claim 2, wherein the dielectric layer has two steps, wherein a side surface of an upper step includes the inclined surface;
the metal layer extends from the top surface of the upper step down onto the top surface of the lower step through the inclined surface, and fills the through hole to be electrically connected with the active region.
4. The semiconductor device according to claim 3, wherein a top of the inclined surface is connected to a top surface of the upper step, and a bottom of the inclined surface is connected to a top surface of the lower step;
and the height of the upper step is 70-95% of the total height by taking the total height of the two steps as 100%.
5. The semiconductor device according to claim 3 or 4, wherein the height of the lower step is 0.6 to 1.5 μm.
6. The semiconductor device of claim 1, wherein the metal layer located in the through hole is in direct contact with a top surface of the active region.
7. A method of manufacturing a semiconductor device, comprising:
forming a dielectric layer on a top surface of a substrate, wherein an active region is disposed in the substrate, the active region being located on top of the substrate;
forming a first mask layer on a top surface of the dielectric layer, an opening of the first mask layer exposing the dielectric layer over the active region;
etching the dielectric layer for the first time through the opening of the first mask layer to enable the thickness of the part, far away from the active region, of the residual dielectric layer to be larger than that of the part, close to the active region, of the residual dielectric layer;
forming a second mask layer on the top surface of the dielectric layer, wherein the opening of the second mask layer exposes a part of the dielectric layer above the active layer;
etching the dielectric layer for the second time through the opening of the second mask layer, and etching a through hole at the position of the dielectric layer corresponding to the active region; and
and forming a metal layer on the surface of the dielectric layer, wherein the metal layer extends from the top surface of the dielectric layer to the upper part of the active region through the side surface, fills the through hole and is electrically connected with the active region.
8. The manufacturing method according to claim 7, wherein the dielectric layer is subjected to a first etching to partially remove the dielectric layer under the opening of the first mask layer and to extend the exposed side surface of the dielectric layer toward the active region to form an inclined surface.
9. The manufacturing method according to claim 8, wherein the first etching is wet etching.
10. The manufacturing method according to claim 8 or 9, wherein the thickness of the dielectric layer under the opening of the first mask layer is 0.6 to 1.5 μm by the first etching.
CN202011154069.1A 2020-10-26 2020-10-26 Semiconductor device and manufacturing method thereof Pending CN112103267A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011154069.1A CN112103267A (en) 2020-10-26 2020-10-26 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011154069.1A CN112103267A (en) 2020-10-26 2020-10-26 Semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN112103267A true CN112103267A (en) 2020-12-18

Family

ID=73784942

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011154069.1A Pending CN112103267A (en) 2020-10-26 2020-10-26 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN112103267A (en)

Similar Documents

Publication Publication Date Title
US7755127B2 (en) Capacitor in semiconductor device and method of manufacturing the same
US7022569B2 (en) Lower electrode contact structure and method of forming the same
CN213340369U (en) Semiconductor device with a plurality of transistors
CN112103267A (en) Semiconductor device and manufacturing method thereof
KR0184064B1 (en) Method of manufacturing capacitor of semiconductor device
CN213340370U (en) Semiconductor device with a plurality of transistors
US20220246845A1 (en) Resistive random-access memory (rram) device and forming method thereof
CN112103266A (en) Semiconductor device and manufacturing method thereof
CN110767627B (en) Semiconductor device and manufacturing process thereof
KR100515378B1 (en) Fabrication method of thin film capacitor
TWI602309B (en) Capacitor structure and manufacturing method thereof
KR100950752B1 (en) Semiconductor device and method for manufacturing the same
CN111326511A (en) Memory device and method of manufacturing the same
KR20040065975A (en) Manufacturing method of semiconductor device
US11289336B2 (en) Method for multi-level etch, semiconductor sensing device, and method for manufacturing semiconductor sensing device
US7199013B2 (en) Semiconductor device and method for fabricating the same
CN109786377B (en) Power transistor and method of manufacturing the same
KR100631938B1 (en) Manufacturing method for capacitor
KR100466982B1 (en) Semiconductor device having capacitors and method of fabricating the same
KR100607762B1 (en) Method for forming shallow trench isolation of semiconductor element
KR20080000274A (en) Capacitor in a semiconductor device and method of manufacturing the same
KR20010063707A (en) Method of manufacturing a capacitor in a semiconductor device
CN115884672A (en) Semiconductor structure, manufacturing method thereof and capacitor
KR20000050505A (en) Method for forming contact hole of semiconductor device
KR100328824B1 (en) Manufacturing method for capacitor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination