CN112083674A

CN112083674A - FPGA chip data processing method, chip, computer equipment and storage medium

Info

Publication number: CN112083674A
Application number: CN202010940576.1A
Authority: CN
Inventors: 刘磊; 张强; 王文皞
Original assignee: Leihua Electronic Technology Research Institute Aviation Industry Corp of China
Current assignee: Leihua Electronic Technology Research Institute Aviation Industry Corp of China
Priority date: 2020-09-09
Filing date: 2020-09-09
Publication date: 2020-12-15

Abstract

The invention provides a data processing method of an FPGA chip, a chip, computer equipment and a storage medium, belonging to the field of digital processing of an AD front end of a radar, and particularly comprising the steps of receiving serial sampling data of a digital-to-analog conversion module by adopting a JESD universal interface, wherein the sampling frequency of the serial sampling data is not less than 200 MHz; converting the serial sampling data into multi-channel parallel data through an IP core of a JESD universal interface; respectively carrying out frequency mixing processing on the multiple paths of parallel data by adopting a digital control oscillator to obtain frequency mixing data corresponding to each path of parallel data; and filtering each group of the frequency mixing data to obtain low-frequency digital-analog sampling data. By the processing scheme, the FPGA chip is simple in design, high in processing capacity and easy in engineering practice.

Description

FPGA chip data processing method, chip, computer equipment and storage medium

Technical Field

The invention relates to the field of digital processing of an AD front end of a radar, in particular to a data processing method of an FPGA chip, a chip, computer equipment and a storage medium.

Background

The radar AD front-end preprocessing system is an important component of a radar system and mainly achieves the functions of receiving intermediate-frequency signals, converting baseband signals and the like. With the development of the active phased array radar to a large broadband and high integration level, the system puts higher requirements on digital components, and the light weight, small volume and high bandwidth become an important development trend. Conventional AD front-end pre-processing has the following disadvantages: when the parallel bus is adopted for communicating with the FPGA, a plurality of output pins are provided, which causes the difficulty of PCB wiring and the increase of design cost; DDR and SDR interfaces are adopted in the FPGA, so that the communication bandwidth is low, the interface design is complex, and the interconnection between IP cores is difficult to realize; and the serial digital down-conversion processing mode is adopted, so that the processing requirements of high sampling rate and high bandwidth are difficult to meet.

Disclosure of Invention

Therefore, in order to overcome the above-mentioned drawbacks of the prior art, the present invention provides an FPGA chip data processing method, a chip, a computer device and a storage medium, which can be applied to a high-sampling-rate, high-bandwidth AD front-end digital down-conversion processing system.

In order to achieve the above object, the present invention provides a data processing method for an FPGA chip, wherein the FPGA chip is provided with a JESD universal interface, and the method comprises the following steps: receiving serial sampling data of a digital-to-analog conversion module by adopting a JESD universal interface, wherein the sampling frequency of the serial sampling data is not less than 200 MHz; converting the serial sampling data into multi-channel parallel data through an IP core of a JESD universal interface; respectively carrying out frequency mixing processing on the multiple paths of parallel data by adopting a digital control oscillator to obtain frequency mixing data corresponding to each path of parallel data; and filtering each group of the frequency mixing data to obtain low-frequency digital-analog sampling data.

In one embodiment, the converting the serial sampling data into multiple parallel data by an IP core of a JESD universal interface includes: acquiring the configured parallel data frequency and parallel data channel number of the IP core; and processing the serial sampling data into a plurality of paths of parallel data according to the parallel data frequency and the number of parallel data channels.

In one embodiment, the performing, by using a numerically controlled oscillator, frequency mixing processing on multiple paths of the parallel data respectively to obtain frequency mixing data corresponding to each path of the parallel data includes: acquiring initial phase and intermediate frequency signal setting parameters of a digital control oscillator; generating a sine wave local oscillation signal and a cosine wave local oscillation signal by adopting a digital control oscillator according to the setting parameters; and respectively mixing the sine wave local oscillation signal and the cosine wave local oscillation signal with each path of parallel data to obtain mixed data corresponding to each path of parallel data.

In one embodiment, the filtering the mixed data of each group to obtain low-frequency digital-to-analog sampling data includes: acquiring cut-off frequency, bandwidth coefficient and order of a filter; and filtering the frequency mixing data according to the cut-off frequency, the bandwidth coefficient and the order number to obtain low-frequency digital-analog sampling data.

The invention also provides an FPGA chip, comprising: the JESD universal interface module is used for receiving serial sampling data of the digital-to-analog conversion module and converting the serial sampling data into multi-channel parallel data, and the sampling frequency of the serial sampling data is not less than 200 MHz; the phase adjustment module is connected with the data output end of the JESD universal interface and is used for respectively carrying out frequency mixing processing on the multiple paths of parallel data by adopting a digital control oscillator to obtain frequency mixing data corresponding to each path of parallel data; and the filtering processing module is used for filtering each group of the mixing data to obtain low-frequency digital-analog sampling data.

The invention also provides a computer device comprising a memory and a processor, the memory storing a computer medium, characterized in that the processor implements the steps of the above method when executing the computer program.

The invention also provides a computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when executed by a processor, carries out the steps of the above-mentioned method.

Compared with the prior art, the invention has the advantages that: by using the JESD high-speed serial communication technology, the higher sampling rate can be realized while the data transmission pins of the AD and the FPGA are reduced; by using the JESD synchronization technology, the synchronization requirement of the multichannel ADC can be realized, so that the requirements of miniaturization, multichannel integration, high bandwidth, high sampling rate and serialized output development of the ADC are met. And AD sampling data are converted into multi-channel parallel data through a JESD interface, and multi-channel parallel processing is performed inside the FPGA, so that the data processing bandwidth inside the FPGA can be remarkably improved, and high-bandwidth processing is realized. The method has the advantages of simple design, strong processing capability, easy engineering practice and the like, and can be applied to an AD front-end digital down-conversion processing system with high sampling rate and high bandwidth.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic flow chart of a data processing method of an FPGA chip according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an FPGA chip according to an embodiment of the present invention;

FIG. 3 is a block diagram of an FPGA chip in an embodiment of the invention; and

fig. 4 is an internal configuration diagram of a computer device in an embodiment of the present invention.

Detailed Description

The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that aspects may be practiced without these specific details.

As shown in fig. 1, an embodiment of the present disclosure provides a method for processing data of an FPGA chip, where the FPGA chip is provided with a JESD universal interface, and the method may be implemented by controlling the FPGA chip by a server, and may also be implemented by the FPGA chip, and the method for processing data of the FPGA chip includes the following steps:

and step 102, receiving serial sampling data of the digital-to-analog conversion module by adopting a JESD universal interface, wherein the sampling frequency of the serial sampling data is not less than 200 MHz.

The FPGA chip receives serial sampling data of a digital-to-analog conversion module (AD) by adopting a JESD universal interface, and the sampling frequency of the serial sampling data is not less than 200 MHz. In one embodiment, the JESD universal interface may be the JESD204B interface. As shown in fig. 2, the FPGA chip has JESD204B communication interface, NCO generation module, multiplier, FIR filter module, and so on. Communication interface 1 is JESD204B communication interface, and is used for serial transmission of sampling data. The AXIS-DISTRIBUTE module 2 is used for converting serial data into 4-way parallel data. The DDS GENERATOR module 3 is used for generating local oscillation signals. The AXIS

multiplexer modules

4, 5, 6, and 7 are all used for generating local oscillator signals and mixing parallel data. The

FIR blocks

8, 9, 10, 11 and the AXIS-addrer block 12 are used for the filtering process. And the modules are interconnected through an AXIS interface.

And step 104, converting the serial sampling data into multi-channel parallel data through an IP core of the JESD universal interface.

And the FPGA chip converts the serial sampling data into multi-path parallel data through an IP core of the JESD universal interface. The FPGA chip is connected with an AXIS-DISTRIBUTE module 2 arranged on an IP core of a JESD universal interface through a JESD module 1, and divides the JESD AXIS into 4 paths of AD AXIS data. The JESD IP core divides the AD data into 4 paths, so that an AD sampling clock in the FPGA can be reduced to 1/4 of the original AD sampling clock, meanwhile, a processing clock in the FPGA can be reduced to 1/4 of the AD sampling clock, and larger data processing bandwidth can be obtained under the same FPGA clock. The IP core of the JESD general interface can adopt an AXI4 Stream interface, so that the interconnection between the IP core and other equipment can be conveniently realized, the FPGA interface design is simplified, and the FPGA design and development difficulty is reduced.

And step 106, respectively carrying out frequency mixing processing on the multiple paths of parallel data by adopting a digital control oscillator to obtain frequency mixing data corresponding to each path of parallel data.

The FPGA chip adopts a digital control oscillator to respectively carry out frequency mixing processing on the multiple paths of parallel data to obtain frequency mixing data corresponding to each path of parallel data. The FPGA chip can adopt the DDS GENERATOR module 3 to store NCO COS parameters (numerical control oscillation parameters) in advance, write corresponding logics and generate 4 paths of independent DDS data through the DDS GENERATOR module 3. The 4

AXIS multiplex modules

4, 5, 6 and 7 respectively realize multiplication of 4 paths of AD data and 4 paths of DDS data to obtain mixing data corresponding to each path of parallel data.

And step 108, filtering each group of mixing data to obtain low-frequency digital-analog sampling data.

And the FPGA chip carries out filtering processing on each group of the mixing data to obtain low-frequency digital-analog sampling data. The FPGA chip respectively carries out filtering processing on each group of the obtained mixed frequency data through 4

FIR modules

8, 9, 10 and 11, and 4 paths of data obtained after filtering are processed through an AXIS-ADDER module 12 to obtain low-frequency digital-analog sampling data. The order of the FIR filter needs to be an integer multiple of 4.

According to the FPGA chip data processing method, the high-speed serial communication technology of the JESD is utilized, and higher sampling rate can be realized while data transmission pins of the AD and the FPGA are reduced; by using the JESD synchronization technology, the synchronization requirement of the multichannel ADC can be realized, so that the requirements of miniaturization, multichannel integration, high bandwidth, high sampling rate and serialized output development of the ADC are met. And AD sampling data are converted into multi-channel parallel data through a JESD interface, and multi-channel parallel processing is performed inside the FPGA, so that the data processing bandwidth inside the FPGA can be remarkably improved, and high-bandwidth processing is realized. The method has the advantages of simple design, strong processing capability, easy engineering practice and the like, and can be applied to an AD front-end digital down-conversion processing system with high sampling rate and high bandwidth.

In one embodiment, converting serial sampling data into multiple parallel data through an IP core of a JESD universal interface includes: acquiring parallel data frequency and parallel data channel number of the configured IP core; and processing the serial sampling data into a plurality of paths of parallel data according to the parallel data frequency and the number of parallel data channels.

And the FPGA chip acquires the parallel data frequency and the parallel data channel number of the configured IP core. The FPGA chip can obtain the maximum output speed according to the parallel data frequency and the number of parallel data channels, for example, when the single-channel communication speed of the JESD204B reaches 12.5Gbps, and when the parallel data channels adopt 8 channels, the speed can reach 100 Gbps. And the FPGA chip processes the serial sampling data into multi-channel parallel data according to the parallel data frequency and the number of parallel data channels.

In one embodiment, the method for obtaining the mixed data corresponding to each path of parallel data by respectively performing mixed frequency processing on multiple paths of parallel data by using a numerically controlled oscillator includes the following steps: acquiring initial phase and intermediate frequency signal setting parameters of a digital control oscillator; generating a sine wave local oscillation signal and a cosine wave local oscillation signal by adopting a digital control oscillator according to the setting parameters; and respectively mixing the sine wave local oscillation signal and the cosine wave local oscillation signal with each path of parallel data to obtain mixed data corresponding to each path of parallel data.

The FPGA chip acquires the initial phase of the digital control oscillator and the setting parameters of the intermediate frequency signal. The FPGA chip generates sine wave local oscillation signals (sin signals) and cosine wave local oscillation signals (cos signals) by adopting a digital control oscillator according to the setting parameters. And the FPGA chip respectively carries out frequency mixing on the sine wave local oscillation signal and the cosine wave local oscillation signal and each path of parallel data to obtain frequency mixing data corresponding to each path of parallel data.

In one embodiment, the filtering processing is performed on each group of mixed data to obtain low-frequency digital-to-analog sampling data, and the method includes the following steps: acquiring cut-off frequency, bandwidth coefficient and order of a filter; and filtering the mixing data according to the cut-off frequency, the bandwidth coefficient and the order number to obtain low-frequency digital-analog sampling data.

The FPGA chip acquires the cut-off frequency, the bandwidth coefficient and the order of the filter; and the FPGA chip carries out filtering processing on the frequency mixing data according to the cut-off frequency, the bandwidth coefficient and the order number to obtain low-frequency digital-analog sampling data.

As shown in fig. 3, there is also provided an FPGA chip, which includes a JESD universal interface module 302, a phase adjustment module 304, and a filtering processing module 306, wherein:

and the JESD universal interface module 302 is used for receiving the serial sampling data of the digital-to-analog conversion module and converting the serial sampling data into multi-channel parallel data, wherein the sampling frequency of the serial sampling data is not less than 200 MHz. The JESD universal interface module 302 may include a JESD universal interface 1 and an AXIS-disable module 2.

And the phase adjustment module 304 is connected with the data output end of the JESD universal interface, and is configured to perform frequency mixing processing on the multiple paths of parallel data respectively by using a digital control oscillator to obtain frequency mixing data corresponding to each path of parallel data. The phase adjustment module 304 may include a

DDS GENERATOR module

3 and 4

AXIS multilyer modules

4, 5, 6, 7.

And the filtering processing module 306 is configured to perform filtering processing on each group of mixed frequency data to obtain low-frequency digital-to-analog sampling data. The filter processing block 306 may comprise 4 FIR blocks 8, 9, 10, 11 and an AXIS-addrer block 12.

In one embodiment, a computer device is provided, which may be a server, the internal structure of which may be as shown in fig. 4. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer equipment is used for storing the FPGA chip processing data. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement an FPGA chip data processing method.

Those skilled in the art will appreciate that the architecture shown in figure Y is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as a particular computing device may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

In one embodiment, there is provided a computer device comprising a memory storing a computer program and a processor implementing the following steps when the processor executes the computer program: receiving serial sampling data of a digital-to-analog conversion module by adopting a JESD universal interface, wherein the sampling frequency of the serial sampling data is not less than 200 MHz; converting serial sampling data into multi-channel parallel data through an IP core of a JESD universal interface; respectively carrying out frequency mixing processing on the multiple paths of parallel data by adopting a digital control oscillator to obtain frequency mixing data corresponding to each path of parallel data; and filtering each group of mixing data to obtain low-frequency digital-analog sampling data.

In one embodiment, the converting the serial sampled data into multiple parallel data by an IP core of a JESD universal interface implemented when the processor executes the computer program includes: acquiring parallel data frequency and parallel data channel number of the configured IP core; and processing the serial sampling data into a plurality of paths of parallel data according to the parallel data frequency and the number of parallel data channels.

In one embodiment, the performing, by a processor executing a computer program, frequency mixing processing on multiple paths of parallel data by using a numerically controlled oscillator to obtain frequency mixing data corresponding to each path of parallel data includes: acquiring initial phase and intermediate frequency signal setting parameters of a digital control oscillator; generating a sine wave local oscillation signal and a cosine wave local oscillation signal by adopting a digital control oscillator according to the setting parameters; and respectively mixing the sine wave local oscillation signal and the cosine wave local oscillation signal with each path of parallel data to obtain mixed data corresponding to each path of parallel data.

In one embodiment, the filtering processing performed on each group of mixed data when the processor executes the computer program to obtain low-frequency digital-to-analog sampling data includes: acquiring cut-off frequency, bandwidth coefficient and order of a filter; and filtering the mixing data according to the cut-off frequency, the bandwidth coefficient and the order number to obtain low-frequency digital-analog sampling data.

In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of: receiving serial sampling data of a digital-to-analog conversion module by adopting a JESD universal interface, wherein the sampling frequency of the serial sampling data is not less than 200 MHz; converting serial sampling data into multi-channel parallel data through an IP core of a JESD universal interface; respectively carrying out frequency mixing processing on the multiple paths of parallel data by adopting a digital control oscillator to obtain frequency mixing data corresponding to each path of parallel data; and filtering each group of mixing data to obtain low-frequency digital-analog sampling data.

In one embodiment, an IP core implemented by a computer program when executed by a processor to convert serial sampled data to multiple parallel data via a JESD universal interface includes: acquiring parallel data frequency and parallel data channel number of the configured IP core; and processing the serial sampling data into a plurality of paths of parallel data according to the parallel data frequency and the number of parallel data channels.

In one embodiment, the computer program, when executed by a processor, implements a mixing process on multiple paths of parallel data respectively by using a numerically controlled oscillator, and obtains mixing data corresponding to each path of parallel data, including: acquiring initial phase and intermediate frequency signal setting parameters of a digital control oscillator; generating a sine wave local oscillation signal and a cosine wave local oscillation signal by adopting a digital control oscillator according to the setting parameters; and respectively mixing the sine wave local oscillation signal and the cosine wave local oscillation signal with each path of parallel data to obtain mixed data corresponding to each path of parallel data.

In one embodiment, the filtering of each group of mixed data to obtain low frequency digital-to-analog sampled data, implemented when the computer program is executed by the processor, includes: acquiring cut-off frequency, bandwidth coefficient and order of a filter; and filtering the mixing data according to the cut-off frequency, the bandwidth coefficient and the order number to obtain low-frequency digital-analog sampling data.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware related to instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

The above is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A data processing method of an FPGA chip is provided with a JESD universal interface, and is characterized by comprising the following steps:

receiving serial sampling data of a digital-to-analog conversion module by adopting a JESD universal interface, wherein the sampling frequency of the serial sampling data is not less than 200 MHz;

converting the serial sampling data into multi-channel parallel data through an IP core of a JESD universal interface;

respectively carrying out frequency mixing processing on the multiple paths of parallel data by adopting a digital control oscillator to obtain frequency mixing data corresponding to each path of parallel data;

and filtering each group of the frequency mixing data to obtain low-frequency digital-analog sampling data.

2. The FPGA chip data processing method of claim 1, wherein the converting the serial sample data into multiple parallel data by an IP core of a JESD universal interface comprises:

acquiring the configured parallel data frequency and parallel data channel number of the IP core;

and processing the serial sampling data into a plurality of paths of parallel data according to the parallel data frequency and the number of parallel data channels.

3. The method according to claim 1, wherein the step of performing frequency mixing processing on the multiple paths of parallel data by using a numerically controlled oscillator to obtain frequency mixing data corresponding to each path of parallel data comprises:

acquiring initial phase and intermediate frequency signal setting parameters of a digital control oscillator;

generating a sine wave local oscillation signal and a cosine wave local oscillation signal by adopting a digital control oscillator according to the setting parameters;

and respectively mixing the sine wave local oscillation signal and the cosine wave local oscillation signal with each path of parallel data to obtain mixed data corresponding to each path of parallel data.

4. The FPGA chip data processing method of claim 1, wherein said filtering each group of said mixing data to obtain low frequency digital-to-analog sampling data comprises:

acquiring cut-off frequency, bandwidth coefficient and order of a filter;

and filtering the frequency mixing data according to the cut-off frequency, the bandwidth coefficient and the order number to obtain low-frequency digital-analog sampling data.

5. An FPGA chip, comprising:

the JESD universal interface module is used for receiving serial sampling data of the digital-to-analog conversion module and converting the serial sampling data into multi-channel parallel data, and the sampling frequency of the serial sampling data is not less than 200 MHz;

the phase adjustment module is connected with the data output end of the JESD universal interface and is used for respectively carrying out frequency mixing processing on the multiple paths of parallel data by adopting a digital control oscillator to obtain frequency mixing data corresponding to each path of parallel data;

and the filtering processing module is used for filtering each group of the mixing data to obtain low-frequency digital-analog sampling data.

6. A computer device comprising a memory and a processor, the memory storing a computer medium, wherein the processor when executing the computer program implements the steps of the method of any of claims 1 to 4.

7. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.