CN110808713A - FPGA-based multi-path parallel demodulation method for ultra-high-speed frequency division signals - Google Patents
FPGA-based multi-path parallel demodulation method for ultra-high-speed frequency division signals Download PDFInfo
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Abstract
The invention provides a multi-path parallel demodulation method of an ultra-high-speed frequency division signal based on an FPGA (field programmable gate array). after the high-speed analog frequency division signal is directly converted into a digital signal by an analog-to-digital conversion chip, the signal is input into the FPGA. And performing serial-parallel conversion on the high-speed digital frequency division signals to generate parallel m-path low-speed digital frequency division signals. And respectively carrying out the same serial-parallel conversion on the carrier signals corresponding to the frequency division number, wherein each carrier generates m paths of parallel subcarriers. The filter is converted into m sub-filters by the same serial-to-parallel conversion. And multiplying each path of low-speed digital frequency division signals by the same subcarrier of the path number, accumulating the multiplied results, and passing the accumulated sum result through a sub-filter of the path number. And adding the m paths of parallel signals which pass through the sub-filters to realize the demodulation of the high-speed frequency division signal. The invention greatly reduces the consumption of FPGA resources.
Description
Technical Field
The invention belongs to the technical field of ultra-high-speed frequency division signal demodulation, and particularly relates to an ultra-high-speed frequency division signal multi-path parallel demodulation method based on an FPGA (field programmable gate array).
Background
With the development of communication technology in recent years, the demand for ultra-high speed signal processing is more urgent. Aiming at the ultrahigh-speed analog frequency division signal, the traditional processing mode is that firstly, the ultrahigh-speed signal is subjected to frequency mixing through an external analog down converter to reduce the speed of the ultrahigh-speed signal, then, digital down conversion based on an FPGA is carried out, and the low-speed frequency division signal passes through a frequency mixing and low-pass filter module which is parallel to the ultrahigh-speed frequency division signal and corresponds to the number of frequency points, so that the demodulation of the ultrahigh-speed frequency division.
In practical application, the external analog down converter is expensive, poor in reliability and signal processing performance, and the weight and size of the equipment are increased due to the addition of the external module; on the other hand, in the implementation process of the FPGA, the multi-channel parallel mixing and low-pass filter module needs to consume a large amount of FPGA resources, and the number of parallel channels increases in proportion with the increase of the number of parallel frequency division signal frequency points, and the resource consumption of the resources cannot be estimated by adopting the traditional method. The traditional method for demodulating the ultra-high-speed frequency division signal cannot meet the requirements of high efficiency and high benefit of the current signal processing.
Disclosure of Invention
The invention aims to solve the problems of complex hardware equipment and high FPGA resource consumption of the demodulation of the ultra-high-speed frequency division signal, and provides a multi-path parallel demodulation method of the ultra-high-speed frequency division signal based on the FPGA, which simplifies the system structure and reduces the resource consumption.
The invention is realized by the following technical scheme:
a multi-path parallel demodulation method of an ultra-high-speed frequency division signal based on an FPGA (field programmable gate array) mainly comprises the following steps:
step one, a receiving end receives an ultra-high speed analog frequency division signal, an analog-to-digital conversion chip carries out analog-to-digital conversion on the received ultra-high speed analog frequency division signal and inputs the converted ultra-high speed analog frequency division signal to FPGA (field programmable gate array), and the rate of the ultra-high speed analog frequency division signal is made to be fsThe number of frequency points of the frequency division signal is N;
and step two, the FPGA receives the digital signal in the step one and carries out serial-to-parallel operation with the coefficient of m on the signal. Then m parallel data A (1), A (2), …, A (m) are obtained finally, and the rate of each frequency division signal is fs/m；
And step three, simultaneously carrying out serial-to-parallel operation with the coefficient of m on the carrier signals of the N frequency points for frequency mixing. N groups of parallel m paths of carrier waves are finally obtained, wherein the nth group of parallel carrier waves has a signal Bn(1)，Bn(2)，…，Bn(m) a rate of each carrier signal of fs/m；
Step four, multiplying the parallel m paths of frequency division signals by the parallel m paths of carriers to complete multi-path parallel frequency mixing operation to obtain m paths of mixed frequency signals C1(1)，C1(2)，…，C1(m) where the subscript "1" denotes the mixed signal at frequency point 1, C1(1) Then represents the first path of signal after mixing of frequency point 1, C1(2) The second channel of signals after the frequency mixing of the frequency point 1 is represented, and so on. Repeating the frequency mixing operation for N-1 times to finally obtain N groups of m-path frequency-mixed signals respectively as C1(1)，C1(2)，…，C1(m),C2(1)，C2(2)，…，C2(m),……,CN(1)，CN(2)，…，CN(m)；
And step five, overlapping the results obtained in the step four after the multi-channel parallel frequency mixing, wherein the overlapping method comprises the following steps: superposing the same path of signals in the N groups of mixing signals to finally obtain m paths of superposed mixing signals D (1), D (2), …, D (m), wherein the ith path of mixing signal is D (i) C1(i)C2(i)，…，CN(i) At the time, the rate of each signal is fs/m；
And step six, performing m-time delay extraction operation on the low-pass filter coefficients for filtering to obtain m parallel sub-filters LP (1), LP (2), …, LP (m). Filtering the m channels of superposed mixing signals D (1), D (2), …, D (m) obtained in the step five with the m channels of sub-filters LP (1), LP (2), …, LP (m) in the step seven respectively to finally obtain m channels of filtered signals G (1), G (2), … and G (m);
and step seven, overlapping the m paths of filtered signals G (1), G (2), …, G (m) obtained in the step six to obtain a final demodulated signal S G (1), G (2), … G (m).
And the multi-path parallel demodulation of the ultra-high-speed frequency division signal based on the FPGA is completed through the seven steps.
Advantageous effects
The invention relates to a multi-path parallel demodulation method of an ultra-high-speed frequency division signal based on an FPGA (field programmable gate array).
The traditional ultra-high-speed frequency division signal processing mode needs to add an external analog down converter and needs a multi-channel mixing and low-pass filter module corresponding to the number of frequency points. The external analog down converter is high in price, and the weight and the size of equipment are increased; meanwhile, the multi-path parallel operation consumes a large amount of FPGA resources such as DSP48, Slice and the like, and has higher requirements on the capacity of common FPGA chip resources.
The method adopts a multi-path parallel rate reduction processing mode, and the rate of each path of parallel data is reduced by carrying out parallel processing on the high-speed signals, but the real-time processing rate in the FPGA still keeps ultra high speed, so that the mode avoids the use of an external analog down converter, improves the system performance, simplifies the system structure and reduces the system cost; on the other hand, after the mixed parallel multi-channel signals are superposed, the parallel multi-channel signals pass through the parallel sub low-pass filters together, namely, from the FPGA implementation perspective, the low-pass filtering is transferred to the common branch, and by the method, N-1(N is the frequency point number of the frequency division signals) low-pass filter modules can be reduced, so that the resource consumption is obviously reduced.
In conclusion, the invention adopts the FPGA-based multi-path parallel demodulation method for the ultra-high-speed frequency division signals, reduces the number of hardware equipment, simplifies the realization algorithm and structure, and greatly saves hardware resources and cost.
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FIG. 1 is a flow chart of a conventional FPGA-based ultra-high-speed frequency division signal demodulation method;
fig. 2 is a schematic flow chart of a method for multi-path parallel demodulation of an ultra-high-speed frequency division signal based on an FPGA according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings and embodiments, and technical problems and advantages solved by the technical solutions of the present invention will be described, wherein the described embodiments are only intended to facilitate understanding of the present invention, and do not limit the present invention in any way.
Fig. 1 is a schematic flow chart of a conventional FPGA-based ultra-high-speed frequency division signal demodulation method, and a main method is to convert a frequency division analog signal into a low-speed analog signal by an external analog down converter. After the analog signal is converted into a digital signal by the analog-to-digital conversion chip, the signal is input into the FPGA. And multiplying and filtering the low-speed analog frequency division signal obtained in the last step and the carrier waves with the corresponding frequency division number respectively, and adding the obtained multi-channel parallel data to realize the demodulation of the high-speed frequency division signal.
Fig. 2 is a schematic flow chart of a method for demodulating an ultra-high-speed frequency division signal in a multipath and parallel manner based on an FPGA according to an embodiment of the present invention, and the method mainly includes converting an analog signal into a digital signal directly from a high-speed analog frequency division signal through an analog-to-digital conversion chip, and inputting the digital signal into the FPGA. And performing serial-parallel conversion on the high-speed digital frequency division signals to generate parallel m-path low-speed digital frequency division signals. And respectively carrying out the same serial-parallel conversion on the carrier signals corresponding to the frequency division number, wherein each carrier generates m paths of parallel subcarriers. The filter is converted into m sub-filters by the same serial-to-parallel conversion. And multiplying each path of low-speed digital frequency division signals by the same subcarrier of the path number, accumulating the multiplied results, and passing the accumulated sum result through a sub-filter of the path number. And adding the m paths of parallel signals which pass through the sub-filters to realize the demodulation of the high-speed frequency division signal.
The specific implementation process of the present invention is described by taking the frequency division signal of 3 frequency points as an example. The original signal rate is 1000Mbps, and the number of parallel paths is 4.
The method comprises the following steps that firstly, a receiving end directly receives an ultra-high-speed analog frequency division signal, an analog-to-digital conversion chip carries out analog-to-digital conversion on a high-frequency signal and inputs the high-frequency signal to an FPGA (field programmable gate array), the rate of an original signal is 1000Mbps, and the number of frequency points of the frequency division signal is 3;
and step two, the FPGA receives the digital signal in the step one and carries out serial-to-parallel operation with the coefficient of 4 on the signal. Then, 4 paths of parallel data A (1), A (2), A (3) and A (4) are finally obtained, and the rate of each path of frequency division signal is 250 Mbps;
and step three, simultaneously carrying out serial-to-parallel operation with the coefficient of 4 on the carrier signals of the 3 frequency points for frequency mixing. Finally obtaining 4 parallel paths of carrier signals cos (1), cos (2), cos (3) and cos (4), wherein the rate of each path of carrier signal is 250 Mbps;
step four, multiplying the parallel 4 paths of frequency division signals by the parallel 4 paths of carriers to complete the multi-path parallel frequency mixing operation to obtain 4 paths of mixed-frequency signals C1(1)，C1(2)，C1(3)，C1(4) Wherein the subscript "1" denotes the mixed signal at frequency point 1, C1(1) Then represents the first path of signal after mixing of frequency point 1, C1(2) The second channel of signals after the frequency mixing of the frequency point 1 is represented, and so on. 3 times of mixing operation are carried out, and 3 groups of m-path mixed signals are finally obtained, wherein the signals are respectively C1(1)，C1(2)，C1(3)，C1(4),C2(1)，C2(2)，C2(3)，C2(4),C3(1)，C31(2)，C3(3)，C3(4)；
And step five, overlapping the results obtained in the step four after the multi-channel parallel frequency mixing, wherein the overlapping method comprises the following steps: superposing the same path of signals in the 3 groups of mixing signals to finally obtain 4 paths of superposed mixing signals, wherein the ith path of mixing signal is D (i) C1(i)C2(i)C3(i) At this time, the rate of each path of signal is 250 Mbps;
and step six, performing 4-time delay extraction on the low-pass filter coefficients for filtering to obtain 4 parallel sub-filters LP (1), LP (2), … and LP (4). Filtering the 4 paths of superposed mixing signals D (1), D (2), … and D (4) obtained in the step five with 4 paths of sub-filters LP (1), LP (2), … and LP (4) respectively to finally obtain 4 paths of filtered signals G (1), G (2), … and G (4);
and step seven, superposing the 4 paths of filtered signals G (1), G (2), … and G (4) obtained in the step six to obtain a final demodulated signal S G (1), G (2) … G (4).
For the above embodiment, the following table shows comparison of FPGA resource consumption of the conventional FPGA-based ultra-high-speed frequency division signal demodulation method and the FPGA-based ultra-high-speed frequency division signal multi-path parallel demodulation method of the present embodiment, where the model of the FPGA used in this embodiment is XC7K325T of Xilinx Kintex-7 series.
The above table shows that the traditional method has huge resource consumption, and part of FPGA resources even exceed the chip resource limit, but the FPGA-based multi-path parallel demodulation method for the ultra-high-speed frequency division signals greatly reduces the consumption of the FPGA resources, and has remarkable effect on saving three resources, namely Slice Registers, Slice LUTs and DSP48E1 s.
The above detailed description is intended to illustrate the objects, aspects and advantages of the present invention, and it should be understood that the above detailed description is only exemplary of the present invention and is not intended to limit the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (1)
1. A multi-path parallel demodulation method of an ultra-high-speed frequency division signal based on an FPGA comprises the following steps:
step one, a receiving end receives an ultra-high speed analog frequency division signal, an analog-to-digital conversion chip carries out analog-to-digital conversion on the received ultra-high speed analog frequency division signal and inputs the converted ultra-high speed analog frequency division signal to FPGA (field programmable gate array), and the rate of the ultra-high speed analog frequency division signal is made to be fsThe number of frequency points of the frequency division signal is N;
step two, FPGA receives the digital signal of step one, and carry on the serial conversion parallel operation that the coefficient is m with the signal, then obtain m routes of data A (1), A (2), …, A (m) that are parallel finally, the speed of each route frequency division signal is fs/m；
Step three, simultaneously carrying out serial-to-parallel operation with the coefficient of m on the carrier signals of the N frequency points for frequency mixing, and finally obtaining N groups of parallel m-path carriers, wherein the nth group of parallel carriersThe carrier signal of is Bn(1)，Bn(2)，…，Bn(m) a rate of each carrier signal of fs/m；
Step four, multiplying the parallel m paths of frequency division signals by the parallel m paths of carriers to complete multi-path parallel frequency mixing operation to obtain m paths of mixed frequency signals C1(1)，C1(2)，…，C1(m) where the subscript "1" denotes the mixed signal at frequency point 1, C1(1) Then represents the first path of signal after mixing of frequency point 1, C1(2) Then the second channel of signals after frequency mixing of the frequency point 1 is represented, and by analogy, the frequency mixing operation is carried out for N times, and finally N groups of m channels of signals after frequency mixing are obtained, wherein C is respectively1(1)，C1(2)，…，C1(m),C2(1)，C2(2)，…，C2(m),……,CN(1)，CN(2)，…，CN(m)；
And step five, overlapping the results obtained in the step four after the multi-channel parallel frequency mixing, wherein the overlapping method comprises the following steps: superposing the same path of signals in the N groups of mixing signals to finally obtain m paths of superposed mixing signals D (1), D (2), …, D (m), wherein the ith path of mixing signal is D (i) C1(i) C2(i)，…，CN(i) At the time, the rate of each signal is fs/m；
Sixthly, performing m-time delay extraction on the low-pass filter coefficients for filtering to obtain m parallel sub-filters LP (1), LP (2), …, LP (m), filtering the m superposed mixing signals D (1), D (2), …, D (m) obtained in the fifth step with the m sub-filters LP (1), LP (2), …, LP (m), and finally obtaining m filtered signals G (1), G (2), …, G (m);
and step seven, overlapping the m paths of filtered signals G (1), G (2), …, G (m) obtained in the step six to obtain a final demodulated signal S G (1), G (2), … G (m).
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| CN112083674A (en) * | 2020-09-09 | 2020-12-15 | 中国航空工业集团公司雷华电子技术研究所 | FPGA chip data processing method, chip, computer equipment and storage medium |
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