CN110808713B - Ultrahigh-speed frequency division signal multipath parallel demodulation method based on FPGA - Google Patents
Ultrahigh-speed frequency division signal multipath parallel demodulation method based on FPGA Download PDFInfo
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Abstract
The invention provides an ultra-high-speed frequency division signal multipath parallel demodulation method based on an FPGA. And (3) carrying out serial-parallel conversion on the high-speed digital frequency division signals to generate m parallel low-speed digital frequency division signals. And respectively carrying out same serial-parallel conversion on carrier signals corresponding to the frequency division number, and generating m parallel sub-carriers by each carrier. The filters are converted into m sub-filters by the same serial-parallel conversion. And multiplying each path of low-speed digital frequency division signal by the same subcarrier of the path number, accumulating the multiplied result, and passing the accumulated result through a sub-filter of the path number. And adding the m paths of signals which are obtained and are subjected to the sub-filter in parallel, so that the demodulation of the high-speed frequency division signals can be realized. The invention greatly reduces the consumption of FPGA resources.
Description
Technical Field
The invention belongs to the technical field of ultrahigh-speed frequency division signal demodulation, and particularly relates to an ultrahigh-speed frequency division signal multipath parallel demodulation method based on an FPGA.
Background
With the development of communication technology in recent years, the demand for ultra-high-speed signal processing is becoming more urgent. Aiming at the ultra-high-speed analog frequency division signals, the traditional processing mode is that firstly, the ultra-high-speed signals are subjected to frequency mixing through an external analog down converter to reduce the speed, then digital down conversion based on an FPGA is carried out, the low-speed frequency division signals pass through a frequency mixing and low-pass filter module corresponding to the number of frequency points in parallel, and finally, the demodulation of the ultra-high-speed frequency division signals is completed.
In practical application, the external analog down converter is expensive, the reliability and the signal processing performance are poor, and the weight and the size of the equipment are increased due to the addition of the external module; on the other hand, in the FPGA implementation process, a plurality of paths of parallel mixing and low-pass filter modules are required to consume a large amount of FPGA resources, and the number of parallel paths is increased in proportion to the number of parallel frequency division signal frequency points, so that the resource consumption of the resources can not be estimated by adopting the traditional method. The traditional ultra-high-speed frequency division signal demodulation method cannot meet the requirements of high efficiency and high benefit of current signal processing.
Disclosure of Invention
The invention aims to solve the problems of complex ultra-high-speed frequency division signal demodulation hardware equipment and large consumption of FPGA resources, and provides an ultra-high-speed frequency division signal multipath parallel demodulation method based on the FPGA.
The invention is realized by the following technical scheme:
the ultra-high speed frequency division signal multipath parallel demodulation method based on the FPGA mainly comprises the following steps:
step one, a receiving end receives an ultra-high-speed analog frequency division signal, an analog-to-digital conversion chip carries out analog-to-digital conversion on the received ultra-high-speed analog frequency division signal, and the ultra-high-speed analog frequency division signal is input to an FPGA, so that the speed of the ultra-high-speed analog frequency division signal is f s The number of frequency points of the frequency division signal is N;
and step two, the FPGA receives the digital signal in the step one, and the signal is subjected to serial-to-parallel operation with the coefficient m. Finally, m paths of parallel data A (1), A (2), … and A (m) are obtained, and the rate of each path of frequency division signal is f s /m；
And thirdly, simultaneously carrying out serial-to-parallel operation with the coefficient of m on carrier signals of N frequency points used for mixing. Finally obtaining N groups of parallel m paths of carriers, wherein the nth group of parallel carrier signals are B n (1)，B n (2)，…，B n (m) the rate of each carrier signal is f s /m；
Multiplying the m parallel frequency division signals with m parallel carriers to finish multi-path parallel mixing operation and obtain m mixed signals C 1 (1)，C 1 (2)，…，C 1 (m), wherein the subscript "1" represents the mixed signal of frequency bin 1, C 1 (1) Then the first path of mixed signals of the frequency point 1 is represented, C 1 (2) The mixed second signal representing bin 1 and so on. Repeating the mixing operation for N-1 times to obtain N groups of m mixed signals, which are C respectively 1 (1)，C 1 (2)，…，C 1 (m),C 2 (1)，C 2 (2)，…，C 2 (m),……,C N (1)，C N (2)，…，C N (m)；
And step five, superposing the multipath parallel mixing results obtained in the step four, wherein the superposition method comprises the following steps: the same path of signals in the N paths of mixed signals are overlapped to finally obtain m paths of overlapped mixed signals D (1), D (2), … and D (m), wherein the ith path of mixed signals are D (i) C 1 (i)C 2 (i)，…，C N (i) At this time, the rate of each signal is f s /m；
And step six, performing m times delay extraction operation on the low-pass filter coefficient for filtering to obtain parallel m sub-filters LP (1), LP (2), … and LP (m). Filtering the m paths of superposition mixed signals D (1), D (2), … and D (m) obtained in the fifth step with m sub-filters LP (1), LP (2), … and LP (m) in the seventh step to finally obtain m paths of filtered signals G (1), G (2), … and G (m);
and seventhly, superposing the m paths of filtered signals G (1), G (2), … and G (m) obtained in the step six to obtain a final demodulated signal of S G (1) G (2) … G (m).
The ultra-high-speed frequency division signal multiplexing parallel demodulation based on the FPGA is completed through the seven steps.
Advantageous effects
The invention relates to an ultra-high-speed frequency division signal multipath parallel demodulation method based on an FPGA.
The traditional ultra-high-speed frequency division signal processing mode needs to be added with an external analog down converter, and meanwhile, multiple frequency mixing and low-pass filter modules corresponding to the number of frequency points are needed. The external analog down converter is high in price, and the weight and the size of equipment are increased; meanwhile, a large amount of FPGA resources such as DSP48 and Slice can be consumed by multipath parallel operation, and the requirement on the resource capacity of a common FPGA chip is high.
The method adopts a multi-path parallel speed-reducing processing mode, and the speed of each path of parallel data is reduced by carrying out parallel processing on high-speed signals, but the real-time processing speed in the FPGA still maintains the ultra-high speed, so that the method avoids the use of an external analog down converter, improves the system performance, simplifies the system structure and simultaneously reduces the system cost; on the other hand, the mixed parallel multipath signals are overlapped and then pass through the parallel sub low-pass filters together, namely, the low-pass filtering is transferred to a common branch from the viewpoint of FPGA realization, N-1 (N is the number of frequency points of the frequency division signals) low-pass filter modules can be reduced, and the resource consumption is obviously reduced.
In summary, the ultra-high-speed frequency division signal multiplexing parallel demodulation method based on the FPGA is adopted, so that the number of hardware devices is reduced, the implementation algorithm and structure are simplified, and the hardware resources and cost are greatly saved.
Drawings
Fig. 1 is a flow chart of a conventional ultra-high-speed frequency division signal demodulation method based on an FPGA;
fig. 2 is a flow chart of a method for multiplexing and parallel demodulating ultrahigh-speed frequency division signals based on an FPGA according to an embodiment of the invention.
Detailed Description
The technical problems and advantages solved by the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and examples, and it should be noted that the described examples are only intended to facilitate understanding of the present invention and are not intended to limit the present invention in any way.
Fig. 1 is a flow chart of a traditional ultra-high-speed frequency division signal demodulation method based on an FPGA, and the main method is that a frequency division analog signal is converted into a low-speed analog signal by an external analog down converter. After the analog signals are converted into digital signals through the analog-to-digital conversion chip, the signals are input into the FPGA. And multiplying and filtering the low-speed analog frequency division signal obtained in the last step with carriers with the corresponding frequency division number respectively, and adding the obtained multipath parallel data to realize the demodulation of the high-speed frequency division signal.
Fig. 2 is a schematic flow chart of a method for multiplexing and demodulating ultrahigh-speed frequency-division signals based on an FPGA according to an embodiment of the present invention, where the main method is to directly convert high-speed analog frequency-division signals into analog signals through an analog-to-digital conversion chip, and then input the signals into the FPGA. And (3) carrying out serial-parallel conversion on the high-speed digital frequency division signals to generate m parallel low-speed digital frequency division signals. And respectively carrying out same serial-parallel conversion on carrier signals corresponding to the frequency division number, and generating m parallel sub-carriers by each carrier. The filters are converted into m sub-filters by the same serial-parallel conversion. And multiplying each path of low-speed digital frequency division signal by the same subcarrier of the path number, accumulating the multiplied result, and passing the accumulated result through a sub-filter of the path number. And adding the m paths of signals which are obtained and are subjected to the sub-filter in parallel, so that the demodulation of the high-speed frequency division signals can be realized.
Taking frequency division signals of 3 frequency points as an example, the specific implementation process of the invention is described. Wherein the original signal rate is 1000Mbps, and the parallel path number is 4.
The method comprises the steps that firstly, a receiving end directly receives an ultra-high-speed analog frequency division signal, an analog-to-digital conversion chip carries out analog-to-digital conversion on a high-frequency signal and inputs the high-frequency signal to an FPGA, the speed of an original signal is 1000Mbps, and the number of frequency points of the frequency division signal is 3;
and step two, the FPGA receives the digital signal in the step one and carries out serial-to-parallel operation with the coefficient of 4 on the signal. Finally, 4 paths of parallel data A (1), A (2), A (3), A (4) are obtained, and the speed of each path of frequency division signal is 250Mbps;
and thirdly, simultaneously carrying out serial-to-parallel operation with the coefficient of 4 on carrier signals of 3 frequency points used for mixing. Finally, 4 paths of parallel carrier waves cos (1), cos (2), cos (3), cos (4) are obtained, and the speed of each path of carrier wave signal is 250Mbps;
multiplying the parallel 4-channel frequency division signals with the parallel 4-channel carriers to finish multi-channel parallel mixing operation and obtain 4-channel mixed signals C 1 (1)，C 1 (2)，C 1 (3)，C 1 (4) Wherein the subscript "1" denotes the mixed signal of frequency point 1, C 1 (1) Then the first path of mixed signals of the frequency point 1 is represented, C 1 (2) The mixed second signal representing bin 1 and so on. The mixing operation is carried out for 3 times, and finally 3 groups of m mixed signals are obtained, wherein the m mixed signals are respectively C 1 (1)，C 1 (2)，C 1 (3)，C 1 (4),C 2 (1)，C 2 (2)，C 2 (3)，C 2 (4),C 3 (1)，C 31 (2)，C 3 (3)，C 3 (4)；
And step five, superposing the multipath parallel mixing results obtained in the step four, wherein the superposition method comprises the following steps: the same path of signals in the 3 paths of mixed signals are overlapped to finally obtain 4 paths of overlapped mixed signals, wherein the ith path of mixed signals is D (i) C 1 (i)C 2 (i)C 3 (i) At this time, the rate of each signal is 250Mbps;
and step six, performing 4 times delay extraction operation on the low-pass filter coefficient for filtering to obtain 4 parallel sub-filters LP (1), LP (2), … and LP (4). Filtering the 4 paths of superimposed mixed signals D (1), D (2), … and D (4) obtained in the fifth step with 4 sub-filters LP (1), LP (2), … and LP (4) respectively to finally obtain 4 paths of filtered signals G (1), G (2), … and G (4);
and step seven, superposing the 4 paths of filtered signals G (1), G (2), … and G (4) obtained in the step six to obtain a final demodulated signal S G (1) G (2) … G (4).
For the above embodiment, the following table is a comparison of FPGA resource consumption using the conventional FPGA-based ultrahigh-speed frequency-division signal demodulation method and the FPGA-based ultrahigh-speed frequency-division signal multiplexing parallel demodulation method of this embodiment, and the FPGA model used in this example is XC7K325T of the Xilinx kinex-7 series.
The method has the advantages that the consumption of resources is huge, part of FPGA resources even exceed the limit of chip resources, the FPGA-based ultrahigh-speed frequency division signal multipath parallel demodulation method greatly reduces the consumption of FPGA resources, and the method has remarkable effect in the aspect of saving three resources of Slice Registers, slice LUTs and DSP48E1 s.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (1)
1. An ultra-high-speed frequency division signal multipath parallel demodulation method based on an FPGA comprises the following steps:
step one, a receiving end receives an ultra-high-speed analog frequency division signal, an analog-to-digital conversion chip carries out analog-to-digital conversion on the received ultra-high-speed analog frequency division signal, and the ultra-high-speed analog frequency division signal is input to an FPGA, so that the speed of the ultra-high-speed analog frequency division signal is f s The number of frequency points of the frequency division signal is N;
step two, the FPGA receives the digital signal in the step one, and carries out serial-to-parallel operation with the coefficient of m, so that m parallel data A (1), A (2), … and A (m) are finally obtained, and the rate of each path of frequency division signal is f s /m；
Step three, carrying out serial-to-parallel operation with the coefficient of m on carrier signals of N frequency points used for mixing, so as to finally obtain N groups of parallel m paths of carriers, wherein the N groups of parallel carrier signals are B n (1)，B n (2)，…，B n (m) the rate of each carrier signal is f s /m；
Multiplying the m parallel frequency division signals with m parallel carriers to finish multi-path parallel mixing operation and obtain m mixed signals C 1 (1)，C 1 (2)，…，C 1 (m), wherein the subscript "1" represents the mixed signal of frequency bin 1, C 1 (1) Then the first path of mixed signals of the frequency point 1 is represented, C 1 (2) The second mixed signal representing the frequency point 1 is subjected to N times of mixing operations, and N groups of m mixed signals are finally obtained and are respectively C 1 (1)，C 1 (2)，…，C 1 (m),C 2 (1)，C 2 (2)，…，C 2 (m),……,C N (1)，C N (2)，…，C N (m)；
Step five, willAnd step four, overlapping the obtained multipath parallel mixing results, wherein the overlapping method comprises the following steps: the same path of signals in the N paths of mixed signals are overlapped to finally obtain m paths of overlapped mixed signals D (1), D (2), … and D (m), wherein the ith path of mixed signals are D (i) C 1 (i) C 2 (i)，…，C N (i) At this time, the rate of each signal is f s /m；
Step six, performing m times delay extraction operation on low-pass filter coefficients for filtering to obtain parallel m sub-filters LP (1), LP (2), … and LP (m), and filtering m superimposed mixed signals D (1), D (2), … and D (m) obtained in the step five with the m sub-filters LP (1), LP (2), … and LP (m) respectively to finally obtain m filtered signals G (1), G (2), … and G (m);
and seventhly, superposing the m paths of filtered signals G (1), G (2), … and G (m) obtained in the step six to obtain a final demodulated signal of S G (1) G (2) … G (m).
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