CN112071908A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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Publication number
CN112071908A
CN112071908A CN201910497868.XA CN201910497868A CN112071908A CN 112071908 A CN112071908 A CN 112071908A CN 201910497868 A CN201910497868 A CN 201910497868A CN 112071908 A CN112071908 A CN 112071908A
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substrate
layer
forming
gate structure
semiconductor device
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201910497868.XA priority Critical patent/CN112071908A/zh
Priority to US16/898,002 priority patent/US20200388699A1/en
Publication of CN112071908A publication Critical patent/CN112071908A/zh
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Abstract

本发明提供一种半导体器件以及形成方法，包括：提供衬底，在所述衬底上交替形成第一衬层和第二衬层；刻蚀所述第一衬层、所述第二衬层以及部分厚度的所述衬底，在所述衬底上形成若干分立排布的鳍部；所述鳍部包括第一区和第二区；在第二区相邻所述鳍部之间填充满绝缘层；在所述衬底上形成伪栅结构，所述伪栅结构横跨所述鳍部，所述伪栅结构的顶部与所述绝缘层的顶部齐平；利用本发明的形成方法，使得形成的半导体器件的使用性能得到提高。

Description

半导体器件及其形成方法
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体器件及其形成方法。
背景技术
随着半导体制造技术的飞速发展，半导体器件朝着更高的元件密度，以及更高的集成度的方向发展。器件作为最基本的半导体器件，目前正被广泛应用，传统的平面器件对沟道电流的控制能力变弱，产生短沟道效应而导致漏电流，最终影响半导体器件的电学性能。
为了克服器件的短沟道效应，抑制漏电流，现有技术提出了鳍式场效应晶体管(Fin FET)，鳍式场效应晶体管是一种常见的多栅器件，鳍式场效应晶体管的结构包括：位于半导体衬底表面的鳍部和隔离结构，所述隔离结构覆盖部分所述鳍部的侧壁，位于衬底上且横跨的栅极结构；位于所述栅极结构两侧的鳍部内的源区和漏区。
随着对器件性能不断提出的更高要求，催生了四面控制的全包围栅结构(Gate-all-around)。具有全包围栅极(Gate-all-around)结构的半导体器件拥有有效地限制短沟道效应(Short channel effect)的特殊性能，正是业界在遵循摩尔定律不断缩小器件尺寸的革新中所极其渴望的。全包围栅极结构中的薄硅膜构成的器件沟道被器件的栅极包围环绕，而且仅被栅极控制。
如何形成全包围栅结构，从而提高半导体器件的使用性能，这是目前急需解决的问题。
发明内容
本发明解决的问题是提供一种半导体器件及其形成方法，使得形成的半导体器件的使用性能得到提高。
为解决上述问题，本发明提供半导体器件的形成方法，包括：提供衬底，在所述衬底上交替形成第一衬层和第二衬层；刻蚀所述第一衬层、所述第二衬层以及部分厚度的所述衬底，在所述衬底上形成若干分立排布的鳍部；所述鳍部包括第一区和第二区；在所述第二区相邻所述鳍部之间填充满绝缘层；在所述衬底上形成伪栅结构，所述伪栅结构横跨所述鳍部，所述伪栅结构的顶部与所述绝缘层的顶部齐平。
可选的，所述绝缘层的材料包括氧化硅、氮化硅、氮氧化硅、碳氮化硅中的一种或者多种。
可选的，形成所述伪栅结构之后，还包括：去除所述伪栅结构以及所述第一衬层，在相邻的所述第二衬层以及所述衬底与所述第二衬层之间形成沟道；在所述衬底上形成栅极结构，所述栅极结构横跨所述第二衬层且填充满所述沟道。
可选的，所述第一衬层的材料与所述第二衬层的材料不同，所述第一衬层的材料包括硅、锗、硅锗、砷化镓中的一种或者多种。
可选的，所述第二衬层的材料包括硅、锗、硅锗、砷化镓中的一种或者多种。
可选的，还包括，在所述衬底上形成隔离结构，所述隔离结构覆盖部分所述鳍部的侧壁。
可选的，还包括硬掩膜层，所述硬掩膜层位于所述鳍部的顶部。
可选的，在所述衬底上形成所述伪栅结构之前，去除所述硬掩膜层。
可选的，采用外延层生长方式在所述衬底上交替形成所述第一衬层和所述第二衬层。
利用上述方法形成的一种半导体器件，包括：衬底；若干鳍部，包括第一区和第二区，分立排布于所述衬底上，且各所述鳍部由部分厚度的衬底、第一衬层以及第二衬层组成；其中：第一衬层，位于所述衬底以及所述第二衬层上；第二衬层，位于所述第一衬层上；绝缘层，填充满任意区相邻所述鳍部之间；伪栅结构，位于所述衬底上，横跨所述鳍部且顶部与绝缘层的顶部齐平。
与现有技术相比，本发明的技术方案具有以下优点：
首先在衬底上形成鳍部，鳍部由第一衬层、第二衬层和部分厚度的衬底组成，鳍部包括第一区和第二区，在第二区相邻鳍部之间填充满切断栅极结构的绝缘层，形成绝缘层之后，再在衬底上形成伪栅结构；一方面由于绝缘层是填充满在相邻的鳍部之间，此时绝缘层和鳍部之间是紧密接触的，绝缘层和鳍部之间没有间距，因此形成的半导体器件的集成度得到提高；另一方面，绝缘层是在形成伪栅结构之前形成的，而且是填充满相邻鳍部之间从而切断形成的伪栅结构，那么后续去除伪栅结构形成栅极结构时，形成的栅极结构不会在鳍部和绝缘层之间出现孔洞或者间隙的现象，保证形成的栅极结构的质量；同时去除鳍部上的第一衬层，栅极结构又能够包围在第二衬层的周围，这种包围第二衬层的栅极具有较大的栅极有效宽度，便于提高形成的半导体器件的质量。
附图说明
图1至图6是一实施例中半导体器件形成过程的结构示意图；
图7至图10是本发明第一实施例中半导体器件形成过程的结构示意图；
图11至图17是本发明第二实施例中半导体器件形成过程的结构示意图。
具体实施方式
在半导体器件中，通常利用多晶硅栅极切割掩膜(Poly gate cut mask，P2)来获得矩形线端(rectangular-shape line end)，从而可以更好地控制栅极图案并提高半导体器件的密度，具体半导体器件的形成方法如下：
参考图1，提供衬底1，所述衬底1上交替形成第一衬层11和第二衬层12。
参考图2，刻蚀所述第一衬层11、所述第二衬层12以及部分厚度的所述衬底1，在所述衬底1上形成若干分立排布的鳍部2。
所述鳍部2包括第一区21和第二区22。
参考图3，在所述衬底1上形成伪栅结构3，所述伪栅结构3横跨所述鳍部2。
参考图4，在所述伪栅结构3上形成开口4，所述开口4位于第二区22的相邻的鳍部2之间。
参考图5，在所述开口4内填充满绝缘层5。
参考图6，去除所述伪栅结构3以及所述第一衬层11，在所述衬底1上形成栅极结构6，所述栅极结构6包围所述第二衬层12。
发明人发现，这种方法形成的半导体器件具有较差的使用性能稳定性，同时形成的半导体器件的集成度低，限制了半导体器件的使用。形成的半导体器件的集成度低的原因是形成绝缘层时，绝缘层是填充在伪栅结构形成的开口内，形成的绝缘层与鳍部之间有伪栅结构，这样鳍部和绝缘层之间的就存在一定的距离，导致形成空间的浪费；形成的半导体器件在使用的过程中具有较差的稳定性差的原因是在去除伪栅结构和第一衬层形成栅极结构时，由于鳍部和绝缘层之间的间隙较小，这样在填充栅极结构时，间隙内部的气压对栅极结构的作用强，容易在栅极结构内部形成孔洞或者缝隙的现象，这种孔洞或者缝隙容易造成半导体器件使用功能的失效，限制半导体器件的使用。
发明人研究发现，在衬底上形成鳍部之后，先在需要形成切断栅极结构的相邻的鳍部之间填充满绝缘层，之后再形成伪栅结构，这种方法形成的半导体器件具有较高的集成度，同时形成的半导体器件具有稳定的使用性能；由于这种方式形成绝缘层和鳍部之间是没有间隙的，两者是接触在一起，不仅提高了半导体器件的空间集成度，而且由于间隙的消除，更容易获得较小的电路尺寸；同时去除伪栅结构和第一衬层形成栅极结构的时候，由于鳍部和绝缘层之间没有间隙，在形成栅极结构时，不存在阻力，保证形成的栅极结构内不存在孔洞或缝隙的缺陷，使得形成的半导体器件具有稳定的使用性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细地说明。
第一实施例
图7至图10是本发明第一实施例中半导体器件形成过程的结构示意图。
首先参考图7，提供衬底100，在所述衬底100上交替形成所述第一衬层110和所述第二衬层120。
本实施例中，所述衬底100的材料为单晶硅；其他实施例中，所述衬底100也可以是多晶硅、非晶硅、锗、锗化硅、砷化镓等半导体材料。
本实施例中，所述第一衬层110的材料与所述第二衬层120的材料不同，所述第一衬层110的材料为硅锗(SiGe)；其他实施例中，所述第一衬层110的材料还可为硅、锗、砷化镓中的一种或者多种。
本实施例中，所述第二衬层120的材料为硅(Si)；其他实施例中，所述第二衬层120的材料还可为硅锗、锗、砷化镓中的一种或者多种。
本实施例中，采用外延生长方式在所述衬底100上形成所述第一衬层110、和所述第二衬层120。
其他实施例中，还可采用离子掺杂的方式或者化学气相沉积方法在所述衬底100上形成所述第一衬层110和所述第二衬层120。
本实施例中，形成所述第一衬层110的工艺参数包括采用硅烷(SiH4)和锗烷(GeH4)作为环境气氛，其中硅烷(SiH4)和锗烷(GeH4)的气体百分数比控制在20～50％之间，压强范围1～100托；温度为400℃～600℃之间，反应时间控制在10min～1h之间。
本实施例中，形成所述第二衬层120的工艺参数包括采用硅烷(SiH4)作为环境气氛，所述SiH4气体的气体流量为10～700sccm；压强范围1～100托；温度为400℃～600℃之间，反应时间控制在10min～1h之间。
参考图8，刻蚀所述第一衬层110、所述第二衬层120以及部分厚度的所述衬底100，在所述衬底100上形成若干分立排布的鳍部200，所述鳍部200包括第一区210和第二区220。
本实施例中，栅极结构横跨所述第一区210的鳍部，栅极结构是不被切断的，栅极结构横跨所述第二区220的鳍部时，栅极结构在第二区220鳍部之间是被切割开的，从而获得矩形线端。
本实施例中，采用干法刻蚀所述第一衬层110、所述第二衬层120以及部分厚度的所述衬底100，从而在所述衬底100上形成所述鳍部200。
本实施例中，所述干法刻蚀工艺的参数包括：采用的刻蚀气体包括HBr和Ar，其中，HBr的流速为10sccm～1000sccm，Ar的流速为10sccm～1000sccm。
参考图9，在所述第二区220的所述鳍部200之间填充满所述绝缘层300。
本实施例中，在所述第二区220的所述鳍部200之间填充满所述绝缘层300；其他实施例中，还可在所述第一区210的所述鳍部200之间形成填充满所述绝缘层300。
本实施例中，所述第二区220是位于栅极结构的切割区，所述切割区是指在该区域栅极结构被所述绝缘层300切割的地方。
本实施例中，所述绝缘层300的材料为氧化硅；其他实施例中，所述绝缘层300的材料还可为氮化硅、氮氧化硅、碳氮化硅中的一种或者多种。
本实施例中，由于所述绝缘层300填充满所述第二区220的所述鳍部200之间，所述绝缘层300与所述鳍部200之间紧密接触，消除了所述绝缘层300与所述鳍部200之间的间隙，从而提高了形成的半导体器件的集成度，节约空间。
参考图10，在所述衬底100上形成伪栅结构400，所述伪栅结构400横跨所述鳍部200，所述伪栅结构400的顶部与所述绝缘层300的顶部齐平。
本实施例中，形成所述伪栅结构400包括伪栅介质层(图中未画出)和伪栅极层。
本实施例中，所述伪栅极层的材料为多晶硅。
本实施例中，一方面由于所述绝缘层300和所述鳍部200之间没有间隙，节约了空间，同时形成所述伪栅结构400的时候，就不会在所述绝缘层300和所述鳍部200之间形成所述伪栅结构400，从而后续去除所述伪栅结构400时形成栅极结构时，就不会在所述绝缘层300和所述鳍部200之间有残留的所述伪栅结构400；另一方面，去除所述伪栅结构400形成栅极结构的时候，栅极结构也不会在所述鳍部200和所述绝缘层300之间出现孔洞或者缝隙的缺陷，从而提高形成的半导体器件的使用性能，保证半导体器件具有稳定的使用性能。
利用上述方法形成的一种半导体器件，包括衬底100；若干鳍部200，包括第一区210和第二区220，分立排布于所述衬底100上，且各所述鳍部由部分厚度的所述衬底100、所述第一衬层110和所述第二衬层120组成；其中，所述第一衬层110，位于所述衬底100以及所述第二衬层120上；所述第二衬层120，位于所述第一衬层110上；绝缘层300，填充满所述第二区220相邻的所述鳍部200之间；伪栅结构400，位于所述衬底100上，且横跨所述鳍部200。
第二实施例
图11至图17是本发明第二实施例中半导体器件形成过程的结构示意图。
参考图11，提供衬底100，在所述衬底100上交替形成所述第一衬层110和所述第二衬层120，在所述第一衬层110的表面形成所述硬掩膜层230，所述硬掩膜层230覆盖所述鳍部位置，以所述硬掩膜层230为掩膜刻蚀所述第一衬层110、所述第二衬层120以及部分厚度的所述衬底100，在所述衬底100上形成所述鳍部200。
本实施例中，所述硬掩膜层230的材料采用氮化硅；其他实施例中，所述硬掩膜层230的材料还可为碳氧化硅、碳化硅、氧化硅等中的一种或者多种。
参考图12，在所述衬底100上形成所述隔离结构500，所述隔离结构500覆盖所述鳍部200的部分侧壁。
本实施例中，在所述衬底100上形成所述隔离结构500；其他实施例中，还可不在所述衬底100上形成所述隔离结构500。
本实施例中，由于所述隔离结构500的存在能够很好的所述衬底100的表面不受到损伤，从而便于提高后续形成的半导体器件的质量。
本实施例中，所述隔离结构500采用浅沟槽隔离结构(STI)，采用传统的方式形成。
参考图13，在所述第二区220的所述鳍部200之间填充满所述绝缘层300。
本实施例中，所述绝缘层300的材料为碳化硅。
本实施例中，先采用原子层沉积的方式在相邻的所述鳍部200之间形成所述绝缘层300的材料，回刻蚀去除所述第一区210的相邻所述鳍部200之间的所述绝缘层300的材料，在所述第二区220的所述鳍部200之间填充满所述绝缘层300。
其他实施例中，还可采用化学气相沉积工艺或者物理气相沉积工艺在所述鳍部200之间形成所述绝缘层300的材料。
参考图14，去除所述硬掩膜层230。
本实施例中，在所述鳍部200的顶部形成有所述硬掩膜层230；其他实施例中，还可在所述鳍部200的顶部不形成所述硬掩膜层230。
本实施例中，形成所述硬掩膜层230的目的是保护好形成的所述鳍部200的顶部表面质量，使得所述鳍部200的顶部表面不受到后续工艺的损伤。
本实施例中，采用干法刻蚀工艺去除所述硬掩膜层230；其他实施例中，还可采用灰化的工艺去除所述硬掩膜层230。
参考图15，在所述衬底100上形成所述伪栅结构400，所述伪栅结构400横跨所述鳍部200。
本实施例中，形成所述伪栅结构400的过程与所述第一实施例中相同。
利用上述方法形成的一种半导体器件，包括：衬底100；若干鳍部200，包括第一区210和第二区220，分立排布于所述衬底100上，且各所述鳍部由部分厚度的所述衬底100、所述第一衬层110和所述第二衬层120组成；其中，所述第一衬层110，位于所述衬底100以及所述第二衬层120上；所述第二衬层120，位于所述第一衬层110上；隔离结构500，位于所述衬底100上覆盖所述鳍部200的部分侧壁；绝缘层300，填充满所述第二区220相邻的所述鳍部200之间；伪栅结构400，位于所述衬底100上，且横跨所述鳍部200。
参考图16，去除所述伪栅结构400以及所述第一衬层110，在相邻的所述第二衬层120以及所述衬底100与所述第二衬层120之间形成沟道130。
本实施例中，采用湿法刻蚀工艺去除所述伪栅结构以及所述第一衬层110，所述湿法刻蚀工艺中采用四甲基氢氧化铵(TMAH)为刻蚀溶液，利用四甲基氢氧化铵、硅酸以及过硫酸铵的混合容易刻蚀2.5h～3h可以获得光滑的刻蚀表面。
参考图17，在所述衬底100上形成所述栅极结构600，所述栅极结构600横跨所述第二衬层120且填充满所述沟道130。
所述栅极结构600包括包围所述第二衬层120的栅介质层和覆盖所述栅介质层的栅电极层。
本实施例中，形成的包围所述第二衬层120的所述栅极结构600具有较大的栅极有效宽度，并且形成的半导体器件具有很好地限制短沟道效应的能力。
本实施例中，所述栅介质层材料为高k介质材料(介电系数大于3.9)；所述高k介质材料包括氧化铪、氧化锆、氧化铪硅、氧化镧、氧化锆硅、氧化钛、氧化钽、氧化钡锶钛、氧化钡钛、氧化锶钛或氧化铝。
所述栅电极层的材料为金属，所述金属材料包括铜、钨、镍、铬、钛、钽和铝中的一种或多种组合。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (10)

1.一种半导体器件的形成方法，其特征在于，包括：
提供衬底，在所述衬底上交替形成第一衬层和第二衬层；
刻蚀所述第一衬层、所述第二衬层以及部分厚度的所述衬底，在所述衬底上形成若干分立排布的鳍部；
所述鳍部包括第一区和第二区；
在所述第二区相邻所述鳍部之间填充满绝缘层；
在所述衬底上形成伪栅结构，所述伪栅结构横跨所述鳍部，所述伪栅结构的顶部与所述绝缘层的顶部齐平。
2.如权利要求1所述半导体器件的形成方法，其特征在于，所述绝缘层的材料包括氧化硅、氮化硅、氮氧化硅、碳氮化硅中的一种或多种。
3.如权利要求1所述半导体器件的形成方法，其特征在于，形成所述伪栅结构之后，还包括：
去除所述伪栅结构以及所述第一衬层，在相邻的所述第二衬层以及所述衬底与所述第二衬层之间形成沟道；
在所述衬底上形成栅极结构，所述栅极结构横跨所述第二衬层且填充满所述沟道。
4.如权利要求1所述半导体器件的形成方法，其特征在于，所述第一衬层的材料与所述第二衬层的材料不同，所述第一衬层的材料包括硅、锗、硅锗、砷化镓。
5.如权利要求4所述半导体器件的形成方法，其特征在于，所述第二衬层的材料包括硅、锗、硅锗、砷化镓。
6.如权利要求1所述半导体器件的形成方法，其特征在于，还包括，在所述衬底上形成隔离结构，所述隔离结构覆盖所述鳍部的部分侧壁。
7.如权利要求1所述半导体器件的形成方法，其特征在于，还包括硬掩膜层，所述硬掩膜层位于所述鳍部的顶部。
8.如权利要求7所述半导体器件的形成方法，其特征在于，在所述衬底上形成所述伪栅结构之前，还包括，去除所述硬掩膜层。
9.如权利要求1所述半导体器件的形成方法，其特征在于，采用外延层生长方式在所述衬底上交替形成所述第一衬层和所述第二衬层。
10.一种采用权利要求1至9任一项方法所形成的半导体器件，其特征在于，包括：
衬底；
若干鳍部，包括第一区和第二区，分立排布于所述衬底上，且各所述鳍部由部分厚度的衬底、第一衬层以及第二衬层组成；
其中：第一衬层，位于所述衬底以及所述第二衬层上；
第二衬层，位于所述第一衬层上；
绝缘层，填充满第二区相邻所述鳍部之间；
伪栅结构，位于所述衬底上，横跨所述鳍部且顶部与绝缘层的顶部齐平。
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