CN112071858B - Three-dimensional memory and preparation method thereof - Google Patents
Three-dimensional memory and preparation method thereof Download PDFInfo
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- 238000005530 etching Methods 0.000 claims description 9
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The application provides a three-dimensional memory and a preparation method thereof. Comprising the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a laminated structure formed on the surface of the substrate; forming a channel hole penetrating the laminated structure in the laminated structure; forming a memory layer, a seed layer and an original channel layer in the channel hole in sequence; and annealing to form the original channel layer into a channel layer. The technical scheme of the application solves the problems that in the prior art, in order to ensure that the defects of the channel layer finally formed in the channel hole are fewer, a long-time annealing treatment is needed, the process and material cost are easy to increase, and the method is not suitable for large-scale mass production.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory and a preparation method thereof.
Background
As the number of layers of the three-dimensional memory is higher, the requirements for the channel layer in the channel hole are also higher. In the conventional manufacturing process of the channel layer, in order to ensure that the defect of the finally formed channel layer is less, a long-time annealing treatment is required, so that the process and material cost are increased easily, and the method is not suitable for large-scale mass production.
Disclosure of Invention
In view of this, the application provides a three-dimensional memory and a preparation method thereof, which are used for solving the problems that in the prior art, in order to ensure that the defects of a channel layer finally formed in a channel hole are fewer, a long-time annealing treatment is needed, the cost of a process and materials is easy to increase, and the three-dimensional memory is not suitable for large-scale mass production.
In a first aspect, the present application provides a method for preparing a three-dimensional memory, including:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a laminated structure formed on the surface of the substrate;
forming a channel hole penetrating the laminated structure in the laminated structure; and
Forming a memory layer, a seed layer and an original channel layer in the channel hole in sequence;
Annealing is performed to form the original channel layer into a channel layer.
In one possible embodiment, the seed layer is a silicon germanium layer.
In a possible embodiment, the thickness of the seed layer is in the range of 1nm-2 nm.
In a possible implementation manner, the sequentially forming the memory layer, the seed layer and the original channel layer in the channel hole includes:
forming an epitaxial layer connected with the substrate at the bottom of the channel hole;
Forming a memory layer and a channel sacrificial layer on the side wall of the channel hole and the surface of the epitaxial layer, which is away from the substrate, in sequence;
Sequentially etching the channel sacrificial layer and the memory layer which are positioned at the bottom of the channel hole to expose the epitaxial layer;
Removing the channel sacrificial layer; and
And forming a seed layer and an original channel layer on the surface of the memory layer, which is away from the channel hole, and the exposed surface of the epitaxial layer in sequence.
In one possible embodiment, the channel sacrificial layer is a first amorphous silicon layer.
In one possible embodiment, the channel sacrificial layer is removed using hydrogen chloride gas.
In a possible implementation manner, the original channel layer is a second amorphous silicon layer.
In a possible embodiment, the annealing time is in the range of 5h to 6 h.
In a possible implementation manner, the memory layer includes a blocking layer, a tunneling layer and a charge trapping layer which are sequentially stacked, and the blocking layer covers the side wall of the channel hole.
In a second aspect, the present application also provides a three-dimensional memory comprising:
a semiconductor structure comprising a substrate and a stacked structure formed on a surface of the substrate;
The channel hole penetrates through the laminated structure and exposes the substrate;
the memory layer, the seed layer and the channel layer are sequentially formed in the channel hole, and the channel layer is formed by annealing the original channel layer formed on the surface of the seed layer, which is away from the memory layer.
In one possible embodiment, the seed layer is a silicon germanium layer.
In a possible embodiment, the thickness of the seed layer is in the range of 1nm-2 nm.
Compared with the traditional method that an original channel layer is directly formed on the surface of a memory layer, the technical scheme of the application comprises the steps of forming a seed layer on the surface of the memory layer, forming the original channel layer on the surface of the seed layer, and annealing the original channel layer to form the channel layer. The seed layer is arranged between the memory layer and the original channel layer, so that the seed layer is fully contacted with the original channel layer, the time of annealing treatment can be greatly shortened in the process of forming the channel layer by annealing treatment of the original channel layer, the process and material cost can be greatly reduced, the mass production performance of the three-dimensional memory is facilitated, and meanwhile, the defect of the channel layer formed by annealing treatment is less due to the full contact with the seed layer, and the yield and the device performance of the three-dimensional memory are improved.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained by those skilled in the art without the inventive effort.
FIG. 1 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present application;
Fig. 2 is a schematic structural diagram of a semiconductor structure of a three-dimensional memory according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a channel hole of a three-dimensional memory according to an embodiment of the present application;
FIG. 4 is a schematic flow chart of a method for preparing a memory layer, a seed layer and an original channel layer of a three-dimensional memory according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a three-dimensional memory according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an epitaxial layer of a three-dimensional memory according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a structure of a memory layer and a channel sacrificial layer of a three-dimensional memory according to an embodiment of the present application;
FIG. 8 is a schematic diagram of another structure of a memory layer and a channel sacrificial layer of the three-dimensional memory according to the embodiment of the present application;
FIG. 9 is a schematic diagram of a memory layer of a three-dimensional memory according to an embodiment of the present application;
FIG. 10 is a schematic diagram of a structure of a memory layer and a seed layer of a three-dimensional memory according to an embodiment of the present application;
fig. 11 is a schematic structural diagram of a memory layer and an original channel layer of a three-dimensional memory according to an embodiment of the present application.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While the exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be practiced otherwise than as described herein and is therefore not limited to the embodiments described below.
As the number of layers of the three-dimensional memory is higher, the requirements for the channel layer in the channel hole are also higher. In the conventional manufacturing process of the channel layer, in order to ensure that the defect of the finally formed channel layer is less, a long-time annealing treatment is required, so that the process and material cost are increased easily, and the method is not suitable for large-scale mass production.
In view of this, the present application provides a method for manufacturing a three-dimensional memory, and fig. 1 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present application. As shown in fig. 1, the method for manufacturing the three-dimensional memory may include at least S100, S200, S300, and S400, which are described in detail below.
S100: a semiconductor structure is provided, wherein the semiconductor structure includes a substrate and a stack structure formed on a surface of the substrate.
S200: and forming a channel hole penetrating through the laminated structure in the laminated structure.
S300: and forming a memory layer, a seed layer and an original channel layer in the channel hole in sequence.
S400: annealing is performed to form the original channel layer into a channel layer.
The respective steps will be further described below.
The following describes the step S100 described above with reference to fig. 2, where fig. 2 is a schematic structural diagram of a semiconductor structure of the three-dimensional memory according to an embodiment of the present application.
S100: a semiconductor structure 10 is provided, wherein the semiconductor structure 10 comprises a substrate 11 and a stacked structure 12 formed at a surface of the substrate 11.
First, a substrate 11 is provided.
In an embodiment of the present application, the substrate 11 is a semiconductor substrate. For example, the substrate 11 may be a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon-on-insulator (Silicon On Insulator, SOI) substrate, or a germanium-on-insulator (Germanium On Insulator, GOI) substrate, or the like. The substrate 11 may also be a P-doped substrate or an N-doped substrate. Suitable materials may be selected as the substrate 11 according to actual demands, and the present application is not particularly limited thereto. Of course, in other embodiments, the material of the substrate 11 may also be a semiconductor or a compound including other elements. For example, the substrate 11 may be a gallium arsenide (GaAs) substrate, an Indium phosphide (InP) substrate, a silicon carbide (SiC) substrate, or the like.
Next, a stacked structure 12 is formed on the surface of the substrate 11.
The laminated structure 12 includes dielectric layers 13 and sacrificial layers 14 alternately laminated successively in a direction perpendicular to the substrate 11, and the laminated structure 12 having a multi-layer structure is formed by alternately laminated successively of the dielectric layers 13 and the sacrificial layers 14. Specifically, the material of the dielectric layer 13 may be an insulating dielectric material such as silicon oxide, aluminum oxide, hafnium oxide, or tantalum oxide. The material of the sacrificial layer 14 may be silicon nitride. In the embodiment of the present application, the material of the dielectric layer 13 is silicon oxide, and the material of the sacrificial layer 14 is silicon nitride.
Also, since the dielectric layer 13 and the sacrificial layer 14 have different etching selectivity, the sacrificial layer 14 as a gate sacrificial layer will be removed in a subsequent process, and the space of the sacrificial layer 14 will be filled with a highly conductive material to form a gate layer. Specifically, the highly conductive material may be metallic tungsten, cobalt, copper, nickel, etc., or may be polysilicon, doped silicon, or any combination thereof. Of course, in other embodiments, the sacrificial layer 14 may be a gate layer.
In one possible implementation, the stacked structure 12 may be formed by stacking two times, where the stacked structure 12 formed by stacking two times may have a higher layer number and a lower aspect ratio, and may be capable of effectively adapting to the application requirement of the three-dimensional memory 100 that the stacked layer number is higher and higher.
Specifically, the stacked structure 12 may include a first stacked structure 121 and a second stacked structure 122, where the first stacked structure 121 may be formed on a surface of the substrate 11, and then the second stacked structure 122 may be formed on a surface of the first stacked structure 121 facing away from the substrate 11, so that the first stacked structure 121 and the second stacked structure 122 together form the stacked structure 12 of the three-dimensional memory 100. The number of stacked layers of the first stacked structure 121 and the second stacked structure 122 may be selected according to practical design requirements, for example, may be 64 layers, 128 layers, etc., which is not strictly limited in the present application.
The above step S200 will be described with reference to fig. 3, where fig. 3 is a schematic structural diagram of the channel hole 20 of the three-dimensional memory 100 according to an embodiment of the present application.
S200: a channel hole 20 is formed in the stacked structure 12 through the stacked structure 12.
It is understood that the channel hole 20 may be etched using a dry etching or a wet etching process. The substrate 11 may be exposed when the channel hole 20 is etched.
In one possible implementation manner, the channel hole 20 may be formed by two etching, where the channel hole 20 formed by two etching may greatly reduce the difficulty of the etching process caused by the application requirement that the number of stacked layers of the three-dimensional memory 100 is higher and higher, and the channel hole 20 formed by two etching has a lower aspect ratio, so that the risk of tilting the channel hole 20 can be effectively improved.
Specifically, the channel hole 20 may include a first channel hole 21 and a second channel hole 22. The first stack structure 121 may be etched after the first stack structure 121 is stacked to form the first channel hole 21, and the second stack structure 122 may be etched at a position aligned with the first channel hole 21 after the first stack structure 121 is stacked to form the second stack structure 122, so as to form the second channel hole 22 penetrating the second stack structure 122 and communicating with the first channel hole 21, thereby communicating the first channel hole 21 and the second channel hole 22 to form the channel hole 20.
The following description of step S300 will be made with reference to fig. 4 to 10, where fig. 4 is a schematic flow chart of a method for preparing the memory layer 30, the seed layer 40 and the original channel layer 52 of the three-dimensional memory according to the embodiment of the present application, fig. 5 is a schematic structural diagram of the three-dimensional memory 100 according to the embodiment of the present application, fig. 6 is a schematic structural diagram of the epitaxial layer 60 of the three-dimensional memory 100 according to the embodiment of the present application, fig. 7 is a schematic structural diagram of the memory layer 30 and the channel sacrificial layer 51 of the three-dimensional memory 100 according to the embodiment of the present application, fig. 8 is a schematic structural diagram of the memory layer 30 and the channel sacrificial layer 51 of the three-dimensional memory 100 according to the embodiment of the present application, fig. 9 is a schematic structural diagram of the memory layer 30 and the seed layer 40 of the three-dimensional memory 100 according to the embodiment of the present application.
S300: a memory layer 30, a seed layer 40, and an original channel layer 52 are sequentially formed within the channel hole 20.
It will be appreciated that the memory layer 30 includes a blocking layer 31, a charge trapping layer 32 and a tunneling layer 33, and since the material of the blocking layer 31 may be Oxide such as silicon Oxide, the material of the charge trapping layer 32 may be Nitride such as silicon Nitride, silicon oxynitride, or a single layer or a multi-layer composite film thereof, and the material of the tunneling layer 33 may be Oxide such as silicon Oxide, silicon oxynitride, or a single layer or a multi-layer composite film thereof, the memory layer 30 forms an ONO stack structure accordingly. Wherein the blocking layer 31 is formed between the sidewall of the channel hole 20 and the charge trapping layer 32, and is capable of blocking outflow of charges (electrons or holes). The charge trapping layer 32 is formed between the blocking layer 31 and the tunneling layer 33, so that charges from the channel layer 50 which will be formed later can be tunneled to the charge trapping layer 32 through the tunneling layer 33 to store the charges for a storage operation. The storage or removal of charge in the charge trapping layer 32 may affect the switching state and/or conductance of the channel structure within the channel hole 20. A tunneling layer 33 is formed over the charge trapping layer 32, capable of tunneling charges from the channel layer 50.
As shown in fig. 4, the preparation method of the memory layer 30, the seed layer 40 and the original channel layer 52 may at least include steps S310, S320, S330, S340 and S350, which are described in detail below:
S310: and forming an epitaxial layer connected with the substrate at the bottom of the channel hole.
S320: and forming a memory layer and a channel sacrificial layer on the side wall of the channel hole and the surface of the epitaxial layer, which is away from the substrate, in sequence.
S330: the channel sacrificial layer and the memory layer at the bottom of the channel hole are sequentially etched to expose the epitaxial layer.
S340: and removing the channel sacrificial layer.
S350: and sequentially forming a seed layer and an original channel layer on the surface of the memory layer, which is away from the channel hole, and the surface of the exposed epitaxial layer.
The respective steps will be further described below.
Step S310 described above will be described below in conjunction with fig. 6.
S310: an epitaxial layer 60 connected to the substrate 11 is formed at the bottom of the channel hole 20.
Specifically, the epitaxial layer 60 may be a silicon layer formed on the substrate 11 by selective epitaxial growth (SELECTIVE EPITAXIAL GROWTH, SEG) that is located at the bottom of the channel hole 20 and covers the substrate 11, and the epitaxial layer 60 can form a bottom select pipe of the three-dimensional memory 100 adjacent to the bottom select gate when the subsequent sacrificial layer 14 is removed to form a gate layer. Wherein the epitaxial layer 60 may act as a channel for the bottom select tube.
Step S320 described above will be described below in conjunction with fig. 7.
S320: a memory layer 30 and a channel sacrificial layer 51 are formed in this order on the side walls of the channel holes 20 and the surface of the epitaxial layer 60 facing away from the substrate 11.
Since the epitaxial layer 60 is formed at the bottom of the channel hole 20 in the foregoing step, at this time, the sidewall of the channel hole 20 and the surface of the epitaxial layer 60 are exposed. Thereby, the blocking layer 31, the charge trapping layer 32, and the tunneling layer 33 are sequentially formed on the sidewall of the channel hole 20 and the surface of the epitaxial layer 60. The blocking layer 31, the charge trapping layer 32 and the tunneling layer 33 together constitute the memory layer 30, and the memory layer 30 is an ONO structure in a stacked arrangement.
And after the memory layer 30 is formed, a channel sacrificial layer 51 is formed on the surface of the memory layer 30 facing away from the sidewall of the channel hole 20.
In a possible embodiment, the channel sacrificial layer 51 is a first amorphous silicon (amorphous silicon, a-Si) layer, i.e., the channel sacrificial layer 51 is made of an amorphous silicon material.
It will be appreciated that the channel sacrificial layer 51 made of amorphous silicon material is formed in the channel hole 20, and the channel sacrificial layer 51 has no grain structure, so that the channel sacrificial layer can be tightly bonded with the outer surface of the memory layer 30 (the surface of the tunneling layer 33 facing away from the charge trapping layer 32) when deposited in the channel hole 20, and defects such as voids are not easily formed. Because the channel layer 50 formed in the subsequent process needs to be communicated with the epitaxial layer 60, the channel sacrificial layer 51 is formed first to prepare the epitaxial layer 60 exposed from the bottom of the channel hole 20 in the subsequent etching process, which is beneficial to improving the performance and yield of the three-dimensional memory 100.
Step S330 described above will be described below in conjunction with fig. 8.
S330: the channel sacrificial layer 51 and the memory layer 30 at the bottom of the channel hole 20 are sequentially etched to expose the epitaxial layer 60.
Since the memory layer 30 and the channel sacrificial layer 51 are sequentially formed on the surface of the epitaxial layer 60, when the bottom layer structure is required to be opened to expose the epitaxial layer 60, the channel sacrificial layer 51 and the memory layer 30 need to be sequentially etched to form an opening exposing the epitaxial layer 60, thereby facilitating the subsequent process. In one possible embodiment, the etching process is a punch etch.
Step S340 described above will be described below in conjunction with fig. 8 and 9.
S340: the channel sacrificial layer 51 is removed.
Since the bottom of the channel hole 20 is opened in the foregoing step, the epitaxial layer 60 at the bottom of the channel hole 20 is exposed. Thereby, the channel sacrificial layer 51 can be removed so that a channel layer capable of conducting with the substrate 11 is subsequently formed.
In one possible embodiment, the channel sacrificial layer 51 may be removed by a dry etching process. For example, hydrogen Chloride (HCL) gas may be used to remove the channel sacrificial layer 51. Based on this, the channel sacrificial layer 51 of the surface of the memory layer 30 facing away from the sidewall of the channel hole 20 is removed.
The above step S350 will be described below with reference to fig. 5, 10 and 11, wherein fig. 11 is a schematic structural diagram of the memory layer 30 and the original channel layer 52 of the three-dimensional memory 100 according to the embodiment of the present application.
S350: the seed layer 40 and the original channel layer 52 are formed in sequence on the surface of the memory layer 30 facing away from the channel hole 20 and the surface of the exposed epitaxial layer 60.
First, a seed layer 40 is formed on the surface of the memory layer 30 facing away from the channel hole 20 and the surface of the exposed epitaxial layer 60.
In this embodiment, the seed layer 40 can cover the memory layer 30 and the exposed surface of the epitaxial layer 60, and the seed layer 40 is a silicon germanium layer, wherein the silicon germanium layer may include silicon germanium (SiGe), or may include germanium (Ge) and silicon germanium (SiGe).
It will be appreciated that the presence of metallic germanium in the sige layer is effective to promote crystallization of silicon on the one hand and to reduce the polysilicon (polysilicon) resistance of the channel layer 50 during subsequent formation of the channel layer 50 on the other hand. Meanwhile, the device performance of the three-dimensional memory 100 can be effectively improved while the Wafer Per Hour (WPH) Per Hour of the Wafer is improved.
In one possible embodiment, the thickness of seed layer 40 is in the range of 1nm-2nm (inclusive of the endpoints 1nm and 2 nm).
Next, an original channel layer 52 is formed on the surface of the seed layer 40 facing away from the memory layer 30.
In one possible implementation, the original channel layer 52 is a second amorphous silicon layer, i.e., the original channel layer 52 is made of an amorphous silicon material.
It will be appreciated that since the seed layer 40 is formed in the foregoing steps, the seed layer 40 is uniform in thickness and can form a better interface state. Therefore, compared with the conventional method that the original channel layer 52 is directly formed on the surface of the memory layer 30 and annealed to form the channel layer 50, the seed layer 40 is arranged between the memory layer 30 and the original channel layer 52, so that the interface state of the original channel layer 52 is good, the quality of the original channel layer 52 can be effectively improved, the quality of the channel layer 50 formed by carrying out subsequent process treatment on the original channel layer 52 is improved, and the yield and the device performance of the three-dimensional memory 100 are improved.
The above-described step S400 will be described below in conjunction with fig. 5 and 11.
S400: annealing is performed to form the original channel layer 52 into the channel layer 50.
It is understood that amorphous silicon can be converted to polysilicon by an annealing process. Thus, the original channel layer 52 made of an amorphous silicon material is annealed, and can be converted into the channel layer 50 made of a polysilicon material.
After forming the seed layer 40 on the sidewall of the memory layer 30 facing away from the channel hole 20, forming an original channel layer 52 on the surface of the seed layer 40, and annealing the original channel layer 52 to form the channel layer 50 on the original channel layer 52. The formed channel layer 50 can be brought into full contact with the seed layer 40 so that the seed layer 40 plays a sufficient role in inducing crystallization. The metal in the seed layer 40 has a cubic lattice structure similar to that of polysilicon, so that the metal can better guide the crystallization of the amorphous silicon into the polysilicon, and simultaneously, the phase transformation energy of the polysilicon can be reduced, the nucleation and the growth can be promoted, and the crystallization capability is enhanced, thereby reducing the crystallization temperature and the crystallization speed, and the amorphous silicon can be rapidly crystallized and converted into the polysilicon.
Based on this, compared to the annealing process conditions for a longer time in the conventional process, the time for the annealing process of the original channel layer 52 can be greatly reduced on the basis of ensuring the crystallinity of the channel layer 50 in the embodiment of the present application, so that the defect of the formed channel layer 50 can be effectively reduced, and the three-dimensional memory 100 has excellent device performance.
In one possible embodiment, the time of the annealing treatment is in the range of 5h (hours) to 6h (inclusive of 5h and 6 h). Therefore, compared with the traditional annealing treatment time which needs 12 hours, the annealing time can be reduced by half in the embodiment of the application, which is beneficial to improving the mass production performance of the three-dimensional memory 100.
In one possible embodiment, the annealing temperature is preferably 650 ℃, the process conditions are such that the probability of amorphous nucleation is greatest and the crystal nuclei are at the highest speed.
Based on the above description, the seed layer 40 is formed on the surface of the memory layer 30, and then the original channel layer 52 is formed on the surface of the seed layer 40, and the original channel layer 52 is annealed to form the channel layer 50, as opposed to the conventional method in which the channel layer is directly formed on the surface of the memory layer. That is, the seed layer 40 is disposed between the memory layer 30 and the original channel layer 52, so that the seed layer 40 is fully contacted with the original channel layer 52, the annealing time can be greatly shortened in the process of forming the channel layer 50 by annealing, the process and material cost can be greatly reduced, the mass production performance of the three-dimensional memory 100 is facilitated, and meanwhile, the channel layer 50 formed by annealing has fewer defects due to the full contact with the seed layer 40, and the yield and the device performance of the three-dimensional memory 100 are improved.
The present application further provides a three-dimensional memory 100, and it can be understood that the three-dimensional memory 100 provided by the present application can be prepared by the method for preparing the three-dimensional memory 100, and the detailed structure and features thereof have been described above, and most of the details are not repeated.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a three-dimensional memory 100 according to an embodiment of the application.
The three-dimensional memory 100 provided by the application comprises a semiconductor structure 10, wherein the semiconductor structure 10 comprises a substrate 11 and a laminated structure 12 formed on the surface of the substrate 11. And a channel hole 20 formed in the laminated structure 12, the channel hole 20 penetrating the laminated structure 12 and exposing the substrate 11. And a memory layer 30, a seed layer 40 and a channel layer 50 formed in sequence in the channel hole 20, the channel layer 50 being formed by annealing an original channel layer 52 formed on a surface of the seed layer 40 facing away from the memory layer 30.
In one possible embodiment, the seed layer is a silicon germanium layer. Illustratively, the seed layer has a thickness in the range of 1nm-2 nm.
The foregoing is illustrative of the embodiments of the invention, and it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are to be considered as within the scope of the invention.
Claims (10)
1. A method for manufacturing a three-dimensional memory, comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a laminated structure formed on the surface of the substrate;
forming a channel hole penetrating the laminated structure in the laminated structure;
forming an epitaxial layer connected with the substrate at the bottom of the channel hole;
Forming a memory layer and a channel sacrificial layer on the side wall of the channel hole and the surface of the epitaxial layer, which is away from the substrate, in sequence;
Sequentially etching the channel sacrificial layer and the memory layer which are positioned at the bottom of the channel hole to expose the epitaxial layer;
Removing the channel sacrificial layer;
sequentially forming a seed layer and an original channel layer on the surface of the memory layer, which is away from the channel hole, and the exposed surface of the epitaxial layer, wherein the seed layer is a silicon germanium layer; and
Annealing is performed to form the original channel layer into a channel layer.
2. The method of manufacturing a three-dimensional memory according to claim 1, wherein the thickness of the seed layer is in the range of 1nm to2 nm.
3. The method of claim 1, wherein the channel sacrificial layer is a first amorphous silicon layer.
4. The method for manufacturing a three-dimensional memory according to claim 1, wherein the channel sacrificial layer is removed using hydrogen chloride gas.
5. The method of manufacturing a three-dimensional memory device according to claim 1, wherein the original channel layer is a second amorphous silicon layer.
6. The method of manufacturing a three-dimensional memory according to claim 5, wherein the time of the annealing is in the range of 5h to 6h.
7. The method for manufacturing a three-dimensional memory according to claim 1, wherein the memory layer includes a blocking layer, a charge trapping layer, and a tunneling layer, which are sequentially stacked, the blocking layer covering sidewalls of the channel hole.
8. A three-dimensional memory, characterized by comprising being prepared by a method for preparing a three-dimensional memory according to any one of claims 1-7.
9. The three-dimensional memory of claim 8, wherein the seed layer is a silicon germanium layer.
10. The three-dimensional memory of claim 8, wherein the seed layer has a thickness in the range of 1nm-2 nm.
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