CN112071857B - Three-dimensional memory and preparation method thereof - Google Patents

Three-dimensional memory and preparation method thereof Download PDF

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Publication number
CN112071857B
CN112071857B CN202010811303.7A CN202010811303A CN112071857B CN 112071857 B CN112071857 B CN 112071857B CN 202010811303 A CN202010811303 A CN 202010811303A CN 112071857 B CN112071857 B CN 112071857B
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layer
material layer
semiconductor material
sacrificial
trench
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CN112071857A (en
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吴林春
张坤
周文犀
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Abstract

The invention provides a three-dimensional memory and a preparation method thereof, wherein the three-dimensional memory comprises a back dielectric layer, a semiconductor substrate arranged on the back dielectric layer, a first groove and a second groove formed on the semiconductor substrate, a first semiconductor material layer formed in the first groove, a second semiconductor material layer formed on the common surface of the first semiconductor material layer and the semiconductor substrate, and a grid laminated structure formed on the second semiconductor material layer; the isolation groove filling layer penetrates through the grid laminated structure, the second semiconductor material layer and is filled in the second groove, and the conductive column penetrates through the back dielectric layer and is in contact with the first semiconductor material layer. By using the method, the thickness of the sacrificial material layer at the groove is increased by forming the groove below the gate line gap, so that the process window in the process of etching the gate line gap can be increased, and the process difficulty is reduced; meanwhile, the top polycrystalline silicon layer above the sacrificial material layer is omitted, so that the electrical property of the device is not affected.

Description

Three-dimensional memory and preparation method thereof
Technical Field
The invention belongs to the field of semiconductor design and manufacture, and particularly relates to a three-dimensional memory and a preparation method thereof.
Background
In a dual stack (dual stack) process of a three-dimensional memory (3D NAND), after the Channel hole etching is completed, a functional sidewall of an ONO (silicon oxide-silicon nitride-silicon oxide) structure and a sacrificial polysilicon layer (SAC Poly) are deposited in the Channel hole, and then deep hole etching is performed to open the ONOP (polysilicon layer and functional sidewall) at the bottom of the Channel hole, so as to form a circuit loop of P-well and Channel polysilicon (Channel Poly, i.e., channel layer). Due to the influence of stress and other factors, the upper channel hole (Upper Channel Hole, UCH) and the lower channel hole (Lower Channel Hole, LCH) are difficult to align, offset (shift) exists in an Overlay Window (Overlay Window) of the upper channel hole and the lower channel hole, and when deep hole etching is performed, the functional side wall at the joint of the upper stacked structure and the lower stacked structure is damaged, so that the electrical property of a final memory cell is influenced, the Wafer test (Wafer Sort) yield is low or the reliability is invalid, and the deep hole etching challenges caused by the increase of the layer number of the 3D NAND structure can be avoided; the back extraction (back Pick Up) can avoid the short circuit leakage (short leakage) of Word Lines (WL) and array common source lines (Array Common Source, ACS) caused by filling conductive materials in gate Line gaps, and can remove the extraction area of the array common source lines on the front surface of the three-dimensional memory, increase the density of a storage area and reduce the cost.
The deep hole-free etching combined with the back extraction architecture can greatly reduce the process challenge of a 3D Nand product with a high layer number, three layers of polysilicon are arranged at the bottom of a grid electrode laminated structure in the structure, namely a top polysilicon layer, a middle polysilicon sacrificial layer and a bottom polysilicon layer in sequence from top to bottom, wherein the middle polysilicon sacrificial layer is removed through a grid line gap to form a middle polysilicon gap, and a polysilicon material is deposited with the polysilicon gap to form middle polysilicon. This structure has mainly the following drawbacks: (1) The Top Poly thickness affects the conduction of the Poly channel layer (CH Poly) in the channel structure; (2) The deep trench (Gouging) at the interface of the Gate Line Slit (GLS) and the Dummy channel hole (Dummy CH) may cause the Bottom polysilicon layer (Bottom Poly) to be removed when the middle sacrificial polysilicon layer (SAC Poly) is removed, affecting the device performance.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an objective of the present invention is to provide a three-dimensional memory and a method for manufacturing the same, which are used for solving the technical problems that a top polysilicon layer of the existing three-dimensional memory without deep hole etching combined with back-out architecture affects the conduction of a polysilicon channel layer in a channel structure of the region, and a bottom polysilicon layer may be removed during the manufacturing process of the three-dimensional memory.
To achieve the above and other related objects, the present invention provides a three-dimensional memory comprising:
a back dielectric layer;
the semiconductor substrate is arranged on the back dielectric layer;
the first groove is formed on the semiconductor substrate, and the surface of the back dielectric layer is exposed by the first groove;
the second groove is formed on the semiconductor substrate, and the second groove exposes the surface of the back dielectric layer;
a first semiconductor material layer formed in the first trench;
a second semiconductor material layer formed on a common surface of the first semiconductor material layer and the semiconductor substrate;
a gate stack structure formed on the second semiconductor material layer;
the separation groove filling layer sequentially penetrates through the grid laminated structure, the second semiconductor material layer and is filled in the second groove; and
and the conductive column penetrates through the back dielectric layer and is in contact with the first semiconductor material layer.
In an alternative embodiment, the three-dimensional memory further comprises a memory string extending sequentially through the gate stack, the second layer of semiconductor material and into the first layer of semiconductor material.
In an alternative embodiment, the memory string includes functional sidewalls and a channel layer disposed sequentially in a radially inward direction.
In an alternative embodiment, the second semiconductor material layer is located at the periphery of the memory string and is in contact with the channel layer.
In an alternative embodiment, the bottom of the memory string is higher than the bottom surface of the trench.
In an alternative embodiment, the gate stack structure includes alternately stacked interlayer dielectric layers and gate layers.
In an alternative embodiment, the material of the gate layer comprises tungsten.
In an alternative embodiment, the material of the first semiconductor material layer includes polysilicon; the material of the second semiconductor material layer comprises polysilicon.
In an alternative embodiment, the width of the portion of the separation trench filling layer located in the gate stack structure is smaller than the width of the second trench.
In an alternative embodiment, the material of the spacer fill layer comprises silicon nitride, silicon oxide, or silicon oxynitride.
In an alternative embodiment, a thinning stop layer is further formed between the first semiconductor material layer and the inner wall of the first trench.
In an alternative embodiment, the material of the thinning stop layer comprises silicon nitride.
In an alternative embodiment, the thickness of the first semiconductor material layer is between 50-200 nm.
To achieve the above and other related objects, the present invention also provides a method for manufacturing a three-dimensional memory, the method comprising:
providing a semiconductor substrate, wherein a first groove and a second groove are formed in the semiconductor substrate, and a thinning stop layer and a first semiconductor material layer are sequentially filled in the first groove;
forming a sacrificial material layer on the surface of the first semiconductor material layer and in the second groove;
forming a stacked structure on the sacrificial material layer, wherein the stacked structure comprises interlayer dielectric layers and gate sacrificial layers which are alternately stacked;
forming a grid line gap in the stacked structure, wherein the grid line gap penetrates through the stacked structure and exposes the surface of the sacrificial material layer, and the grid line gap is positioned right above the second groove;
removing the sacrificial material layer based on the gate line gap to form a sacrificial gap and re-opening the second trench, and forming a second semiconductor material layer in the sacrificial gap;
replacing the gate sacrificial layer with a conductive material to form a gate layer based on the gate line slit;
Forming a separation groove filling layer in the gate line gap and the second groove;
thinning the semiconductor substrate, and forming a back dielectric layer on the exposed surface after thinning;
and forming a conductive column in the back dielectric layer, wherein the conductive column sequentially penetrates through the back dielectric layer and the rest of the thinning stop layer and then contacts with the first semiconductor material layer.
In an alternative embodiment, the method further includes the step of forming a memory string in the stacked structure, wherein the memory string sequentially penetrates through the gate stack structure, the second semiconductor material layer and extends into the first semiconductor material layer.
In an alternative embodiment, the memory string includes functional sidewalls and a channel layer disposed sequentially in a radially inward direction.
In an alternative embodiment, the second semiconductor material layer is located at the periphery of the memory string and is in contact with the channel layer.
In an alternative embodiment, the step of forming a sacrificial material layer on the surface of the first semiconductor material layer and in the second trench includes:
forming a dielectric protection layer on the surface of the first semiconductor material layer and the inner wall of the second groove;
Forming the sacrificial material layer on the dielectric protection layer;
wherein the dielectric protection layer is removed when the sacrificial material layer is subsequently removed based on the gate line slit to form a sacrificial gap and the second trench is reopened to remove the sacrificial material layer.
In an alternative embodiment, the step of removing the sacrificial material layer based on the gate line slit to form a sacrificial gap and reopening the second trench, and forming a second semiconductor material layer in the sacrificial gap includes:
forming a side wall protection layer on the side wall of the grid line gap;
the sacrificial material layer is removed based on the gate line slit formed with the sidewall protection layer to form a sacrificial gap and reopen the second trench, and the second semiconductor material layer is formed in the sacrificial gap.
In an alternative embodiment, the step of forming a sidewall protection layer on the sidewall of the gate line slit includes sequentially forming a sidewall protection layer composed of nitride layer-oxide layer-nitride layer-alumina on the sidewall of the separation trench.
In an alternative embodiment, the step of cleaning the surface of the sacrificial gap is further included before forming the second layer of semiconductor material in the sacrificial gap.
In an alternative embodiment, the step of replacing the gate sacrificial layer with a conductive material to form a gate layer includes replacing the gate sacrificial layer with tungsten to form the gate layer.
In an alternative embodiment, the material of the first semiconductor material layer includes polysilicon; the material of the second semiconductor material layer comprises polysilicon.
In an alternative embodiment, in the step of forming a gate line slit in the stacked structure, a width of the gate line slit is smaller than a width of the trench.
In an alternative embodiment, the step of forming the spacer filling layer in the gate line gap and the second trench includes filling silicon nitride, silicon oxide or silicon oxynitride in the gate line gap and the second trench to form the spacer filling layer.
In an alternative embodiment, the material of the thinning stop layer comprises silicon nitride.
In an alternative embodiment, the depth of the second trench is greater than the depth of the first trench.
In an alternative embodiment, the thickness of the first semiconductor material layer is between 50-200 nm.
By using the method, the thickness of the sacrificial material layer at the groove is increased by forming the groove below the gate line gap, so that the process window in the process of etching the gate line gap can be increased, and the process difficulty is reduced;
By using the invention, the Process Window (Process Window) of removing the back semiconductor substrate by Chemical Mechanical Planarization (CMP) can be greatly improved by depositing a thinning stop layer (such as silicon nitride) on the semiconductor substrate;
by using the invention, the Top polysilicon layer (Top Poly) between the sacrificial material layer (such as sacrificial polysilicon, SAC Poly) and the stacking structure is omitted, so that the influence of the Top polysilicon layer on the conduction of the polysilicon channel layer in the prior art can be effectively improved;
with the present invention, the thickness of the first semiconductor material layer (e.g., the Bottom polysilicon layer) can be thinned, thereby avoiding the influence on the electrical properties that may be caused by the excessive thickness of the Bottom Poly.
Drawings
Fig. 1 shows a schematic cross-sectional view of a three-dimensional memory device prior to forming a gate line slit, which is an example of the present invention.
Fig. 2 is a schematic cross-sectional view of the three-dimensional memory corresponding to fig. 1 after formation of conductive pillars.
Fig. 3 is a schematic cross-sectional view of the three-dimensional memory corresponding to fig. 1, at the boundary between the gate line slit and the dummy channel hole, with the bottom polysilicon layer being at risk of being removed when the middle sacrificial polysilicon layer is removed.
Fig. 4 is a schematic diagram showing a process flow of manufacturing the three-dimensional memory according to the first embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view showing a semiconductor substrate provided in the preparation of the three-dimensional memory according to the first embodiment of the present invention, and a thinning stop layer and a first semiconductor material layer are sequentially formed on the semiconductor substrate.
Fig. 6 is a schematic cross-sectional view illustrating a process of forming a sacrificial material layer on a surface of the first semiconductor material layer and in the trench in the fabrication of the three-dimensional memory according to the first embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view showing a stacked structure formed on the sacrificial material layer in the fabrication of the three-dimensional memory according to the first embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view illustrating formation of gate line slits in the stacked structure in preparation of the three-dimensional memory according to the first embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view illustrating formation of a sidewall protection layer on sidewalls of the gate line slit in preparation of the three-dimensional memory according to the first embodiment of the present invention.
Fig. 10 is a schematic cross-sectional view showing the removal of the sacrificial material layer based on the gate line slit formed with the sidewall protection layer to form a sacrificial gap and re-opening the trench in the preparation of the three-dimensional memory according to the first embodiment of the present invention.
Fig. 11 is a schematic cross-sectional view showing a barrier layer of a memory string exposed by the sacrificial gap in the fabrication of a three-dimensional memory according to the first embodiment of the present invention.
Fig. 12 is a schematic cross-sectional view showing the removal of the aluminum oxide of the sidewall protection layer in the preparation of the three-dimensional memory according to the first embodiment of the present invention.
Fig. 13 is a schematic cross-sectional view of a memory layer and a tunneling layer of a memory string exposed by the sacrificial gap in the preparation of the three-dimensional memory according to the first embodiment of the present invention.
Fig. 14 is a schematic cross-sectional view showing the formation of a second semiconductor material in the sacrificial gap in the fabrication of the three-dimensional memory according to the first embodiment of the present invention.
Fig. 15 is a schematic cross-sectional view showing the removal of semiconductor material on the sidewalls of the gate line slits in the fabrication of the three-dimensional memory device according to the first embodiment of the present invention to form the second semiconductor material layer in the sacrificial gap.
Fig. 16 is a schematic cross-sectional view showing removal of the oxide layer in the sidewall protection layer in the preparation of the three-dimensional memory according to the first embodiment of the present invention.
Fig. 17 is a schematic cross-sectional view showing the replacement of the gate sacrificial layer with a conductive material to form a gate layer based on the gate line slit in the preparation of the three-dimensional memory according to the first embodiment of the present invention.
Fig. 18 is a schematic cross-sectional view showing a process of forming a spacer filling layer in the gate line slit and the trench in the preparation of the three-dimensional memory according to the first embodiment of the present invention.
Fig. 19 is a schematic cross-sectional view showing a thinning process performed to remove a semiconductor substrate in the preparation of a three-dimensional memory according to the first embodiment of the present invention.
Fig. 20 is a schematic cross-sectional view showing removal of a thinning stop layer in the preparation of a three-dimensional memory according to the first embodiment of the present invention.
Fig. 21 is a schematic cross-sectional view showing a back dielectric layer formed on a surface of the three-dimensional memory after removing the thinning stop layer and forming a conductive post in the back dielectric layer according to the first embodiment of the present invention.
Fig. 22 is a schematic diagram showing a process flow of manufacturing a three-dimensional memory according to a second embodiment of the present invention.
Fig. 23 is a schematic cross-sectional view showing a semiconductor substrate provided in the fabrication of a three-dimensional memory according to a second embodiment of the present invention, and a first trench formed in the semiconductor substrate.
Fig. 24 is a schematic cross-sectional view illustrating sequentially filling a thinning stop layer and a first semiconductor material layer in the first trench in the preparation of the three-dimensional memory according to the second embodiment of the present invention.
Fig. 25 is a schematic cross-sectional view showing a second trench formed in the semiconductor substrate in the preparation of the three-dimensional memory according to the second embodiment of the present invention.
Fig. 26 is a schematic cross-sectional view illustrating a formation of a sacrificial material layer on a surface of the first semiconductor material layer and in the second trench in the fabrication of the three-dimensional memory according to the second embodiment of the present invention.
Fig. 27 is a schematic cross-sectional view showing a stacked structure formed on the sacrificial material layer in the fabrication of the three-dimensional memory according to the second embodiment of the present invention.
Fig. 28 is a schematic cross-sectional view showing a gate line slit formed in the stacked structure in the fabrication of the three-dimensional memory according to the second embodiment of the present invention.
Fig. 29 is a schematic cross-sectional view showing a formation of a sidewall protection layer on a sidewall of the gate line slit in the preparation of the three-dimensional memory according to the second embodiment of the present invention.
Fig. 30 is a schematic cross-sectional view showing the removal of the sacrificial material layer based on the gate line slit formed with the sidewall protection layer to form a sacrificial gap and re-opening the second trench in the fabrication of the three-dimensional memory according to the second embodiment of the present invention.
Fig. 31 is a schematic cross-sectional view showing a barrier layer of a memory string exposed by the sacrificial gap in the fabrication of a three-dimensional memory according to a second embodiment of the present invention.
Fig. 32 is a schematic cross-sectional view showing the removal of the aluminum oxide layer of the sidewall protection layer in the fabrication of the three-dimensional memory according to the second embodiment of the present invention.
Fig. 33 is a schematic cross-sectional view of a memory layer and a tunneling layer of a memory string exposed by the sacrificial gap in the preparation of a three-dimensional memory according to a second embodiment of the present invention.
Fig. 34 is a schematic cross-sectional view showing the formation of a second semiconductor material in the sacrificial gap in the fabrication of a three-dimensional memory according to a second embodiment of the present invention.
Fig. 35 is a schematic cross-sectional view showing the removal of semiconductor material on the sidewalls of the gate line slits in the fabrication of the three-dimensional memory device according to the second embodiment of the present invention, so as to form the second semiconductor material layer in the sacrificial gap.
Fig. 36 is a schematic cross-sectional view showing removal of the oxide layer in the sidewall protection layer in the preparation of the three-dimensional memory according to the second embodiment of the present invention.
Fig. 37 is a schematic cross-sectional view showing the replacement of the gate sacrificial layer with a conductive material to form a gate layer based on the gate line slit in the fabrication of the three-dimensional memory according to the second embodiment of the present invention.
Fig. 38 is a schematic cross-sectional view illustrating a process of forming a spacer filling layer in the gate line slit and the second trench in the preparation of the three-dimensional memory according to the second embodiment of the invention.
Fig. 39 is a schematic cross-sectional view showing a thinning process performed to remove the semiconductor substrate in the preparation of the three-dimensional memory according to the second embodiment of the present invention.
Fig. 40 is a schematic cross-sectional view illustrating formation of a back dielectric layer on a surface exposed after a thinning process and formation of conductive pillars in the back dielectric layer in preparation of a three-dimensional memory according to a second embodiment of the present invention.
Description of element reference numerals
101. Silicon substrate
102. A first oxide layer
103. Silicon nitride layer
104. A second oxide layer
105. Bottom polysilicon layer
106. First silicon oxynitride layer
107. Sacrificial polysilicon layer
108. Second silicon oxynitride layer
109. Top polysilicon layer
110. Interlayer dielectric layer
111. Grid sacrificial layer
112. Stacked structure
113. Barrier layer
114. Storage layer
115. Tunneling layer
116. Channel layer
117. Filled insulating core
118. Storage string
119. Middle polysilicon layer
120. Back dielectric layer
121. Conductive column
122. Spacer groove filling layer
123. Gate layer
124. Gate stack structure
125. Grid line gap
126. Virtual channel hole
201 301 semiconductor substrate
202 302 first dielectric oxide layer
203 303 thinning stop layer
204 304 second dielectric oxide layer
205 305 first semiconductor material layer
2051. Groove(s)
206 306 dielectric protective layer
207 307 sacrificial material layer
208 308 interlayer dielectric layer
209 309 gate sacrificial layer
210 310 stacked structure
211 311 barrier layer
212 312 storage layers
213 313 tunneling layer
214 314 channel layer
215 315 filled insulating core
216 316 storage string
217 317 grid line gap
218 318 first silicon nitride layer
219 Intermediate oxide layer 319
220 320 a second silicon nitride layer
221 321 alumina layer
222 322 sidewall protection layer
223 Sacrificial gap 323
2240 3240 second semiconductor material
224 324 a layer of a second semiconductor material
225 325 gate layer
226 326 gate stack structure
227 Dividing groove filling layer 327
228 328 backside dielectric layer
229 329 conductive posts
3011. First groove
3012. Second groove
S110 to S190, S210 to S290 steps
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact. It should be noted that the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present application, and only the components related to the present application are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The three-dimensional memory of the present invention is applicable to a variety of memory devices including, but not limited to, three-dimensional semiconductor memory devices such as 3D NAND. FIG. 1 illustrates a schematic cross-sectional view of an exemplary three-dimensional memory of the present invention prior to forming a gate line slit; fig. 2 shows a schematic cross-sectional view of the three-dimensional memory corresponding to fig. 1 after formation of conductive pillars. The preparation process is as follows: first, a three-dimensional memory structure as shown in fig. 1 is formed, which includes, in order from bottom to top, a silicon substrate 101 (Si-Sub), a first oxide layer 102 (other suitable dielectric materials are also possible), a silicon nitride layer 103 (other suitable dielectric materials are also possible), a second oxide layer 104, a bottom polysilicon layer 105, a first silicon oxynitride layer 106 (other suitable dielectric materials are also possible), a sacrificial polysilicon layer 107, a second silicon oxynitride layer 108 (other suitable dielectric materials are also possible), a top polysilicon layer 109, and a stacked structure 112; the stacked structure 112 is formed by alternately stacking interlayer dielectric layers 110 and gate sacrificial layers 111, a memory string 118 is formed in the stacked structure 112, the memory string 118 penetrates through the stacked structure 112, the top polysilicon layer 109, the second silicon oxynitride layer 108, the sacrificial polysilicon layer 107, the first silicon oxynitride layer 106 and the bottom polysilicon layer 105 in sequence from top to bottom and extends into the second oxide layer 104, and the memory string 118 includes a barrier layer 113, a memory layer 114, a tunneling layer 115, a channel layer 116 and a filled insulating core 117 sequentially arranged along a radially inward direction; next, as shown in fig. 2, a gate line slit 125 is formed in the stacked structure 112, and the gate line slit 125 penetrates through the stacked structure 112, the top polysilicon layer 109 and the second silicon oxynitride layer 108 to expose the middle sacrificial polysilicon layer 107; again, the sacrificial polysilicon layer 107, the first silicon oxynitride layer 106, the second silicon oxynitride layer 108, and the barrier layer 113, the memory layer 114, the tunneling layer 115 of the memory string 118 at the corresponding positions of the sacrificial polysilicon layer 107, the first silicon oxynitride layer 106, the second silicon oxynitride layer 108 are removed based on the gate line slit 125 to form a gap for filling the middle polysilicon layer 119, and polysilicon is filled in the gap to form the middle polysilicon layer 119, wherein the middle polysilicon layer 119 is located at the periphery of the channel layer 116 of the memory string 118 and is in contact with the sidewall of the channel layer 116; from this, the gate sacrificial layer 111 in the stacked structure 112 is replaced with a conductive material based on the gate line slit 125 to form a gate stack structure 124 alternately stacked by the gate layer 123 and the interlayer dielectric layer 110; then, filling insulating materials (such as titanium nitride, silicon oxide or silicon oxynitride and the like) in the gate line gaps to form separation groove filling layers; then, removing the back silicon substrate 101, the first oxide layer 102 and the silicon nitride layer 103 by using a mechanochemical grinding process CMP to expose the surface of the second oxide layer 104; next, forming a back dielectric layer 120 on the surface exposed after the thinning process; finally, a conductive pillar 121 is formed in the back dielectric layer 120, and the conductive pillar 121 sequentially penetrates through the back dielectric layer 120 and the second oxide layer 104 and then contacts the bottom polysilicon layer 105, so as to realize back extraction (back Pick Up).
Such a three-dimensional memory as shown in fig. 2 has the following disadvantages: (1) The thickness of the top polysilicon layer 109 affects the turn-on of the polysilicon channel layer 116 in the channel structure in this region; (2) Referring to fig. 3, since the etching of the Dummy channel hole is performed first and then the etching of the gate line slit 125 is performed, the position trench (guiding) of the boundary (filling region of the region shown in fig. 3B) between the gate line slit 125 and the Dummy channel hole (Dummy CH) is deeper. When the trench extends into the bottom polysilicon layer 105, the bottom polysilicon at location a in fig. 3 is also removed when the sacrificial polysilicon layer 107 (SAC Poly) in the middle is removed, thereby affecting device performance.
Based on this, the embodiments of the present invention provide two three-dimensional memories as shown in fig. 21 and 40, respectively, by forming a trench under the gate line slit to increase the thickness of the sacrificial material layer at the trench, the process window during the gate line slit etching can be increased, and the process difficulty can be reduced; meanwhile, the top polycrystalline silicon layer above the sacrificial material layer is omitted, so that the electrical property of the device is not affected. The technical scheme of the invention will be described below in connection with specific embodiments.
Example 1
Referring to fig. 4, the present embodiment describes a method for manufacturing a three-dimensional memory according to the first embodiment. Referring to fig. 4, the method for preparing the three-dimensional memory includes:
Step S110, providing a semiconductor substrate 201, and sequentially forming a thinning stop layer 203 and a first semiconductor material layer 205 on the semiconductor substrate 201, wherein a trench 2051 is formed in the first semiconductor material layer 205;
step S120, forming a sacrificial material layer 207 on the surface of the first semiconductor material layer 205 and in the trench 2051;
step S130, forming a stacked structure 210 on the sacrificial material layer 207, where the stacked structure 210 includes interlayer dielectric layers 208 and gate sacrificial layers 209 stacked alternately;
step S140, forming a gate line slit 217 in the stacked structure 210, where the gate line slit 217 penetrates through the stacked structure 210 and exposes a surface of the gate sacrificial layer 209, and the gate line slit 217 is located right above the trench 2051;
step S150, removing the sacrificial material layer 207 based on the gate line slit 217 to form a sacrificial gap 223 and reopening the trench 2051, and forming a second semiconductor material layer 224 in the sacrificial gap 223;
step S160, replacing the gate sacrificial layer 209 with a conductive material to form a gate layer 225 based on the gate line slit 217;
step S170, forming a spacer filling layer 227 in the gate line slit 217 and the trench 2051;
Step S180, performing a thinning process to remove the semiconductor substrate 201 and at least a portion of the thinning stop layer 203, and forming a back dielectric layer 228 on the surface exposed after the thinning process;
in step S190, a conductive pillar 229 is formed in the back dielectric layer 228, and the conductive pillar 229 sequentially penetrates through the back dielectric layer 228 and the rest of the thinning stop layer 203 and then contacts the first semiconductor material layer 205, where the conductive pillar 229 is used to implement back extraction (back Pick Up) of the first semiconductor material layer 205.
The method for preparing the three-dimensional memory according to the present embodiment will be described in detail below with reference to the schematic diagrams corresponding to the steps.
First, referring to fig. 5, step S110 is performed: a semiconductor substrate 201 is provided, and a thinning stop layer 203 and a first semiconductor material layer 205 are sequentially formed on the semiconductor substrate 201, wherein a trench 2051 is formed in the first semiconductor material layer 205. The semiconductor substrate 201 may be, for example, a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, or a GOI (Germanium-on-Insulator) substrate, or the like, such as a Silicon substrate. The material of the thinning Stop Layer 203 may be, for example, silicon nitride (of course, other suitable materials), and the Process Window (Process Window) of the back semiconductor substrate 201 is removed by depositing silicon nitride on the semiconductor substrate 201 as a Stop Layer (Stop Layer) of the thinning Process of the semiconductor substrate 201 by using CMP in the subsequent step S180, so as to completely remove the semiconductor substrate 201, and by disposing the thinning Stop Layer 203 of the silicon nitride material, the Process Window (Process Window) of the back semiconductor substrate 201 is greatly improved by CMP. The bottom surface of the trench 2051 needs to be lower than the bottom surface of the trench hole to be described later, so that the thickness of the sacrificial material layer 207 formed at the trench 2051 in step S120 can be ensured to be thicker, and the width of the trench 2051 needs to be larger than the width of the gate line slit 217 to be described later; the position and the size of the groove 2051 can increase the process window for etching the gate line gap 217, reduce the process difficulty and improve the yield.
It should be noted that, in this embodiment, the thickness of the first semiconductor material layer 205 is between 100 nm and 1000nm, and by using a thicker first semiconductor material layer 205, the etching of the channel hole can be stopped in the first semiconductor material layer 205, so that the subsequent step S180 of removing the semiconductor substrate 201 through the chemical mechanical planarization process is not affected.
Referring to fig. 5, in this embodiment, a first dielectric oxide layer 202 is further formed between the thinning stop layer 203 and the semiconductor substrate 201, and a second dielectric oxide layer 204 is further formed between the thinning stop layer 203 and the first semiconductor material layer 205, where a material of the first dielectric oxide layer 202 and the second dielectric oxide layer 204 may be, for example, silicon oxide.
Next, referring to fig. 6, step S120 is performed: a sacrificial material layer 207 is formed on the surface of the first semiconductor material layer 205 and in the trench 2051, and the material of the sacrificial material layer 207 includes, but is not limited to, polysilicon. It should be noted that, in order to avoid the first semiconductor material layer 205 being removed or damaged when the sacrificial material layer 207 is removed later, the dielectric protection layer 206 may be formed on the surface of the first semiconductor material layer 205 and the inner wall of the trench 2051; the sacrificial material is then formed on the dielectric protection layer 206 to form the sacrificial material layer 207, the sacrificial material layer 207 fills the trench 2051 and is higher than the upper surface of the trench 2051, that is, the sacrificial material layer 207 includes a portion filled in the trench 2051 and a horizontal portion higher than the second trench 2051, and the dielectric protection layer 206 is removed when the sacrificial material layer 207 is removed based on the gate line slit 217 to form a sacrificial gap 223 and reopen the trench 2051 in the subsequent step S150.
Referring to fig. 7, step S130 is performed to form a stacked structure 210 on the sacrificial material layer 207, wherein the stacked structure 210 includes alternately stacked interlayer dielectric layers 208 and gate sacrificial layers 209, and the interlayer dielectric layers 208 and the gate sacrificial layer 209 have a high etching selectivity to ensure that the interlayer dielectric layer 208 is hardly removed when the gate sacrificial layer 209 is subsequently removed, and the material of the gate sacrificial layer 209 may include, but is not limited to, silicon nitride (Si 3 N 4 ) The material of the interlayer dielectric layer 208 may include, but is not limited to, silicon oxide (SiO) 2 ). In the present invention, the number of layers of the gate sacrificial layer 209 in the stacked structure 210 may include 32 layers, 64 layers, 96 layers, 128 layers, etc., and specifically, the number of layers of the gate sacrificial layer 209 and the interlayer dielectric layer 208 in the stacked structure 210 may be set according to actual needs, which is not limited herein. The gate sacrificial layer 209 and the interlayer dielectric layer 208 may be formed using processes including, but not limited to, a physical vapor deposition (Physical Vapor Deposition, PVD), a chemical vapor deposition (Chemical Vapor Deposition, CVD), or an atomic layer deposition (Atomic Layer Deposition, ALD), such as chemical vapor deposition. It should be noted that, in the present embodiment, the topmost interlayer dielectric layer 208 in fig. 7 is composed of two parts, one part is the topmost interlayer dielectric layer 208 of the stack structure 210, and the other part is the capping dielectric layer formed on the topmost interlayer dielectric layer 208 after the memory string 216 is formed in the stack structure 210.
With continued reference to fig. 7, in this embodiment, the bottom layer of the stacked structure 210 is the gate sacrificial layer 209a, and the bottom layer of the gate sacrificial layer 209a can avoid that the bottom interlayer dielectric layer 208 of the stacked structure 210 is also removed or damaged when the sacrificial material layer 207 is subsequently removed, so as to affect the device performance, and the bottom layer of the gate sacrificial layer 209a is removed in the subsequent step S150 based on the gate line slit 217 to form the sacrificial gap 223 and reopen the trench 2051. It will be appreciated that in some embodiments, the bottommost layer of the stacked structure 210 may also be a thicker interlayer dielectric layer 208, such that the bottommost interlayer dielectric layer 208 remains partially thick after the sacrificial material layer 207 is removed.
With continued reference to fig. 7, in this embodiment, after forming the stacked structure 210, a step of forming a channel hole in the stacked structure 210 and forming a memory string 216 in the channel hole is further included. The channel hole sequentially penetrates through the gate stack 226, the second semiconductor material 224 and extends into the first semiconductor material 205, the memory string 216 includes a filled insulating core 215, a channel layer 214 surrounding the filled insulating core 215, and functional sidewalls surrounding the channel layer 214, and the functional sidewalls include a blocking layer 211, a memory layer 212, and a tunneling layer 213 sequentially formed on the sidewalls of the channel hole from the sidewalls of the channel hole to the center. As an example, the material of the barrier layer 211 and the tunneling layer 213 includes silicon oxide or silicon oxynitride, such as silicon oxynitride; the material of the memory layer 212 includes silicon nitride; as an example, the material filling the insulating core 215 may include silicon oxide.
Referring to fig. 8, step S140 is performed to form a gate line slot 217 in the stacked structure 210, wherein the gate line slot 217 penetrates through the stacked structure 210 and exposes a surface of the gate sacrificial layer 209, and the gate line slot 217 is located directly above the trench 2051. Since the width of the trench 2051 is greater than the width of the gate line slot 217, and the thickness of the gate sacrificial layer 209 at the trench 2051 is thicker, this increases the process window for etching the gate line slot 217, and improves the yield.
Referring to fig. 9-15, step S150 is performed to remove the sacrificial material layer 207 based on the gate line slit 217 to form a sacrificial gap 223 and reopen the trench 2051, and form a second semiconductor material layer 224 in the sacrificial gap 223. The method specifically comprises the following steps: step S151, forming a sidewall protection layer 222 on the sidewall of the gate line slot 217 (see fig. 9); step S152, removing the sacrificial material layer 207 based on the gate line slit 217 formed with the sidewall protection layer 222 to form a sacrificial gap 223 and reopening the trench 2051 (see fig. 10-13); step S153 forms the second semiconductor material layer 224 in the sacrificial gap 223 (see fig. 14 and 15).
Referring to fig. 9, in step S151, for example, a sidewall protection layer 222 formed of the first silicon nitride layer 218, the intermediate oxide layer 219, the second silicon nitride layer 220, and the aluminum oxide layer 221 may be sequentially formed on the sidewall of the isolation trench, and it is understood that in other embodiments, the sidewall protection layer 222 may be a multi-layer structure of other materials.
Referring to fig. 10 to 13, in step S152, first, the sacrificial material layer 207 is removed based on the wet etching of the gate line slit 217 formed with the sidewall protection layer 222 to form a sacrificial gap 223a (see fig. 10); next, the barrier layer 211 of the memory string 216 exposed by the sacrificial gap 223a, the dielectric protection layer 206 on the surface of the first semiconductor material layer 205 and the inner wall of the trench 2051, and the bottommost gate sacrificial layer 209a are removed by wet etching based on the gate line slit 217 formed with the sidewall protection layer 222 to form a sacrificial gap 223b and re-open the trench 2051 (see fig. 11); again, the aluminum oxide layer 221 of the sidewall protection layer 222 is removed based on the gate line slit 217 formed with the sidewall protection layer 222 by wet etching (see fig. 12); finally, the memory layer 212 and the tunneling layer 213 of the memory string 216 exposed by the sacrificial gap 223b are removed by wet etching based on the gate line slit 217 formed with the sidewall protection layer 222 to form a sacrificial gap 223 (see fig. 13), and the second silicon nitride layer 220 of the sidewall protection layer 222 is also removed at the time of removing the memory layer 212 and the tunneling layer 213.
Referring to fig. 14 and 15, in step S153, a second semiconductor material 2240 (for example, polysilicon) may be formed in the sacrificial gap 223 by a chemical vapor deposition method, where the second semiconductor material 2240 is formed on the sidewalls of the gate line slit 217 and the top surface of the stacked structure 210 (see fig. 14) in addition to being formed in the sacrificial gap 223; then, the second semiconductor material 2240 on the sidewalls of the gate line slit 217 and the top surface of the stacked structure 210 is etched away to form the second semiconductor material layer 224 in the sacrificial gap 223, wherein the second semiconductor material layer 224 is located at the periphery of the memory string 216 and contacts the channel layer 214.
It should be noted that, before step S153, a step of cleaning the surface of the sacrificial gap 223 is further included before the second semiconductor material layer 224 is formed in the sacrificial gap 223.
Note that, referring to fig. 16, after step S253, a step of etching to remove the intermediate oxide layer 219 (e.g. silicon oxide) of the sidewall protection layer 222 may be further included.
Referring to fig. 17, step S160 is performed: based on the gate line slit 217, the gate sacrificial layer 209 is replaced with a conductive material to form a gate layer 225. Specifically, the gate sacrificial layer 209 in the stacked structure 210 may be removed by wet etching based on the gate line slit 217 to form a gate gap, and the first silicon nitride layer 218 of the sidewall protection layer 222 is also removed at the same time; then, a high dielectric constant layer (for example, alumina) and a titanium nitride layer are sequentially formed on the side wall of the gate gap, and finally, tungsten (W) is filled in the gate gap formed with titanium nitride to form the gate layer 225, and the gate layer 225 and the interlayer dielectric layer 208 are alternately stacked to form a gate stack structure 226. It is understood that in other embodiments, the material of the gate layer 225 may further include any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped poly-Si (polysilicon), doped single-crystal Si, silicide, or any combination thereof.
Referring to fig. 18, step S170 is performed: a spacer fill layer 227 is formed in the gate line slot 217 and the trench 2051. Specifically, for example, the gate line slit 217 and the trench 2051 may be filled with silicon nitride, silicon oxide, or silicon oxynitride to form the isolation trench filling layer 227.
Referring to fig. 19-21, step S180 and step S190 are performed: performing thinning treatment to remove the semiconductor substrate 201 and at least part of the thinning stop layer 203, and forming a back dielectric layer 228 on the surface exposed after the thinning treatment; a conductive pillar 229 is formed in the back dielectric layer 228, and the conductive pillar 229 sequentially penetrates through the back dielectric layer 228 and the rest of the thinning stop layer 203 to contact the first semiconductor material layer 205.
Specifically, in the present embodiment, the semiconductor substrate 201 may be thinned by a CMP process, stopping at the thinning stop layer 203, to completely remove the semiconductor substrate 201 (see fig. 19); the thinning stop layer 203 is then removed (see fig. 20); next, a back dielectric layer 228 is formed on the surface of the second dielectric oxide layer 204 exposed after the removal of the thinning stop layer 203 (see fig. 21); finally, a hole is formed in the back dielectric layer 228 by photolithography, which sequentially penetrates through the back dielectric layer 228 and exposes the first semiconductor material layer 205, the hole of the conductive pillar 229 exposes the first semiconductor material layer 205, and a conductive material (e.g., tungsten) is filled in the hole of the conductive pillar 229 to form a conductive pillar 229 (see fig. 21).
Note that, in an embodiment, after the semiconductor substrate 201 is thinned and removed, the back dielectric layer 228 may be directly formed on the exposed surface of the thinned and stopped layer 203 without removing the thinned and stopped layer 203. In another embodiment, after the semiconductor substrate 201 is thinned and removed, the thinning stop layer 203 and the second dielectric oxide layer 204 may also be removed to expose the lower surface of the first semiconductor material layer 205, and a back dielectric layer 228 is formed on the lower surface of the first semiconductor material layer 205.
It should be noted that, compared with the technical solutions shown in fig. 1-2, the method for manufacturing the three-dimensional memory of the present embodiment omits the Top polysilicon layer (Top Poly) between the sacrificial material layer 207 and the stacked structure 210, so that the influence of the Top polysilicon layer on the conduction of the polysilicon channel layer 214 can be effectively improved.
Example two
Fig. 21 shows a schematic structural diagram of a three-dimensional memory manufactured by the manufacturing method of the first embodiment. Referring to fig. 21, in the present embodiment, the three-dimensional memory mainly includes a back dielectric layer 228, a trench 2051 (see fig. 17), a first semiconductor material layer 205, a second semiconductor material layer 224, a gate stack structure 226, and a conductive pillar 229. The three-dimensional memory structure increases the thickness of the sacrificial material layer 207 at the trench 2051 by forming the trench 2051 under the gate line slot 217 (see fig. 17), so that the process window in the etching of the gate line slot 217 can be increased and the process difficulty can be reduced; meanwhile, a Top polysilicon layer (Top Poly) between the sacrificial material layer 207 (for example, may be sacrificial polysilicon) and the stacked structure 210 is omitted, so that the influence of Top Poly on the conduction of the polysilicon channel layer 214 in the prior art can be effectively improved.
Specifically, referring to fig. 21, the first semiconductor material layer 205 is formed on the back dielectric layer 228, and the material of the first semiconductor material layer 205 includes, but is not limited to, polysilicon; the trench 2051 is formed in the first semiconductor material layer 205, the trench 2051 being located below the gate line slot 217; the second semiconductor material layer 224 is formed on the surface of the first semiconductor material layer 205 and is located on two sides of the trench 2051, wherein the material of the second semiconductor material layer 224 includes, but is not limited to, polysilicon; the spacer filling layer 227 is disposed in the gate line slot 217 and the trench 2051, that is, the spacer filling layer 227 sequentially penetrates through the gate stack structure 226 and the second semiconductor material layer 224 and is filled in the trench 2051, and the material of the spacer filling layer 227 includes, but is not limited to, silicon nitride, silicon oxide or silicon oxynitride; the conductive pillar 229 penetrates through the back dielectric layer 228 and contacts the first semiconductor material layer 205 to implement back extraction (back Pick Up) of the first semiconductor material layer 205, and the material of the conductive pillar 229 may include tungsten, for example. It should be noted that, in this embodiment, the bottom surface of the trench 2051 needs to be lower than the bottom end of the storage string 216 to be described later, that is, the bottom of the storage string 216 is higher than the bottom surface of the trench 2051, and the width of the portion of the spacer trench filling layer 227 located in the gate stack structure 226 is smaller than the width of the trench 2051, which is described in detail in the related portion of the second embodiment, and will not be described herein.
Referring to fig. 21, in the present embodiment, the gate stack 226 is formed on the second semiconductor material layer 224, and a channel hole for forming the memory string 216 is formed in the gate stack 226, wherein the gate stack 226 includes alternately stacked interlayer dielectric layers 208 and gate layers 225, and the channel hole sequentially penetrates through the gate stack 226, the second semiconductor material layer 224 and extends along the thickness directionInto the first semiconductor material layer 205. As an example, the number of layers of the gate layer 225 in the gate stack structure 226 may include 32 layers, 64 layers, 96 layers, 128 layers, etc., and specifically, the number of layers of the interlayer dielectric layer 208 and the gate layer 225 in the gate stack structure 226 may be set according to actual needs, which is not limited herein; the gate layer 225 is made of a conductive material, including but not limited to any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped poly-Si (polysilicon), doped single-crystal Si, silicide, or any combination thereof, such as tungsten (W); the material of the interlayer dielectric layer 208 may include, but is not limited to, silicon oxide (SiO 2 ) A layer. The interlayer dielectric layer 208 and the gate layer 225 may be formed using processes including, but not limited to, a physical vapor deposition (Physical Vapor Deposition, PVD), chemical vapor deposition (Chemical Vapor Deposition, CVD), or atomic layer deposition (Atomic Layer Deposition, ALD).
Note that, in this embodiment, the topmost interlayer dielectric layer 208 in fig. 21 is composed of two parts, one part is the topmost interlayer dielectric layer of the gate stack structure 226, and the other part is the capping dielectric layer formed on the topmost interlayer dielectric layer 208 after the memory string 216 is formed in the gate stack structure 226.
Referring to fig. 21, in the present embodiment, the three-dimensional memory further includes a memory string 216 formed in the channel hole, and the memory string 216 sequentially penetrates the gate stack 226 and the second semiconductor material layer 224 and extends into the first semiconductor material layer 205; the memory string 216 includes a filled insulating core 215, a channel layer 214 surrounding the filled insulating core 215, and functional sidewalls surrounding the channel layer 214, the functional sidewalls including a barrier layer 211, a memory layer 212, and a tunneling layer 213 sequentially formed along sidewalls of the channel hole to the center thereof. As an example, the material of the barrier layer 211 and the tunneling layer 213 includes silicon oxide or silicon oxynitride, such as silicon oxynitride; the material of the memory layer 212 includes silicon nitride; as an example, the material filling the insulating core 215 may include silicon oxide.
Referring to fig. 21, in the present embodiment, functional sidewalls of the memory string 216 corresponding to the second semiconductor material layer 224 are removed to expose the channel layer 214, so that the second semiconductor material layer 224 is located at the periphery of the memory string 216 and contacts the channel layer 214 when the second semiconductor material layer 224 is formed.
It should be noted that, in this embodiment, the thickness of the first semiconductor material layer 205 is between 100 nm and 1000nm, and by using a thicker first semiconductor material layer 205, the etching of the channel hole can be stopped in the first semiconductor material layer 205, so that the chemical mechanical planarization process of the back semiconductor substrate 201 is not affected.
Example III
Referring to fig. 22, the present embodiment describes a method for manufacturing a three-dimensional memory according to the second embodiment. Referring to fig. 22, the method for preparing the three-dimensional memory includes:
step S210, providing a semiconductor substrate 301, wherein a first trench 3011 and a second trench 3012 are formed in the semiconductor substrate 301, and the first trench 3011 is sequentially filled with a thinning stop layer 303 and a first semiconductor material layer 305;
step S220, forming a sacrificial material layer 307 on the surface of the first semiconductor material layer 305 and in the second trench 3012;
Step S230, forming a stack structure 310 on the sacrificial material layer 307, where the stack structure 310 includes interlayer dielectric layers 308 and gate sacrificial layers 309 that are alternately stacked;
step S240, forming a gate line slit 317 in the stacked structure 310, where the gate line slit 317 penetrates through the stacked structure 310 and exposes the surface of the gate sacrificial layer 309, and the gate line slit 317 is located right above the second trench 3012;
step S250, removing the sacrificial material layer 307 based on the gate line slit 317 to form a sacrificial gap 323 and reopening the second trench 3012, and forming a second semiconductor material layer 324 in the sacrificial gap 323;
step S260, replacing the gate sacrificial layer 309 with a conductive material to form a gate layer 325 based on the gate line slit 317;
step S270, forming a spacer filling layer 327 in the gate line slit 317 and the second trench 3012;
step S280, performing thinning treatment on the semiconductor substrate 301, and forming a back dielectric layer 328 on the surface exposed after the thinning treatment, where the thinning is stopped in the thinning stop layer 303;
in step S290, a conductive pillar 329 is formed in the back dielectric layer 328, where the conductive pillar 329 sequentially penetrates through the back dielectric layer 328 and the rest of the thinned stop layer 303 and then contacts the first semiconductor material layer 305, and the conductive pillar 329 is used to implement back extraction (back Pick Up) of the first semiconductor material layer 205.
The method for preparing the three-dimensional memory according to the present embodiment will be described in detail below with reference to the schematic diagrams corresponding to the steps.
First, referring to fig. 23-25, step S110 is performed: a semiconductor substrate 301 is provided, a first trench 3011 and a second trench 3012 are formed in the semiconductor substrate 301, and the first trench 3011 is filled with a thinning stop layer 303 and a first semiconductor material layer 305 in order. Specifically, referring first to fig. 23, a semiconductor substrate 301 is provided, and a first trench 3011 is formed on the semiconductor substrate 301 by a photolithography process, wherein the first trench 3011 extends in a direction parallel to a gate line slit 317, and the semiconductor substrate 301 may be, for example, a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, a Silicon-on-Insulator (SOI) substrate, a Germanium-on-Insulator (GOI) substrate, or the like, such as a Silicon substrate. Then, referring to fig. 24, a thinning Stop Layer 303 and a first semiconductor material Layer 305 are sequentially formed on the inner wall of the first trench 3011 formed on the semiconductor substrate 301, the first semiconductor material Layer 305 fills the first trench 3011 and is located on the same polishing plane on the surface of the semiconductor substrate 301, the material of the thinning Stop Layer 303 may be, for example, silicon nitride (of course, other suitable materials), and by depositing silicon nitride on the semiconductor substrate 301 as a Stop Layer (Stop Layer) for the thinning Process of the semiconductor substrate 301 in the subsequent step S180 by using chemical mechanical planarization CMP, the Process Window (Process Window) of the back semiconductor substrate 301 can be greatly improved by providing the thinning Stop Layer 303 of silicon nitride material by chemical mechanical planarization CMP. Finally, referring to fig. 25, a second trench 3012 is formed on the semiconductor substrate 301, the second trench 3012 is located directly under the gate line slit 317, and the bottom surface of the second trench 3012 is lower than the bottom surface of the first trench 3011, and meanwhile, the width of the gate line slit 317 is smaller than the width of the second trench 3012, so as to ensure that the thickness of the sacrificial material layer 307 formed at the second trench 3012 in step S220 is thicker; the position and the size of the groove can increase the process window for etching the gate line gap 317, reduce the process difficulty and improve the yield.
It should be noted that, in the present embodiment, compared to the three-dimensional memory structure of the embodiment, the thickness of the first semiconductor material layer 305 may be reduced, and the thickness of the first semiconductor material layer 305 is between 50 nm and 200nm, so that the influence on the electrical property caused by the excessive thickness of the Bottom Poly may be avoided.
Referring to fig. 24 and 25, in this embodiment, a first dielectric oxide layer 302 is further formed between the thinning stop layer 303 and the semiconductor substrate 301, and a second dielectric oxide layer 304 is further formed between the thinning stop layer 303 and the first semiconductor material layer 305, where the material of the first dielectric oxide layer 302 and the second dielectric oxide layer 304 may be, for example, silicon oxide.
Next, referring to fig. 26, step S220 is performed: a sacrificial material layer 307 is formed on the surface of the first semiconductor material layer 305 and in the second trench 3012, and the material of the sacrificial material layer 307 includes, but is not limited to, polysilicon. It should be noted that, in order to avoid that the first semiconductor material layer 305 is also removed or damaged when the sacrificial material layer 307 is removed later, a dielectric protection layer 306 may be formed on the surface of the first semiconductor material layer 305 and the inner wall of the second trench 3012; the sacrificial material is then formed on the dielectric protection layer 306 to form the sacrificial material layer 307, the sacrificial material layer 307 fills the second trench 3012 and is higher than the upper surface of the second trench 3012, i.e., the sacrificial material layer 307 includes a portion filled in the second trench 3012 and a horizontal portion higher than the second trench 3012, and the dielectric protection layer 306 is removed when the sacrificial material layer 307 is removed based on the gate line slit 317 to form a sacrificial gap 323 and reopen the trench in the subsequent step S250.
Referring to fig. 27, step S230 is performed to form a stacked structure 310 on the sacrificial material layer 307, where the stacked structure 310 includes alternately stacked interlayer dielectric layers 308 and gate sacrificial layers 309, and the interlayer dielectric layers 308 and the gate sacrificial layers 309 have a high etching selectivity to ensure that the interlayer dielectric layers 308 are hardly removed when the gate sacrificial layers 309 are subsequently removed, and the material of the gate sacrificial layers 309 may include, but is not limited to, silicon nitride (Si 3 N 4 ) The material of the interlayer dielectric layer 308 may include, but is not limited to, silicon oxide (SiO) 2 ). In the present invention, the number of layers of the gate sacrificial layer 309 in the stacked structure 310 may include 32 layers, 64 layers, 96 layers, 128 layers, etc., and specifically, the number of layers of the gate sacrificial layer 309 and the interlayer dielectric layer 308 in the stacked structure 310 may be set according to actual needs, which is not limited herein. The gate sacrificial layer 309 and the interlayer dielectric layer 308 may be formed using processes including, but not limited to, a physical vapor deposition (Physical Vapor Deposition, PVD), a chemical vapor deposition (Chemical Vapor Deposition, CVD), or an atomic layer deposition (Atomic Layer Deposition, ALD) process, such as chemical vapor deposition. In this embodiment, the topmost interlayer dielectric layer 308 in fig. 27 is formed by two parts, one part is the topmost interlayer dielectric layer 308 of the stack structure 310, and the other part is the capping dielectric layer formed on the topmost interlayer dielectric layer 308 after the memory string 316 is formed in the stack structure 310.
With continued reference to fig. 27, in this embodiment, the bottom layer of the stacked structure 310 is the gate sacrificial layer 309a, and the bottom layer of the gate sacrificial layer 309a can avoid that the bottom interlayer dielectric layer 308 of the stacked structure 310 is also removed or damaged when the sacrificial material layer 307 is subsequently removed, thereby affecting the device performance, and the bottom layer of the gate sacrificial layer 309a is removed in the subsequent step S250 based on the gate line slit 317 to form the sacrificial gap 323 and reopen the second trench 3012. It will be appreciated that in some embodiments, the bottom layer of the stacked structure 310 may also be a thicker interlayer dielectric layer 308, so that the bottom interlayer dielectric layer 308 remains partially thick after the sacrificial material layer 307 is removed.
With continued reference to fig. 27, in this embodiment, after forming the stack structure 310, a step of forming a channel hole in the stack structure 310 and forming a memory string 316 in the channel hole is further included. The channel hole sequentially penetrates through the gate stack 326, the second semiconductor material layer 324 and extends into the first semiconductor material layer 305, the memory string 316 includes a filled insulating core 315, a channel layer 314 surrounding the filled insulating core 315, and functional sidewalls surrounding the channel layer 314, and the functional sidewalls include a blocking layer 311, a memory layer 312, and a tunneling layer 313 sequentially formed on the sidewalls of the channel hole from the sidewalls of the channel hole to the center. As an example, the material of the barrier layer 311 and the tunneling layer 313 includes silicon oxide or silicon oxynitride, such as silicon oxynitride; the material of the memory layer 312 includes silicon nitride; as an example, the material filling the insulating core 315 may include silicon oxide.
It should be noted that, referring to fig. 27, in this embodiment, the thinning stop layer 303 may also be used as an etching stop layer of a channel hole, that is, the channel hole exposes the upper surface of the thinning stop layer 303, in other words, the barrier layer 311 of the memory string 316 contacts the thinning stop layer 303.
Referring to fig. 28, step S240 is performed to form a gate line slit 317 in the stacked structure 310, wherein the gate line slit 317 penetrates through the stacked structure 310 and exposes the surface of the gate sacrificial layer 309, and the gate line slit 317 is located right above the second trench 3012. Since the width of the second trench 3012 is greater than the width of the gate line slit 317, and the thickness of the gate sacrificial layer 309 at the second trench 3012 is thicker, this increases the process window for etching the gate line slit 317, and improves the yield.
Referring to fig. 29-35, step S250 is performed to remove the sacrificial material layer 307 based on the gate line slit 317 to form a sacrificial gap 323 and reopen the second trench 3012, and form a second semiconductor material layer 324 in the sacrificial gap 323. The method specifically comprises the following steps: step S251, forming a sidewall protection layer 322 on the sidewall of the gate line slit 317 (see fig. 29); step S252, removing the sacrificial material layer 307 based on the gate line slit 317 formed with the sidewall protection layer 322 to form a sacrificial gap 323 and reopening the second trench 3012 (see fig. 30-33); step S253, forming the second semiconductor material layer 324 in the sacrificial gap 323 (see fig. 34 and 35).
Referring to fig. 29, in step S251, for example, a sidewall protection layer 322 formed by a first silicon nitride layer 318, an intermediate oxide layer 319, a second silicon nitride layer 320, and an aluminum oxide layer 321 may be sequentially formed on the sidewall of the isolation trench, and it is understood that in other embodiments, the sidewall protection layer 322 may be a multi-layer structure of other materials.
Referring to fig. 30 to 33, in step S252, first, the sacrificial material layer 307 is removed based on the wet etching based on the gate line slit 317 formed with the sidewall protection layer 322 to form a sacrificial gap 323a (see fig. 30); next, the barrier layer 311 of the memory string 316 exposed by the sacrificial gap 323a, the dielectric protection layer 306 on the surface of the first semiconductor material layer 305 and the inner wall of the second trench 3012, and the bottommost gate sacrificial layer 309a are removed by wet etching based on the gate line slit 317 formed with the sidewall protection layer 322 to form a sacrificial gap 323b and reopen the second trench 3012 (see fig. 31); again, the aluminum oxide layer 321 of the sidewall protection layer 322 is removed based on the gate line slit 317 formed with the sidewall protection layer 322 by wet etching (see fig. 32); finally, the memory layer 312 and the tunneling layer 313 of the memory string 316 exposed by the sacrificial gap 323b are removed by wet etching based on the gate line slit 317 formed with the sidewall protection layer 322 to form a sacrificial gap 323 (see fig. 33), and the second silicon nitride layer 320 of the sidewall protection layer 322 is also removed at the time of removing the memory layer 312 and the tunneling layer 313.
Referring to fig. 34 and 35, in step S253, a second semiconductor material 3240 (e.g. polysilicon) is formed in the sacrificial gap 323, for example, by chemical vapor deposition, wherein the second semiconductor material 3240 is formed on the sidewalls of the gate line slit 317 and the top surface of the stacked structure 310 (see fig. 34) in addition to being formed in the sacrificial gap 323; then, the second semiconductor material 3240 on the sidewalls of the gate line slit 317 and the top surface of the stacked structure 310 is etched away to form the second semiconductor material layer 324 in the sacrificial gap 323, wherein the second semiconductor material layer 324 is located at the periphery of the memory string 316 and contacts the channel layer 314.
It should be noted that, before step S253, a step of cleaning the surface of the sacrificial gap 323 may be further included before the second semiconductor material layer 324 is formed in the sacrificial gap 323.
Note that, referring to fig. 36, after step S253, a step of etching to remove the intermediate oxide layer 319 (e.g. silicon oxide) of the sidewall protection layer 322 may be further included.
Referring to fig. 37, step S260 is performed: based on the gate line slit 317, the gate sacrificial layer 309 is replaced with a conductive material to form a gate layer 325. Specifically, the gate sacrificial layer 309 in the stacked structure 310 may be removed by wet etching based on the gate line slit 317 to form a gate gap, and in this step, the first silicon nitride layer 318 in the sidewall protection layer 322 is also removed; then, a high dielectric constant layer (for example, aluminum oxide) and a titanium nitride layer are sequentially formed on the side wall of the gate gap, and finally, tungsten (W) is filled in the gate gap formed with titanium nitride to form the gate layer 325, and the gate layer 325 and the interlayer dielectric layer 308 which are alternately stacked with each other form a gate stack structure 326. It is appreciated that in other embodiments, the material of the gate layer 325 may further include any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped poly-Si (polysilicon), doped single-crystal Si, silicide, or any combination thereof.
Referring to fig. 38, step S270 is performed: a spacer filling layer 327 is formed in the gate line slit 317 and the second trench 3012, and for example, silicon nitride, silicon oxide, or silicon oxynitride may be filled in the gate line slit 317 and the second trench 3012 to form the spacer filling layer 327.
Referring to fig. 39 and 40, step S280 and step S290 are performed: thinning the semiconductor substrate 301, and forming a back dielectric layer 328 on the surface exposed after the thinning, wherein the thinning is stopped in the thinning stop layer 303; a conductive post 329 is formed in the back dielectric layer 328, and the conductive post 329 sequentially penetrates through the back dielectric layer 328 and the rest of the thinning stop layer 303 to contact the first semiconductor material layer 305.
Specifically, in the present embodiment, the semiconductor substrate 301 may be thinned by a CMP process, and stopped at the thinning stop layer 303 to completely remove the semiconductor substrate 301 (see fig. 39); the thinning stop layer 303 is then removed (see fig. 40); next, a back dielectric layer 328 is formed on the surface (surface of the thinning stop layer 303) exposed after the thinning process (see fig. 40); finally, a conductive post 329 is formed in the back dielectric layer 328 by using a photolithography process, which sequentially penetrates through the back dielectric layer 328 and the rest of the thinned stop layer 303 and exposes the first semiconductor material layer 305, the conductive post 329 exposing the first semiconductor material layer 305, and a conductive material (e.g., tungsten) is filled in the conductive post 329 to form a conductive post 329 (see fig. 40), and the conductive post 329 is used to implement back extraction (Backside Pick Up) of the first semiconductor material layer 205.
It should be noted that, in an embodiment, when the bottom of the memory string 316 is formed inside the first semiconductor material and a certain thickness of the first semiconductor material layer 305 is still maintained between the bottom and the second dielectric oxide layer 304, after the semiconductor substrate 301 is thinned and removed, the thinning stop layer 303 may be removed to expose the lower surface of the second dielectric oxide layer 304, and the back dielectric layer 328 may be formed on the lower surface of the second dielectric oxide layer 304. In another embodiment, when the bottom of the memory string 316 is formed inside the first semiconductor material and the first semiconductor material layer 305 still maintains a certain thickness with the second dielectric oxide layer 304, after the semiconductor substrate 301 is thinned and removed, the thinning stop layer 303 and the second dielectric oxide layer 304 may also be removed to expose the lower surface of the first semiconductor material layer 305, and a back dielectric layer 328 is formed on the lower surface of the first semiconductor material layer 305.
It should be noted that, compared with the technical solutions shown in fig. 1-2, the method for manufacturing the three-dimensional memory in this embodiment omits the Top polysilicon layer (Top Poly) between the sacrificial material layer 307 and the stacked structure 310, so that the influence of the Top polysilicon layer on the conduction of the polysilicon channel layer 314 can be effectively improved.
It should be noted that, in the three-dimensional memory manufacturing method of the present embodiment, compared with the second embodiment, the thickness of the first semiconductor material layer 305 (Bottom Poly) can be reduced, and the influence on the electrical property, which may be caused by the excessive thickness of the Bottom Poly, can be avoided.
Example IV
Fig. 40 shows a schematic structural diagram of a three-dimensional memory fabricated using the fabrication method of example three. Referring to fig. 40, in the present embodiment, the three-dimensional memory mainly includes a back dielectric layer 328, a semiconductor substrate 301, a first trench 3011 (see fig. 23), a second trench 3012 (see fig. 37), a first semiconductor material layer 305, a second semiconductor material layer 324, a gate stack 326 and a conductive pillar 329. The three-dimensional memory structure increases the thickness of the sacrificial material layer 307 at the trench by forming the trench under the gate line slit 317 (see fig. 37), so that the process window during etching of the gate line slit 317 can be increased, and the process difficulty can be reduced; meanwhile, a polysilicon layer (Top Poly) between the sacrificial material layer 307 (for example, may be sacrificial polysilicon) and the stacked structure 310 is omitted, so that the influence of the Top Poly on the conduction of the polysilicon channel layer 314 in the prior art can be effectively improved.
Specifically, referring to fig. 40, the semiconductor substrate 301 is disposed on the back dielectric layer 328; the first trench 3011 is formed on the semiconductor substrate 301, and the first trench 3011 exposes a surface of the back dielectric layer 328; the second trench 3012 is formed on the semiconductor substrate 301, and the second trench 3012 exposes the surface of the back dielectric layer 328, and the second trench 3012 is located below the gate line slit 317; the first semiconductor material layer 305 is formed in the first trench 3011, and the material of the first semiconductor material layer 305 includes, but is not limited to, polysilicon; the second semiconductor material layer 324 is formed on a common surface of the first semiconductor material layer 305 and the semiconductor substrate 301, and the material of the second semiconductor material layer 324 includes, but is not limited to, polysilicon; the spacer filling layer 327 is disposed in the gate line slit 317 and the second trench 3012, that is, the spacer filling layer 327 sequentially penetrates through the gate stack structure 326, the second semiconductor material layer 324 and is filled in the second trench 3012, and the material of the spacer filling layer 327 includes but is not limited to silicon nitride, silicon oxide or silicon oxynitride; the conductive pillar 329 penetrates the back dielectric layer 328 and contacts the first semiconductor material layer 305 to realize back extraction (back Pick Up) of the first semiconductor material layer 205, and the material of the conductive pillar 329 may include tungsten, for example. It should be noted that, the width of the portion of the spacer filling layer 327 located in the gate stack structure 326 is smaller than the width of the second trench 3012, and the detailed reason is described in the fourth embodiment below, which is not described herein.
It should be noted that, in the three-dimensional memory structure of the present embodiment, compared with the three-dimensional memory structure of the first embodiment, the thickness of the first semiconductor material layer 305 may be reduced, and the thickness of the first semiconductor material layer 305 may be between 50 nm and 200nm, so that the influence on the electrical property caused by the excessive thickness of the Bottom Poly may be avoided.
Referring to fig. 40, in the present embodiment, the gate stack 326 is formed on the first layerA channel hole for forming the memory string 316 is formed in the gate stack structure 326 above the first trench 3011 on the two semiconductor material layers 324, wherein the gate stack structure 326 includes alternately stacked interlayer dielectric layers 308 and gate layers 325, and the channel hole sequentially penetrates through the gate stack structure 326 and the second semiconductor material layers 324 in a thickness direction and extends into the first semiconductor material layer 305. As an example, in the gate stack structure 326, the number of layers of the gate layer 325 may include 32 layers, 64 layers, 96 layers, 128 layers, etc., and specifically, the number of layers of the interlayer dielectric layer 308 and the gate layer 325 in the gate stack structure 326 may be set according to actual needs, which is not limited herein; the gate layer 325 is made of a conductive material including, but not limited to, any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped poly-Si (polysilicon), doped single-crystal Si, silicide, or any combination thereof, such as tungsten (W); the material of the interlayer dielectric layer 308 may include, but is not limited to, silicon oxide (SiO 2 ) A layer. The interlayer dielectric layer 308 and the gate layer 325 may be formed using processes including, but not limited to, a physical vapor deposition (Physical Vapor Deposition, PVD) process, a chemical vapor deposition (Chemical Vapor Deposition, CVD) process, or an atomic layer deposition (Atomic Layer Deposition, ALD) process.
In this embodiment, the topmost interlayer dielectric layer 308 in fig. 40 is composed of two parts, one part is the topmost interlayer dielectric layer 308 of the gate stack structure 326, and the other part is the capping dielectric layer formed on the topmost interlayer dielectric layer 308 after the memory string 316 is formed in the gate stack structure 326.
Referring to fig. 40, in the present embodiment, the three-dimensional memory further includes a memory string 316 formed in the channel hole, and the memory string 316 sequentially penetrates through the gate stack 326, the second semiconductor material layer 324 and extends into the first semiconductor material layer 305; the memory string 316 includes a filled insulating core 315, a channel layer 314 surrounding the filled insulating core 315, and functional sidewalls surrounding the channel layer 314, the functional sidewalls including a barrier layer 311, a memory layer 312, and a tunneling layer 313 sequentially formed along sidewalls of the channel hole to the center thereof. As an example, the material of the barrier layer 311 and the tunneling layer 313 includes silicon oxide or silicon oxynitride, such as silicon oxynitride; the material of the memory layer 312 includes silicon nitride; as an example, the material filling the insulating core 315 may include silicon oxide.
Referring to fig. 40, in this embodiment, a thinning stop layer 303 is further formed between the first semiconductor material layer 305 and the inner wall of the first trench, and the thinning stop layer 303 may also be used as an etching stop layer of a channel hole, that is, the channel hole exposes the upper surface of the thinning stop layer 303, in other words, the barrier layer 311 of the memory string 316 contacts with the thinning stop layer 303. As an example, the material of the thinning stop layer 303 may be silicon nitride (of course, other suitable materials may be used).
Referring to fig. 40, in an alternative embodiment, a second dielectric oxide layer 304 is further formed between the first semiconductor material layer and the thinning stop layer 303, and the material of the second dielectric oxide layer 304 may be, for example, silicon oxide.
Referring to fig. 40, in the present embodiment, functional sidewalls of the memory string 316 corresponding to the second semiconductor material layer 324 are removed to expose the channel layer 314, so that the second semiconductor material layer 324 is located at the periphery of the memory string 316 and contacts the channel layer 314 when the second semiconductor material layer 324 is formed.
In summary, by using the method and the device, the thickness of the sacrificial material layer at the groove is increased by forming the groove below the gate line gap, so that the process window during etching the gate line gap can be increased, and the process difficulty is reduced; by using the invention, the Process Window (Process Window) of removing the back semiconductor substrate by the chemical mechanical planarization Process can be greatly improved by depositing the thinning stop layer (such as silicon nitride) on the semiconductor substrate; by using the invention, the Top polysilicon layer (Top Poly) between the sacrificial material layer (such as sacrificial polysilicon, SAC Poly) and the stacking structure is omitted, so that the influence of Top Poly on the conduction of the polysilicon channel layer in the prior art can be effectively improved; in the first embodiment of the present invention, since a thicker first semiconductor material layer (Bottom Poly) is used, the etching of the channel hole can be stopped in the first semiconductor material layer without affecting the chemical mechanical planarization process of the back semiconductor substrate; in the three-dimensional memory structure according to the second embodiment of the present invention, compared to the three-dimensional memory structure according to the first embodiment, the thickness of the first semiconductor material layer (e.g., the bottom polysilicon layer) can be reduced, and the influence on the electrical property, which may be caused by the excessive thickness of the first semiconductor material layer, can be avoided.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (25)

1. A three-dimensional memory, the three-dimensional memory comprising:
a back dielectric layer;
the semiconductor substrate is arranged on the back dielectric layer;
the first groove is formed on the semiconductor substrate, and the surface of the back dielectric layer is exposed by the first groove;
the second groove is formed on the semiconductor substrate and is positioned below the gate line gap, and the second groove exposes the surface of the back dielectric layer;
a first semiconductor material layer formed in the first trench;
a second semiconductor material layer formed on a common surface of the first semiconductor material layer and the semiconductor substrate;
a gate stack structure formed on the second semiconductor material layer;
The separation groove filling layer sequentially penetrates through the grid laminated structure, the second semiconductor material layer and is filled in the second groove; and
and the conductive column penetrates through the back dielectric layer and is in contact with the first semiconductor material layer.
2. The three-dimensional memory of claim 1, further comprising a memory string extending sequentially through the gate stack, the second layer of semiconductor material, and into the first layer of semiconductor material.
3. The three-dimensional memory of claim 2, wherein the memory string comprises functional sidewalls and a channel layer disposed sequentially in a radially inward direction, the second semiconductor material layer being located at a periphery of the memory string and in contact with the channel layer.
4. The three-dimensional memory of claim 2, wherein a bottom of the memory string is higher than a bottom surface of the separator trench fill layer.
5. The three-dimensional memory of claim 1, wherein the gate stack comprises alternating stacks of interlayer dielectric layers and gate layers.
6. The three-dimensional memory of claim 5, wherein the material of the gate layer comprises tungsten.
7. The three-dimensional memory of claim 1, wherein the material of the first semiconductor material layer comprises polysilicon.
8. The three-dimensional memory of claim 1, wherein a width of a portion of the separation trench fill layer located in the gate stack is less than a width of the second trench.
9. The three-dimensional memory of claim 1, wherein the material of the spacer trench fill layer comprises silicon nitride, silicon oxide, or silicon oxynitride.
10. The three-dimensional memory of claim 1, wherein a thinning stop layer is further formed between the first semiconductor material layer and an inner wall of the first trench.
11. The three-dimensional memory of claim 1, wherein the material of the second semiconductor material layer comprises polysilicon.
12. The three-dimensional memory of any one of claims 1-11, wherein the first semiconductor material layer has a thickness between 50-200 nm.
13. A method for manufacturing a three-dimensional memory, the method comprising:
Providing a semiconductor substrate, wherein a first groove and a second groove are formed in the semiconductor substrate, and a thinning stop layer and a first semiconductor material layer are sequentially filled in the first groove;
forming a sacrificial material layer on the surface of the first semiconductor material layer and in the second groove;
forming a stacked structure on the sacrificial material layer, wherein the stacked structure comprises interlayer dielectric layers and gate sacrificial layers which are alternately stacked;
forming a grid line gap in the stacked structure, wherein the grid line gap penetrates through the stacked structure and exposes the surface of the sacrificial material layer, and the grid line gap is positioned right above the second groove;
removing the sacrificial material layer based on the gate line gap to form a sacrificial gap and re-opening the second trench, and forming a second semiconductor material layer in the sacrificial gap;
replacing the gate sacrificial layer with a conductive material to form a gate layer based on the gate line slit;
forming a separation groove filling layer in the gate line gap and the second groove;
thinning the semiconductor substrate, and forming a back dielectric layer on the surface exposed after the thinning, wherein the thinning is stopped at the thinning stop layer;
And forming a conductive column in the back dielectric layer, wherein the conductive column sequentially penetrates through the back dielectric layer and the rest of the thinning stop layer and then contacts with the first semiconductor material layer.
14. The method of claim 13, further comprising the step of forming a memory string in the stacked structure, wherein the memory string sequentially extends through the stacked structure, the second layer of semiconductor material, and into the first layer of semiconductor material.
15. The method of claim 14, wherein the memory string includes a functional sidewall and a channel layer sequentially disposed in a radially inward direction, and the second semiconductor material layer is located at a periphery of the memory string and contacts the channel layer.
16. The method of claim 13, wherein the depth of the second trench is greater than the depth of the first trench.
17. The method of claim 13, wherein the step of forming a sacrificial material layer on the surface of the first semiconductor material layer and in the second trench comprises:
Forming a dielectric protection layer on the surface of the first semiconductor material layer and the inner wall of the second groove;
forming the sacrificial material layer on the dielectric protection layer;
wherein the dielectric protection layer is removed when the sacrificial material layer is subsequently removed based on the gate line slit to form a sacrificial gap and the second trench is reopened to remove the sacrificial material layer.
18. The method of claim 13, wherein the removing the sacrificial material layer based on the gate line slit to form a sacrificial gap and reopening the second trench, and the forming the second semiconductor material layer in the sacrificial gap comprises:
forming a side wall protection layer on the side wall of the grid line gap;
the sacrificial material layer is removed based on the gate line slit formed with the sidewall protection layer to form a sacrificial gap and reopen the second trench, and the second semiconductor material layer is formed in the sacrificial gap.
19. The method of claim 18, wherein the step of forming a sidewall protection layer on the sidewall of the gate line slit comprises sequentially forming a sidewall protection layer consisting of nitride layer-oxide layer-nitride layer-aluminum oxide on the sidewall of the gate line slit.
20. The method of claim 18, further comprising the step of cleaning a surface of the sacrificial gap prior to forming the second semiconductor material layer in the sacrificial gap.
21. The method of claim 13, wherein the step of replacing the gate sacrificial layer with a conductive material to form a gate layer comprises replacing the gate sacrificial layer with tungsten to form the gate layer.
22. The method of claim 13, wherein the material of the first semiconductor material layer comprises polysilicon; the material of the second semiconductor material layer comprises polysilicon.
23. The method of claim 13, wherein in the step of forming a gate line slit in the stacked structure, a width of the gate line slit is smaller than a width of the second trench.
24. The method of claim 13, wherein the step of forming a spacer fill layer in the gate line gap and the second trench comprises filling silicon nitride, silicon oxide, or silicon oxynitride in the gate line gap and the second trench to form a spacer fill layer.
25. The method of any one of claims 13-24, wherein the first semiconductor material layer has a thickness between 50-200 nm.
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