CN112713154B - Three-dimensional memory structure and preparation method thereof - Google Patents
Three-dimensional memory structure and preparation method thereof Download PDFInfo
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- CN112713154B CN112713154B CN202110171089.8A CN202110171089A CN112713154B CN 112713154 B CN112713154 B CN 112713154B CN 202110171089 A CN202110171089 A CN 202110171089A CN 112713154 B CN112713154 B CN 112713154B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a three-dimensional memory structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a semiconductor substrate with a defined junction area, forming a pre-groove in the junction area and filling to form a bottom compensation structure to form a laminated structure, preparing a virtual channel hole structure exposing the bottom compensation structure in the laminated structure, filling to form a stress buffer structure, and preparing a grid line dividing groove exposing the bottom compensation structure in the laminated structure, wherein an interface between the grid line dividing groove and the stress buffer structure is positioned in a region corresponding to the bottom compensation structure. The bottom compensation structure is manufactured in advance at the junction of the grid line dividing Groove (GLC) and the virtual channel hole structure (DCH), so that the problem of sharp corners of the grid line dividing groove can be effectively avoided based on the bottom compensation structure, and in addition, the process window for combining the grid line dividing groove with the virtual channel hole structure can be further increased based on the bottom compensation structure.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a three-dimensional memory structure and a preparation method thereof.
Background
To overcome the limitations of two-dimensional memory devices, memory devices having three-dimensional (3D) structures have been developed to increase integration density by three-dimensionally disposing memory cells over a substrate. The 3D NAND memory has a higher storage density per unit area than a general two-dimensional memory device due to its three-dimensional stacked structure, and is a very innovative main development direction of the memory. Currently, in the process of 3D NAND memory, the number of layers of the device stack structure is increasing based on the requirement of improving the device performance.
In a three-dimensional memory device such as a 3D NAND flash memory, a memory array may include a core (GB) region and a step region (SS). The core region has a substrate and a stacked structure in which a plurality of transistors for storing electric charges are formed. The step area is provided with a plurality of electric connection column structures to realize the electric extraction of the core area device. The step region is further formed with a plurality of gate line Cut structures (gate line Cut) to separate blocks, and the CD of the gate line Cut structures after etching is greatly changed due to the stress of the dielectric layer (such as TEOS), wherein the change can be improved by introducing a Dummy channel hole (Dummy CH), however, the problem of effective configuration between the Dummy channel hole and the gate line Cut structures is difficult to be effectively solved.
Therefore, it is necessary to provide a three-dimensional memory structure and a method for manufacturing the same to solve the above-mentioned problems.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a three-dimensional memory structure and a method for manufacturing the same, which are used for solving the problems of the prior art such as the configuration of the dummy channel holes and the filling and gate line dividing structures thereof.
To achieve the above and other related objects, the present invention provides a method for manufacturing a three-dimensional memory structure, the method comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a step region, and the step region is defined with a junction region;
etching the semiconductor substrate to form a prefabricated groove at a position corresponding to the junction area;
filling the pre-formed groove to form a bottom compensation structure in the pre-formed groove, wherein the upper surface of the bottom compensation structure is level with the upper surface of the semiconductor substrate;
forming a laminated structure on the semiconductor substrate, wherein the laminated structure at least covers the bottom compensation structure;
etching the laminated structure to form a virtual channel hole structure in the laminated structure, wherein the virtual channel hole structure extends to the semiconductor substrate and has an overlapping region with the bottom compensation structure;
filling the virtual channel hole structure to form a stress buffer structure in the virtual channel hole structure;
and etching the laminated structure to form a grid line dividing groove in the laminated structure, wherein the grid line dividing groove extends to the semiconductor substrate and has an overlapping area with the bottom compensation structure, and an interface is arranged between the grid line dividing groove and the stress buffer structure and is positioned in an area corresponding to the bottom compensation structure.
Optionally, the material of the bottom compensation structure is the same as the material of the stress buffering structure.
Optionally, the material of the stress buffer structure comprises silicon oxide, and the manner of forming the silicon oxide comprises a photoresist protection oxidation manner.
Optionally, the stacked structure includes sacrificial layers and dielectric layers stacked alternately, wherein the dielectric layers are in contact with the surface of the semiconductor substrate.
Optionally, the step region includes a bridge region and a step connection region adjacent to the bridge region, the stress buffer structure is located in the bridge region, and the gate line dividing groove is located in the step connection region and extends to the bridge region.
Optionally, the gate line dividing groove includes an extension portion extending into the stress buffering structure, and the stress buffering structure surrounds the extension portion.
Optionally, the extending direction of the gate line dividing groove is defined as a first direction, the direction perpendicular to the first direction is defined as a second direction, and the direction parallel and opposite to the first direction is defined as a third direction, wherein the size of the second direction of the gate line dividing groove increases stepwise along the first direction, and the size of the second direction of the stress buffering structure increases stepwise along the third direction.
In addition, the invention also provides a three-dimensional memory structure, which is preferably prepared by adopting the preparation method of the invention, and of course, the three-dimensional memory structure can also be prepared by adopting other methods, and the three-dimensional memory structure comprises:
a semiconductor substrate comprising a step region, wherein the step region defines a junction region;
the semiconductor device comprises a semiconductor substrate, a junction area, a pre-groove and a bottom compensation structure, wherein the pre-groove is formed in the semiconductor substrate corresponding to the junction area, the bottom compensation structure is formed in the pre-groove, and the upper surface of the bottom compensation structure is flush with the upper surface of the semiconductor substrate;
a stacked structure formed on the semiconductor substrate and covering the pre-groove, the stacked structure covering at least the bottom compensation structure;
a dummy channel hole structure formed in the stacked structure and extending to the semiconductor substrate and having an overlap region with the bottom compensation structure, and a stress buffer structure filled in the dummy channel hole;
and the grid line dividing groove is formed in the laminated structure, extends to the semiconductor substrate and has an overlapping area with the bottom compensation structure, wherein an interface is formed between the grid line dividing groove and the virtual channel hole structure, and the interface is positioned in the area corresponding to the bottom compensation structure.
Optionally, the material of the bottom compensation structure is the same as the material of the stress buffering structure; the materials of the stress buffer structure comprise silicon oxide.
Optionally, the stacked structure includes sacrificial layers and dielectric layers stacked alternately, wherein the dielectric layers are in contact with the surface of the semiconductor substrate.
Optionally, the step region includes a bridge region and a step connection region adjacent to the bridge region, the stress buffer structure is located in the bridge region, and the gate line dividing groove is located in the step connection region and extends to the bridge region.
Optionally, the gate line dividing groove includes an extension portion extending into the stress buffering structure, and the stress buffering structure surrounds the extension portion.
Optionally, the extending direction of the gate line dividing groove is defined as a first direction, the direction perpendicular to the first direction is defined as a second direction, and the direction parallel and opposite to the first direction is defined as a third direction, wherein the size of the second direction of the gate line dividing groove increases stepwise along the first direction, and the size of the second direction of the stress buffering structure increases stepwise along the third direction.
As described above, the three-dimensional memory structure and the method for manufacturing the same of the present invention can effectively avoid the problem of sharp corners of the gate line dividing grooves by manufacturing the bottom compensation structure in advance at the junction of the gate line dividing Grooves (GLC) and the virtual channel hole structure (DCH), and can further increase the process window for combining the gate line dividing grooves with the virtual channel hole structure based on the bottom compensation structure.
Drawings
FIG. 1 shows a process flow diagram of the fabrication of a three-dimensional memory structure in an example of the invention.
Fig. 2 shows a schematic diagram of a semiconductor substrate provided in the fabrication of an exemplary three-dimensional memory structure of the present invention.
FIG. 3 is a schematic illustration of the formation of pregroove in the fabrication of an exemplary three-dimensional memory structure according to the present invention.
FIG. 4 is a schematic diagram illustrating formation of a bottom compensation structure in the fabrication of an exemplary three-dimensional memory structure in accordance with the present invention.
Fig. 5 is a schematic diagram illustrating formation of a stacked structure in the fabrication of an exemplary three-dimensional memory structure according to the present invention.
Fig. 6 is a schematic diagram illustrating formation of a virtual channel hole structure in the fabrication of an exemplary three-dimensional memory structure according to the present invention.
FIG. 7 is a schematic diagram illustrating formation of a stress buffering structure in the fabrication of an exemplary three-dimensional memory structure according to the present invention.
Fig. 8 is a top view of a gate line dividing groove formed in the fabrication of an exemplary three-dimensional memory structure according to the present invention.
FIG. 9 is a top view of a gate line split trench, stress buffering structure, and bottom compensation structure fit in the fabrication of an exemplary three-dimensional memory structure according to the present invention.
FIG. 10 is a schematic cross-sectional view of a gate line dividing groove formed in the fabrication of an exemplary three-dimensional memory structure according to the present invention.
FIG. 11 is a schematic diagram of an exemplary three-dimensional memory structure of the present invention further formed with a channel structure.
FIG. 12 (a) shows the interface between the gate line dividing groove and the stress buffering structure in an example according to an aspect of the present invention; fig. 12 (b) shows that sharp corners are formed between the gate line dividing grooves and the stress buffering structure when the silicon substrate is directly used.
Description of element reference numerals
100. Semiconductor substrate
100a pre-groove
100b bottom compensation structure
101. Laminated structure
102. Dielectric layer
103. Sacrificial layer
104. Virtual channel hole structure
105. Stress buffering structure
106. Grid line dividing groove
106a extension
107. Functional sidewall layer
108. Channel layer
109. Insulating filling layer
110. Air cavity
S1 to S7 steps
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. In addition, "between … …" as used in the present invention includes two end points.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
As shown in fig. 1, the present invention provides a method for preparing a three-dimensional memory structure, which includes the following steps:
s1, providing a semiconductor substrate, wherein the semiconductor substrate comprises a step region, and a junction region is defined in the step region;
s2, etching the semiconductor substrate to form a prefabricated groove at a position corresponding to the junction area;
s3, filling the prefabricated groove to form a bottom compensation structure in the prefabricated groove, wherein the upper surface of the bottom compensation structure is flush with the upper surface of the semiconductor substrate;
s4, forming a laminated structure on the semiconductor substrate, wherein the laminated structure at least covers the bottom compensation structure;
s5, etching the laminated structure to form a virtual channel hole structure in the laminated structure, wherein the virtual channel hole structure extends to the semiconductor substrate and has an overlapping area with the bottom compensation structure;
s6, filling the virtual channel hole structure to form a stress buffer structure in the virtual channel hole structure;
and S7, etching the laminated structure to form a grid line dividing groove in the laminated structure, wherein the grid line dividing groove extends to the semiconductor substrate and has an overlapping area with the bottom compensation structure, and an interface is arranged between the grid line dividing groove and the stress buffer structure and is positioned in an area corresponding to the bottom compensation structure.
The method for fabricating the three-dimensional memory structure of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the preparation sequence of the preparation method of the three-dimensional memory structure protected by the present invention, and those skilled in the art may choose to perform the steps according to the conventional method in the art, and fig. 1 only shows the preparation steps of the preparation method of the three-dimensional memory structure in one example.
First, as shown in S1 in fig. 1 and fig. 2, step S1 is performed to provide a semiconductor substrate 100, where the semiconductor substrate 100 includes a step region (SS) having a junction region defined therein, and the step region may be a step region commonly found in an existing three-dimensional memory structure, so as to electrically draw out a device structure of the device region in the region.
Specifically, the semiconductor substrate 100 includes, but is not limited to, a silicon substrate. The semiconductor substrate 100 may include a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, or the like, and may be selected according to actual requirements of a device, and in other embodiments, the semiconductor substrate 100 may be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, silicon carbide, or the like, and the semiconductor substrate 100 may be a stacked structure, such as a Silicon/Germanium Silicon stack, or the like. As an example, the semiconductor substrate 100 may be, for example, a monocrystalline silicon wafer. In addition, the semiconductor substrate may be a substrate after ion doping, and may be P-type doped or N-type doped.
Where a three-dimensional memory device will typically include one or more chip (plane) memory areas. Symmetric step connection regions for the extraction gates are typically provided on both sides of the chip storage region. Generally, the Step connection region has a Step (SS) shape, and a plurality of connection through holes are provided on the Step region to realize electrical extraction. Word line driving (3D NAND WL center drive) can be implemented based thereon. The slice memory area and the step connection area are typically divided into a plurality of blocks (blocks) to form a plurality of Block memory areas. The steps of the connecting area can be further divided into a plurality of subareas so as to reduce the manufacturing difficulty of the steps.
In an example, the step region (SS) is disposed in the middle of the core region (GB), but the core region may be disposed around the step region. In addition, a bridge region (such as W Wall) is further disposed in the step region, and the bridge region is used to connect the core regions separated by the step region to reduce the difficulty of metal connection path (routing) and connect the metal layer (metal layer). In the above structure, the block is separated by using the gate line dividing groove (gate Cut) on the side structure (sidewall), and the feature size (GLC CD) of the gate line dividing groove on the side structure of the sidewall is greatly changed due to the stress of the dielectric layer (such as TEOS), so that the two blocks can be separated by the Dummy CH, DCH and connected with the gate line dividing groove, thereby effectively reducing the change of the feature size of the gate line dividing groove in the step region.
In an example, as shown in fig. 2, an interface region is defined in the semiconductor substrate 100 to enable connection of a subsequent gate line dividing Groove (GLC) and a dummy channel hole structure (DHC) to improve a joint connected therebetween.
Next, as shown in S2 in fig. 1 and fig. 3, step S2 is performed to etch the semiconductor substrate 100, so as to form a pre-groove 100a at a position corresponding to the interface region. In one example, the pre-groove 100a may be formed by using a photolithography-etching process, which corresponds to forming an auxiliary structure in the semiconductor substrate 100 in advance.
In an example, the shape of the pre-groove 100a may be rectangular, trapezoidal, inverted trapezoidal, etc., and may be selected according to actual processes. In another example, the depth of the pregroove 100a may be the same as the depth of the GLC and DCH, alternatively the pregroove 100a has a depth between 140-180nm, e.g. 150nm, 160nm. The width of the groove 100a is greater than the length of the interface between the GLC and the DCH, so as to wrap the place where the GLC and the DCH meet from top to bottom), optionally, can be performed based on a mask of the existing memory manufacturing process, so as to save the cost.
Next, as shown in S3 in fig. 1 and fig. 4, step S3 is performed to fill the pre-groove 100a, so as to form a bottom compensation structure 100b in the pre-groove 100a, where the upper surface of the bottom compensation structure 100b is flush with the upper surface of the semiconductor substrate 100, so as to facilitate the formation of a subsequent material layer.
The bottom compensation structure 100b is prefabricated in the semiconductor substrate 100, so that the problem of sharp corners of the subsequent gate line dividing Grooves (GLC) is effectively avoided based on the bottom compensation structure 100b, and meanwhile, the process window of combining the gate line dividing Grooves (GLC) with the virtual channel hole structure (DCH) can be effectively increased based on the sharp corners.
As an example, it is preferable that the bottom compensating structure 100b fills the pre-groove 100a. Materials of the bottom supplemental structure 100b include, but are not limited to, silicon oxide SiO2, TEOS.
Next, as shown in S4 and fig. 5 in fig. 1, step S4 is performed to form a stacked structure 101 on the semiconductor substrate 100, where the stacked structure covers at least the bottom compensation structure. In an example, the stacked structure 101 includes sacrificial layers 103 and dielectric layers 102 alternately stacked in a direction perpendicular to a surface of the semiconductor substrate 100.
Specifically, the material of the dielectric layer 102 includes, but is not limited to, silicon oxide, TEOS, and the material of the sacrificial layer 103 includes, but is not limited to, silicon nitride. Optionally, the dielectric layer and the sacrificial layer have a certain selection ratio in the same etching/corrosion process, so as to ensure that the dielectric layer is hardly removed when the sacrificial layer is removed. The stacked structure 101 may be formed by a physical vapor deposition (Physical Vapor Deposition, PVD) process, a chemical vapor deposition (Chemical Vapor Deposition, CVD) process, an atomic layer deposition (Atomic Layer Deposition, ALD) process, or the like. The number of dielectric layers and the number of sacrificial layers in the laminated structure may include 32 layers, 64 layers, 96 layers, 128 layers, or the like, and the number of dielectric layers and the number of sacrificial layers and the thickness thereof may be set according to actual needs, which is not limited herein.
In addition, a channel structure is formed in the stacked structure 101, and as an effective device, as shown in fig. 11, the channel structure is located in the core region, and the related structure is only shown in the figure, and does not strictly represent the positional relationship. The channel structure comprises a laminated material layer formed in a channel hole, wherein the functional side wall layer 107, the channel layer 108 and the insulating filling layer 109 are sequentially arranged from outside to inside. In one example, the functional sidewall layer 107 includes a silicon oxide, silicon nitride, silicon oxide layer arranged from the inner wall surface of the trench hole toward the center, forming an ONO sidewall structure. The material of the insulating fill 109 includes, but is not limited to, silicon oxide. In addition, an air cavity 110 is formed in the insulating filling layer 109 to facilitate stress buffering.
Next, as shown in S5 in fig. 1 and fig. 6, step S5 is performed to etch the laminated structure 101 to form a virtual channel hole structure (DCH) 104 in the laminated structure 101, where in an example, the shape of the virtual channel hole structure 104 may be elongated, which is beneficial to improving the CD variation of the GLC, and of course, may be circular, that is, may be referred to as a top view in fig. 8, and in the top view, the shape of the virtual channel hole structure 104 may be elongated or circular, and of course, may also include structures with both shapes, and the virtual channel hole structure 104 extends to the semiconductor substrate 100 and has an overlapping area with the bottom compensation structure 100b. Overlapping here may mean that the dummy channel hole structure 104 is formed at the surface of the bottom compensation structure 100b, and may extend further into the bottom compensation structure 100b.
Specifically, based on the above arrangement, the dummy channel hole structure 104 is not the material of the semiconductor substrate 100 but the material of the bottom compensation structure 100b when being etched to the bottom of the stacked structure 101 in the etching process, that is, the dummy channel hole structure 104 exposes the bottom compensation structure 100b after the etching is completed.
Wherein in one example, the dummy channel hole structure 104 is selected to extend through the stacked structure 101 to a predetermined distance into the bottom compensation structure 100b and not to exceed the height of the bottom compensation structure 100b.
Next, as shown in S6 in fig. 1 and fig. 7, step S6 is performed to fill the dummy channel hole structure 104, so as to form a stress buffer structure 105 in the dummy channel hole structure 104. The stress buffer structure 105 fills the virtual channel hole structure 104, so that the virtual channel hole structure can be effectively supported, and the problem of non-uniform Characteristic Dimension (CD) of the gate line dividing groove can be effectively improved based on the connection of the stress buffer structure 105 and the subsequent gate line dividing groove.
In one example, the stress buffer structure 105 fills the dummy channel hole structure 104. At this time, the stress buffering structure 105 is formed on the material layer surface of the bottom supplemental structure 100b. In an example, the dummy channel hole structure 104 extends into the bottom compensation structure 100b, and the inner wall of the recess of the bottom compensation structure 100b and the side wall of the stacked structure 101 form the inner wall of the dummy channel hole structure 104.
In one example, the material of the bottom compensation structure 100b is the same as the material of the stress buffering structure 105. For example, the materials of both are selected to be silicon oxide SiO2, so that on one hand, uniformity of the overall structure can be improved, and on the other hand, based on the above arrangement, the stress buffer structure 105 can be made not to be affected by the material of the semiconductor substrate 100 (the material different from the stress buffer structure) in the process of forming. In one example, the material of the stress buffer structure 105 comprises silicon oxide, and the manner in which the silicon oxide is formed comprises a photoresist protection oxide (RPO) manner.
Finally, as shown in S7 of fig. 1 and fig. 8-10, step S7 is performed to etch the stacked structure 101 to form a gate line dividing groove 106 in the stacked structure 101, wherein the gate line dividing groove 106 extends to the semiconductor substrate 100 and has an overlapping region with the bottom compensation structure 100b. Wherein fig. 8 shows a top view after forming the gate line dividing grooves 106; FIG. 9 is a top view of an example gate line dividing groove, stress buffering structure and bottom compensation structure configuration; FIG. 10 is a schematic cross-sectional view of the position A-A' of FIG. 8.
An interface (for example, a star line area 200 in the figure) is formed between the gate line dividing groove 106 and the stress buffering structure 105, and the interface is located in an area corresponding to the bottom compensation structure 100b. Here, the interface may refer to the formation of the gate line dividing groove 106 to the interface of the stress buffering structure 105 and the bottom supplemental structure 100b, such as the interface of the vertical corner formed between the stress buffering structure 105 and the bottom supplemental structure 100b, where the interface of the gate line dividing groove 106 and the stress buffering structure 105 is formed. Of course, in other examples, the material layer may be filled in the gate line dividing grooves 106 according to actual requirements in a subsequent process, such as filling silicon oxide, etc.
When the etching of the gate line dividing groove 106 is performed on the semiconductor substrate, if the semiconductor substrate silicon material layer is directly etched, the upper layer is the laminated structure, and when the etching is performed on the semiconductor substrate silicon, the stress buffer structure 105 is externally provided with an oxide layer, so that the problem that the gate line dividing groove 106 has a sharp angle occurs in the region.
By the design of the present invention, when the bottom complementary structure 100b is formed in the semiconductor substrate 100 in advance, and the gate line dividing groove 106 is etched to the semiconductor substrate, the bottom complementary structure 100b is prefabricated, and the stress buffer structure 105 is formed by oxidizing the dummy channel hole structure 104 after etching, and the material of the bottom complementary structure 100b is not affected by the formation of the stress buffer structure 105 due to the material selection of the stress buffer structure 105 and the bottom complementary structure 100b, for example, the stress buffer structure 105 and the bottom complementary structure 100b are both selected to be silicon oxide, siO2 is surrounding when the photoresist protection oxidation is performed after the dummy channel hole structure 104 is etched, the bottom complementary structure 100b is not affected by RPO, and the problem that the silicon is affected by RPO is avoided. Therefore, when the gate line dividing grooves 106 are etched, silicon oxide is etched in the area, and the problem of sharp corners can be effectively avoided. In addition, a combination window (window) of the gate line dividing groove 106 and the stress buffering structure 105 may be enlarged based on the bottom supplemental structure 100b. In addition, as shown in fig. 12, fig. 12 (a) shows an electron microscope image at the joint between the GLC large-head structure and the DCH large-head structure according to the scheme of the present invention, and fig. 12 (b) shows an electron microscope image at the joint between the silicon oxide DCH large-head structure 2 and the grid line dividing groove 1 after the stacked structure is directly formed on the semiconductor silicon substrate, it can be seen that the problem of sharp angles according to the scheme of the present invention is effectively improved, and the problem of sharp angles is significantly present in the prefabricated bottom compensation structure.
As an example, the bottom layer in the stacked structure 101 is the dielectric layer 102, that is, the dielectric layer 102 contacts the surface of the semiconductor substrate 100, thereby further facilitating the improvement of the sharp corner problem.
As an example, the step region includes a bridge region (not shown) and a step connection region (not shown), the stress buffer structure is located in the bridge region, and the gate line dividing groove is located in the step connection region and extends to the bridge region.
As an example, as shown in fig. 9, the gate line dividing groove 106 includes an extension portion 106a extending into the stress buffering structure 105, and the stress buffering structure 105 surrounds the extension portion 106a.
Further, in an example, the extending direction of the gate line dividing groove 106 is defined as a first direction X1, a direction perpendicular to the first direction X1 is defined as a second direction Y1, and a direction parallel to and opposite to the first direction X1 is defined as a third direction X2, wherein the second direction dimension of the gate line dividing groove increases stepwise along the first direction X1, and the second direction dimension of the stress buffering structure increases stepwise along the third direction X2.
In addition, the present invention further provides a three-dimensional memory structure, which is preferably prepared by the preparation method of the present invention, and of course, may also be prepared by other methods, wherein the characteristics and the related descriptions of each material layer in the three-dimensional memory structure may refer to the descriptions in the preparation method, and are not repeated herein. The three-dimensional memory structure includes:
a semiconductor substrate 100 comprising a step region, wherein the step region defines a junction region;
a pre-groove 100a and a bottom compensation structure 100b, wherein the pre-groove 100a is formed in the semiconductor substrate 100 corresponding to the interface region, the bottom compensation structure 100b is formed in the pre-groove 100a, and the upper surface of the bottom compensation structure 100b is flush with the upper surface of the semiconductor substrate 100;
a stacked structure 101 formed on the semiconductor substrate 100 and covering the pre-groove 100a;
a dummy channel hole structure 104 and a stress buffer structure 105, the dummy channel hole structure 104 being formed in the stacked structure 101 and extending to the semiconductor substrate 100 and having an overlapping region with the bottom compensation structure 100b, the stress buffer structure 105 being filled in the dummy channel hole structure 104;
and a gate line dividing groove 106 formed in the stacked structure 101, wherein the gate line dividing groove 106 extends to the semiconductor substrate 100 and has an overlapping region with the bottom compensation structure 100b, and an interface is formed between the gate line dividing groove 106 and the virtual channel hole structure 104, and the interface is located in a region corresponding to the bottom compensation structure 100b.
As an example, the material of the bottom compensation structure 100b is the same as the material of the stress buffering structure 105; the materials of the stress buffer structure 105 each comprise silicon oxide.
As an example, the stacked structure 101 includes sacrificial layers 103 and dielectric layers 102 stacked alternately, wherein the dielectric layers 102 are in contact with the surface of the semiconductor substrate 100.
As an example, the step region includes a bridge region where the stress buffer structure 105 is located and a step connection region adjacent to the bridge region where the gate line dividing groove 106 is located.
As an example, the gate line dividing groove 106 includes an extension portion 106a extending into the stress buffering structure 105, and the stress buffering structure 105 surrounds the extension portion.
As an example, the extending direction of the gate line dividing groove 106 is defined as a first direction X1, a direction perpendicular to the first direction X1 is defined as a second direction Y1, and a direction parallel and opposite to the first direction X1 is defined as a third direction X2, wherein the second direction dimension of the gate line dividing groove increases stepwise along the first direction X1, and the second direction dimension of the stress buffering structure increases stepwise along the third direction X2.
In summary, according to the three-dimensional memory structure and the preparation method thereof, the bottom compensation structure is manufactured in advance at the junction of the gate line dividing Groove (GLC) and the virtual channel hole structure (DCH), so that the problem of sharp corners of the gate line dividing groove can be effectively avoided, and in addition, the process window for combining the gate line dividing groove with the virtual channel hole structure can be further increased based on the bottom compensation structure. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (13)
1. A method of fabricating a three-dimensional memory structure, the method comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a step region, and a junction region is defined in the step region;
etching the semiconductor substrate to form a prefabricated groove at a position corresponding to the junction area;
filling the pre-formed groove to form a bottom compensation structure in the pre-formed groove, wherein the upper surface of the bottom compensation structure is level with the upper surface of the semiconductor substrate;
forming a laminated structure on the semiconductor substrate, wherein the laminated structure at least covers the bottom compensation structure;
etching the laminated structure to form a virtual channel hole structure in the laminated structure, wherein the virtual channel hole structure extends to the semiconductor substrate and has an overlapping region with the bottom compensation structure;
filling the virtual channel hole structure to form a stress buffer structure in the virtual channel hole structure;
and etching the laminated structure to form a grid line dividing groove in the laminated structure, wherein the grid line dividing groove extends to the semiconductor substrate and has an overlapping area with the bottom compensation structure, and an interface is arranged between the grid line dividing groove and the stress buffer structure and is positioned in an area corresponding to the bottom compensation structure.
2. The method of claim 1, wherein the material of the bottom compensation structure is the same as the material of the stress buffer structure.
3. The method of claim 2, wherein the material of the stress buffer structure comprises silicon oxide, and the manner of forming the silicon oxide comprises a photoresist protection oxidation process.
4. The method of claim 1, wherein the stacked structure comprises alternating sacrificial layers and dielectric layers, wherein the dielectric layers are in contact with the semiconductor substrate surface.
5. The method of claim 1, wherein the step region comprises a bridge region and a step connection region adjacent to the bridge region, the stress buffer structure is located in the bridge region, and the gate line dividing groove is located in the step connection region and extends to the bridge region.
6. The method of any of claims 1-5, wherein the gate line split trench includes an extension that extends into the stress buffer structure, the stress buffer structure surrounding the extension.
7. The method of manufacturing a three-dimensional memory structure according to claim 6, wherein an extending direction of the gate line dividing groove is defined as a first direction, a direction perpendicular to the first direction is defined as a second direction, and a direction parallel opposite to the first direction is defined as a third direction, wherein a second direction dimension of the gate line dividing groove increases stepwise along the first direction, and a second direction dimension of the stress buffering structure increases stepwise along the third direction.
8. A three-dimensional memory structure, the three-dimensional memory structure comprising:
a semiconductor substrate comprising a step region having a junction region defined therein;
the semiconductor device comprises a semiconductor substrate, a junction area, a pre-groove and a bottom compensation structure, wherein the pre-groove is formed in the semiconductor substrate corresponding to the junction area, the bottom compensation structure is formed in the pre-groove, and the upper surface of the bottom compensation structure is flush with the upper surface of the semiconductor substrate;
a stacked structure formed on the semiconductor substrate and covering the pre-groove, the stacked structure covering at least the bottom compensation structure;
a dummy channel hole structure formed in the stacked structure and extending to the semiconductor substrate and having an overlap region with the bottom compensation structure, and a stress buffer structure filled in the dummy channel hole;
and the grid line dividing groove is formed in the laminated structure, extends to the semiconductor substrate and has an overlapping area with the bottom compensation structure, wherein an interface is formed between the grid line dividing groove and the virtual channel hole structure, and the interface is positioned in the area corresponding to the bottom compensation structure.
9. The three-dimensional memory structure of claim 8, wherein a material of said bottom compensation structure is the same as a material of said stress buffer structure; the material of the stress buffering structure comprises silicon oxide.
10. The three-dimensional memory structure of claim 8, wherein the stacked structure comprises alternating sacrificial and dielectric layers, wherein the dielectric layers are in contact with the semiconductor substrate surface.
11. The three-dimensional memory structure of claim 8, wherein the step region comprises a bridge region and a step connection region adjacent to the bridge region, the stress buffering structure is located in the bridge region, and the gate line dividing groove is located in the step connection region and extends to the bridge region.
12. The three-dimensional memory structure of any one of claims 8-11 wherein said gate line segmentation trench comprises an extension into said stress buffer structure, said stress buffer structure surrounding said extension.
13. The three-dimensional memory structure of claim 12, wherein an extending direction of the gate line dividing groove is defined as a first direction, a direction perpendicular to the first direction is defined as a second direction, and a direction parallel opposite to the first direction is defined as a third direction, wherein a second direction dimension of the gate line dividing groove increases stepwise along the first direction, and a second direction dimension of the stress buffering structure increases stepwise along the third direction.
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