CN112067877A - Power semiconductor device for testing gate pole current - Google Patents
Power semiconductor device for testing gate pole current Download PDFInfo
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- CN112067877A CN112067877A CN202010783194.2A CN202010783194A CN112067877A CN 112067877 A CN112067877 A CN 112067877A CN 202010783194 A CN202010783194 A CN 202010783194A CN 112067877 A CN112067877 A CN 112067877A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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Abstract
The invention discloses a power semiconductor device for testing gate current, which comprises a power semiconductor chip and a tube shell, wherein the power semiconductor chip comprises a plurality of first insulating layers and a plurality of sub-gate annular electrodes, the first insulating layers divide a gate public metal area of the power semiconductor chip into a plurality of sub-gate public metal areas, and the plurality of sub-gate public metal areas are respectively connected with the plurality of sub-gate annular electrodes in a one-to-one correspondence manner; the tube shell comprises a plurality of sub-gate electrode contact rings and a plurality of metal rings in sub-insulating bases, and the sub-gate electrode contact rings and the metal rings are arranged in one-to-one correspondence with the plurality of sub-gate electrode annular electrodes; and a plurality of square grooves are arranged on the cathode copper block outside the tube shell gate electrode groove, and gate electrode leading-out strips are arranged in the square grooves to respectively lead out gate electrode currents on the corresponding sub-gate electrode annular electrodes. The power semiconductor device can effectively lead out gate pole currents of different cathode strip-shaped areas in the power semiconductor chip, so that the purpose of measurement is achieved.
Description
Technical Field
The invention belongs to the field of power electronics, and particularly relates to a power semiconductor device for testing gate pole current.
Background
The power semiconductor device mainly comprises a power semiconductor chip, a low-inductance tube shell and a control drive part. The anode copper block and the anode welding ring are welded together to form an anode tube shell in the traditional power semiconductor device, the cathode copper block, the cathode welding ring, the cathode leading-out ring, the lower ceramic, the gate leading-out ring, the upper ceramic and the anode welding ring on the upper ceramic are welded together to form a cathode tube shell, the rest gate components comprise gate disc springs, the metal rings under the insulating seat, the gate insulating seat and the metal rings in the insulating seat are sequentially placed in a gate groove of the cathode tube shell, finally, an inner cathode contact piece, a gate contact ring, an outer cathode contact piece, a power semiconductor chip and an anode contact piece are simultaneously installed in the cathode tube shell, and finally, the anode tube shell is installed and is pressed and connected from the outside by adopting pressure, so that the thyristor chip is in close contact with the.
In key equipment of a direct current power grid, such as a direct current breaker and an alternating current-direct current converter, the maximum turn-off current of a gate integrated converter thyristor is an important application index, the current understanding of the turn-off failure mechanism of the gate integrated converter thyristor is limited by a fully-closed low-inductance shell structure and a chip layout, the gate integrated converter thyristor only stays at a current information level on the periphery of a chip, the current information distribution inside the chip cannot be detected, further, the gate integrated converter thyristor is a schematic diagram of a cathode plane layout of a traditional thyristor chip as shown in fig. 1, and the chip cathode plane layout mainly comprises a cathode strip electrode 52, a gate annular electrode 53, a second insulating layer 55 and a third insulating layer 51. The common gate metal region is arranged below the second insulating layer 55 of the chip and is connected with the gate annular electrode, so that the second insulating layer 55 is mainly used for preventing the gate metal region from contacting with the cathode contact piece when the chip is in compression joint, and the third insulating layer 51 of the chip covers the edge of the chip and is used for protecting the edge terminal of the chip from being polluted. The cathode strip electrodes arranged at intervals in a ring shape in the chip are contacted with the inner cathode contact piece and the outer cathode contact piece in the cathode tube shell, the gate pole ring electrode is contacted with the gate pole contact ring in the cathode tube shell, and the gate pole ring electrode is connected with the common gate pole metal area below the second insulating layer 55 in the chip, so the gate pole current of the chip only has a unique ring leading-out end, and the gate pole current of different cathode strip areas in the thyristor chip cannot be distinguished. Therefore, the traditional power semiconductor device brings great obstruction to further understanding of the failure mechanism of the chip in the traditional power semiconductor device and optimizing the design structure and parameters of the chip due to the limitation of the sealing of the tube shell.
How to provide a power semiconductor device which is convenient for testing the distribution condition of gate current information inside a chip becomes an urgent technical problem to be solved.
Disclosure of Invention
In view of the above problems, the present invention provides a power semiconductor device for testing a gate current, which enables the tested gate current to be more accurate.
The invention aims to provide a power semiconductor device for testing gate current, which comprises a power semiconductor chip and a case,
the power semiconductor chip comprises a plurality of first insulating layers and a plurality of sub-gate annular electrodes, wherein the gate electrode common metal area of the power semiconductor chip is divided into a plurality of sub-gate common metal areas by the first insulating layers, and the plurality of sub-gate common metal areas are respectively connected with the plurality of sub-gate annular electrodes in a one-to-one correspondence manner;
the tube shell comprises a plurality of sub-gate electrode contact rings and a plurality of metal rings in sub-insulating bases, wherein the plurality of sub-gate electrode contact rings and the plurality of metal rings in the sub-insulating bases are arranged in one-to-one correspondence with the plurality of sub-gate electrode annular electrodes;
and a plurality of square grooves are arranged on the cathode copper block outside the tube shell gate electrode groove, and gate electrode leading-out strips are arranged in the square grooves to respectively lead out gate electrode currents on the corresponding sub-gate electrode annular electrodes.
Furthermore, the first end of the gate electrode leading-out strip extends into the gate electrode insulating seat, the upper surface of the first end of the gate electrode leading-out strip is in contact connection with the corresponding sub-gate electrode contact ring, and the lower surface of the first end of the gate electrode leading-out strip is in contact connection with the metal ring in the corresponding sub-insulating seat.
Further, the air conditioner is provided with a fan,
the plurality of sub-gate electrode contact rings are insulated and isolated from the metal rings in the corresponding plurality of sub-insulating seats respectively.
Further, the air conditioner is provided with a fan,
the tube shell also comprises a plurality of sub-gate pole leading-out rings which are provided with leading-out strip terminals, wherein,
the terminal ends of the lead-out strips are connected to the second ends of the corresponding gate lead-out strips.
Further, the air conditioner is provided with a fan,
and a gap with a preset distance is arranged between two adjacent sub-gate pole lead-out rings in the plurality of sub-gate pole lead-out rings to form a lead-out channel of a lead-out strip terminal.
Further, the air conditioner is provided with a fan,
the gate pole leading-out strip terminal is a conductive plate.
Further, the air conditioner is provided with a fan,
the envelope further comprises a plurality of lower ceramics, a plurality of cathode lead-out rings, and a plurality of cathode weld rings, wherein,
the lower ceramics, the cathode lead-out rings and the cathode welding rings are respectively welded with the sub gate lead-out rings correspondingly.
Compared with the traditional power semiconductor device, the power semiconductor device for testing the gate current has the advantages that the gate metal area is divided by the first insulating layer, so that the cathode area of the power semiconductor chip is divided into a plurality of cathode strip-shaped areas, and further, the plurality of sub-gate annular electrodes are respectively connected with the corresponding gate leading-out strips, so that the gate current of different cathode strip-shaped areas in the power semiconductor chip can be effectively led out, and the purpose of measurement is achieved.
In addition, the power semiconductor device for testing the gate current ensures the equivalence of the power semiconductor chip in the working state and does not cause the imbalance of the power density. In addition, the tube shell of the power semiconductor device can still meet the requirements of tube shell stray inductance and maximum current capacity required by chip operation while realizing the gate electrode current partition test function.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 shows a schematic diagram of a cathode plane layout of a conventional thyristor chip;
FIG. 2 is a schematic diagram of a cathode panel of a power semiconductor chip for testing gate current in an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional diagram of a power semiconductor device package for testing gate current in an embodiment of the present invention;
fig. 4 is a schematic cross-sectional view of a power semiconductor device for testing gate current according to an embodiment of the present invention.
Description of the drawings: 1-anode copper block, 2-anode welding ring, 3-anode welding ring, 4-anode contact piece, 5-power semiconductor chip, 6-inner cathode contact piece, 7-outer cathode contact piece, 8-sub-gate contact ring, 9-upper ceramic, 10-sub-gate lead-out ring, 11-lower ceramic, 12-cathode lead-out ring, 13-cathode welding ring, 14-cathode copper block, 15-sub-insulator inner metal ring, 16-gate insulator, 17-gate disc spring, 18-insulator lower metal ring, 51-third insulating layer, 52-cathode strip electrode, 53-gate annular electrode, 54-first insulating layer, 55-second insulating layer and 531-sub-gate annular electrode.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a power semiconductor device for testing gate current, which comprises a power semiconductor chip and a tube shell, wherein the power semiconductor chip comprises a plurality of first insulating layers and a plurality of sub-gate annular electrodes, the first insulating layers divide a gate common metal area of the power semiconductor chip into a plurality of sub-gate common metal areas, and the plurality of sub-gate common metal areas are respectively connected with the plurality of sub-gate annular electrodes in a one-to-one correspondence manner; the tube shell comprises a plurality of sub-gate electrode contact rings and a plurality of metal rings in sub-insulating bases, wherein the plurality of sub-gate electrode contact rings and the plurality of metal rings in the sub-insulating bases are arranged in one-to-one correspondence with the plurality of sub-gate electrode annular electrodes; and a plurality of square grooves are arranged on the cathode copper block outside the tube shell gate electrode groove, and gate electrode leading-out strips are arranged in the square grooves to respectively lead out gate electrode currents on the corresponding sub-gate electrode annular electrodes. Compared with the traditional power semiconductor device, the gate metal area is divided by the first insulating layer, so that the cathode area of the power semiconductor chip is divided into a plurality of cathode strip-shaped areas, and further, the gate ring electrodes are arranged to be respectively connected with the corresponding gate leading-out strips, so that gate currents of different cathode strip-shaped areas in the power semiconductor chip can be effectively led out, and the purpose of measurement is achieved.
Illustratively, as shown in fig. 2, the power semiconductor chip includes 6 first insulating layers 54 and 6 sub-gate ring electrodes 531, wherein the 6 first insulating layers 54 equally divide the gate common metal region of the conventional power semiconductor chip into 6, and at the same time, the gate ring on the conventional power semiconductor chip is equally divided into 6 sub-gate ring electrodes 531, wherein each sub-gate ring electrode 531 is connected to the gate metal region of its corresponding sector region. Thereby introducing the first insulating layer 54 and equally dividing the entire gate ring electrode into 6 sub-gate ring electrodes 531, six independent gate current outlets are realized at the power semiconductor chip level. In the present embodiment, only 6 equal divisions in fig. 2 are taken as an example, but the selection of only 6 equal divisions, 4 equal divisions, 7 equal divisions, etc. is also applicable to the present invention.
In this embodiment, the first end of the gate electrode lead-out strip extends into the gate electrode insulating seat, the upper surface of the first end of the gate electrode lead-out strip is in contact connection with the corresponding sub-gate electrode contact ring, and the lower surface of the first end of the gate electrode lead-out strip is in contact connection with the metal ring in the corresponding sub-insulating seat. The plurality of sub-gate electrode contact rings and the corresponding metal rings in the plurality of sub-insulating seats are respectively insulated and isolated, namely any one of the plurality of sub-gate electrode contact rings is correspondingly provided with the corresponding metal rings in the sub-insulating seats in the plurality of sub-gate electrode contact rings, and the two metal rings are mutually insulated and isolated.
Illustratively, as shown in fig. 3, the example of fig. 3 is based on the example of fig. 2, the number of gate leads is also 6, each gate lead is disposed on a cathode copper block 14 (not shown in fig. 3, and detailed in fig. 4) outside the gate trench of the package, a first end of each gate lead extends into a gate insulator 16, and upper and lower surfaces of each gate lead are in contact with a corresponding sub-gate contact ring 8 and a corresponding sub-insulator inner metal ring 15 (not shown in fig. 3, and detailed in fig. 4), respectively. It should be noted that, in this embodiment, the number of the sub-gate contact rings 8 and the number of the sub-insulating seat inner metal rings 15 are also 6, that is, the gate contact rings and the insulating seat inner metal rings on the conventional power semiconductor device are divided into 6 equal parts, specifically, the number of the sub-gate contact rings 8 after 6 equal parts are respectively No. 1 to No. 6, the number of the sub-gate contact rings 15 in the sub-insulating seat after 6 equal parts are respectively No. 1 to No. 6, the number of the sub-gate contact rings 1 and No. 1, the number of the sub-gate contact rings 2 and No. 2 …, and the number of the sub-gate contact rings 6 and No. 6 are respectively matched with each other, and then the sub-gate contact rings are respectively connected with the 6 gate lead-out bars to form 6 independent lead-out. Further exemplarily, as shown in fig. 3, the package further includes a plurality of sub-gate lead-out rings 10, where the number of the sub-gate lead-out rings 10 is also 6, and the sub-gate lead-out rings 10 divide a gate lead-out ring on a conventional semiconductor device, and each of the sub-gate lead-out rings 10 is provided with a lead-out bar terminal, where the lead-out bar terminal is connected to a second end of a corresponding gate lead-out bar. Thus, with the above arrangement, 6 discrete gate currents can be maintained extending all the way to the tab terminal of the sub-gate lead-out ring.
Fig. 4 shows a schematic cross-sectional view of a structure of a power semiconductor chip and a case matching of a power semiconductor device for testing gate current in an embodiment of the invention, wherein an anode copper block 1 and an anode welding ring 2 are welded together to form an anode case, a cathode copper block 14, a cathode welding ring 13, a cathode lead-out ring 12, a lower ceramic 11, a sub-gate lead-out ring 10, an upper ceramic 9 and an anode welding ring 3 on the upper ceramic are welded together to form a cathode case, the remaining gate components include a gate disc spring 17, a lower metal ring 18 of an insulating base, a gate insulating base 16, and an inner metal ring 15 of the sub-insulating base are sequentially placed in a gate groove of the cathode case, and finally an inner cathode contact piece 6, a sub-gate contact ring 8, an outer cathode contact piece 7, a power semiconductor chip 5, and an anode contact piece 4 are simultaneously installed in the cathode case.
In this embodiment, the gate bar terminal is a conductive plate and is an interface of an external circuit.
In this embodiment, as shown in fig. 3, a gap with a predetermined distance is formed between two adjacent sub-gate lead-out rings 10 in the plurality of sub-gate lead-out rings 10 to form a lead-out channel of a terminal of a lead-out bar. The envelope further includes a plurality of lower ceramics, a plurality of cathode lead-out rings, and a plurality of cathode weld rings, wherein the plurality of lower ceramics 11, the plurality of cathode lead-out rings 12, and the plurality of cathode weld rings 13 are welded to the plurality of sub gate lead-out rings 10, respectively, in correspondence. The lower ceramic 11, the cathode lead-out rings 12 and the cathode welding rings 13 are obtained by cutting the lower ceramic, the cathode lead-out rings and the cathode welding rings which are integrated in the traditional semiconductor device tube shell, so that a power semiconductor chip can be sleeved into a current probe from the outer part of the tube shell through a lead-out channel at 6 lead-out strip terminals to perform gate pole current test in a closed state of a crimping test, and the regional measurement of the gate pole current of the thyristor is finally realized. Further, the lower ceramics 11, the cathode lead-out rings 12, and the cathode welding rings 13 are welded to the sub gate lead-out rings 10 one by one, and the lower ceramics, the cathode lead-out rings, the cathode welding rings, and the sub gate lead-out rings are divided into 6 groups, for example, 6 lower ceramics, cathode lead-out rings, cathode welding rings, and sub gate lead-out rings are provided in each group, and the lower ceramics, the cathode lead-out rings, the cathode welding rings, and the sub gate lead-out rings in each group are welded together.
In this embodiment, the power semiconductor device for testing the gate current may be an IGCT (integrated gate commutated thyristor).
It should be noted that, in this embodiment, the numbers of the "equal divisions" and the equal divisions are exemplary, and the equal divisions may not be adopted in practical application, but the numbers of the plurality of first insulating layers, the plurality of sub-gate annular electrodes, the plurality of sub-gate contact rings, the plurality of sub-insulating base inner metal rings, the plurality of square grooves, the gate lead-out bars, the plurality of sub-gate lead-out rings, the plurality of lower ceramics, the plurality of cathode lead-out rings, and the plurality of cathode welding rings are all the same.
The power semiconductor device for testing the gate current in the embodiment of the invention ensures the equivalence of the power semiconductor chip in the working state and does not cause the imbalance of the power density. The tube shell of the power semiconductor device for testing the gate current can still meet the requirements of tube shell stray inductance and maximum current capacity required by chip operation while realizing the gate current partition test function.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (7)
1. A power semiconductor device for testing gate current, comprising a power semiconductor chip and a package, characterized in that,
the power semiconductor chip comprises a plurality of first insulating layers and a plurality of sub-gate annular electrodes, wherein the gate electrode common metal area of the power semiconductor chip is divided into a plurality of sub-gate common metal areas by the first insulating layers, and the plurality of sub-gate common metal areas are respectively connected with the plurality of sub-gate annular electrodes in a one-to-one correspondence manner;
the tube shell comprises a plurality of sub-gate electrode contact rings and a plurality of metal rings in sub-insulating bases, wherein the plurality of sub-gate electrode contact rings and the plurality of metal rings in the sub-insulating bases are arranged in one-to-one correspondence with the plurality of sub-gate electrode annular electrodes;
and a plurality of square grooves are arranged on the cathode copper block outside the tube shell gate electrode groove, and gate electrode leading-out strips are arranged in the square grooves to respectively lead out gate electrode currents on the corresponding sub-gate electrode annular electrodes.
2. The power semiconductor device for testing gate current according to claim 1, wherein the first end of the gate lead extends into the gate insulator, and wherein the upper surface of the first end of the gate lead is in contact with the corresponding sub-gate contact ring and the lower surface of the first end of the gate lead is in contact with the metal ring in the corresponding sub-insulator.
3. The power semiconductor device for testing gate current according to claim 2,
the plurality of sub-gate electrode contact rings are insulated and isolated from the metal rings in the corresponding plurality of sub-insulating seats respectively.
4. The power semiconductor device for testing gate current of claim 3, wherein said package further comprises a plurality of sub-gate lead-out rings each provided with a lead-out bar terminal, wherein,
the terminal ends of the lead-out strips are connected to the second ends of the corresponding gate lead-out strips.
5. The power semiconductor device for testing gate current according to claim 4, wherein a gap of a predetermined distance is provided between two adjacent ones of the plurality of sub-gate lead-out rings to form a lead-out channel for a terminal of a lead-out bar.
6. A power semiconductor device according to claim 4 or 5, wherein the gate terminal is a conductive plate.
7. The power semiconductor device for testing gate current of claim 6, wherein said package further comprises a plurality of lower ceramics, a plurality of cathode lead rings, and a plurality of cathode weld rings, wherein,
the lower ceramics, the cathode lead-out rings and the cathode welding rings are respectively welded with the sub gate lead-out rings correspondingly.
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