CN112038289A - Array substrate, display panel and manufacturing method of array substrate - Google Patents
Array substrate, display panel and manufacturing method of array substrate Download PDFInfo
- Publication number
- CN112038289A CN112038289A CN202011214667.3A CN202011214667A CN112038289A CN 112038289 A CN112038289 A CN 112038289A CN 202011214667 A CN202011214667 A CN 202011214667A CN 112038289 A CN112038289 A CN 112038289A
- Authority
- CN
- China
- Prior art keywords
- film forming
- layer
- substrate
- array substrate
- depositing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 267
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000010410 layer Substances 0.000 claims abstract description 229
- 239000004065 semiconductor Substances 0.000 claims abstract description 87
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 85
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 84
- 238000000151 deposition Methods 0.000 claims abstract description 77
- 238000000034 method Methods 0.000 claims abstract description 72
- 230000008569 process Effects 0.000 claims abstract description 41
- 230000001681 protective effect Effects 0.000 claims abstract description 30
- 239000011241 protective layer Substances 0.000 claims abstract description 29
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000001301 oxygen Substances 0.000 claims abstract description 14
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 14
- 238000001259 photo etching Methods 0.000 claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 85
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 85
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 55
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 55
- 239000007789 gas Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 239000004973 liquid crystal related substance Substances 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 307
- 239000010409 thin film Substances 0.000 abstract description 37
- 238000001514 detection method Methods 0.000 abstract description 12
- 238000010586 diagram Methods 0.000 description 22
- 239000011521 glass Substances 0.000 description 17
- 238000002161 passivation Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 9
- 230000006866 deterioration Effects 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 7
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000012546 transfer Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000011787 zinc oxide Substances 0.000 description 3
- 239000012459 cleaning agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000012044 organic layer Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910020923 Sn-O Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002052 molecular layer Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N titanium dioxide Inorganic materials O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides an array substrate, a display panel and a manufacturing method of the array substrate. The manufacturing method of the array substrate comprises the following steps: preheating a substrate, wherein a grid electrode and a grid electrode insulating layer are formed in the substrate, and the preheating time of the substrate is 10-50 s; depositing a metal oxide semiconductor layer on a substrate by using a first film forming device; depositing a protective layer on the metal oxide semiconductor layer by using first film forming equipment, and carrying out a photoetching process to form a metal oxide semiconductor pattern and a protective pattern on the substrate; in the step of depositing the protective layer, the content of film forming oxygen in the first film forming equipment is 2% -14%, the film forming power is 20 kW-40 kW, and the film forming pressure is 0.1 MPa-0.7 MPa. The invention can increase the pressure resistance of the thin film transistor device, avoid the conditions of burning and the like of the array substrate in the detection process and improve the yield of the array substrate.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a manufacturing method of the array substrate.
Background
With the development of Display technology, flat panel Display devices such as Liquid Crystal Displays (LCDs) have the advantages of high image quality, power saving, thin body, and no radiation, and are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, and notebook computers, and become the mainstream of Display devices. The liquid crystal display panel generally comprises an array substrate, a color filter substrate and a liquid crystal molecular layer sandwiched between the array substrate and the color filter substrate, which are oppositely arranged.
At present, the preparation process of the array substrate generally comprises six photolithography processes, and the method comprises the following steps: the first step is as follows: depositing a metal layer on a glass substrate, and carrying out first photoetching to form a grid; depositing a grid insulating layer and an Indium Gallium Zinc Oxide (IGZO) semiconductor layer in sequence, and carrying out second photoetching to form a semiconductor pattern; thirdly, depositing a protective layer and carrying out third photoetching to form a protective pattern; fourthly, depositing a source drain metal layer, and carrying out fourth photoetching to form a source electrode and a drain electrode; depositing a passivation layer and a planarization layer, and performing a fifth photolithography process to form a conductive via hole; and sixthly, depositing a transparent conductive film, and carrying out sixth photoetching to form a pixel electrode and a communication pattern of the conductive through hole and the pixel electrode. The method further comprises a step of detecting the substrate by using an electrical detection device in or after the steps, specifically, the electrical detection device applies a preset voltage or current to the substrate to detect whether each parameter of the substrate meets the requirement.
However, under the existing conditions of the array substrate preparation process, the film quality of the protective pattern used as the etching barrier layer is poor, so that the voltage resistance of the thin film transistor device is low and the impedance is low.
Disclosure of Invention
The invention provides an array substrate, a display panel and a manufacturing method of the array substrate, which can increase the pressure resistance of a thin film transistor device, avoid the conditions of burning and the like of the array substrate in the detection process and improve the yield of the array substrate.
The invention provides a manufacturing method of an array substrate, which comprises the following steps:
preheating a substrate, wherein a grid electrode and a grid electrode insulating layer are formed in the substrate, and the preheating time of the substrate is 10-50 s; depositing a metal oxide semiconductor layer on a substrate by using a first film forming device; depositing a protective layer on the metal oxide semiconductor layer by using first film forming equipment, and carrying out a photoetching process to form a metal oxide semiconductor pattern and a protective pattern on the substrate; the first film forming equipment comprises 2-14% of film forming oxygen, 20-40 kW of film forming power and 0.1-0.7 MPa of film forming pressure.
In a possible implementation mode, the preheating time of the substrate base plate is 20 s-40 s, in the step of depositing the protective layer on the metal oxide semiconductor layer, the film forming oxygen content in the first film forming equipment is 5% -13%, the film forming power is 25 kW-35 kW, and the film forming pressure is 0.3 MPa-0.5 MPa.
In one possible implementation manner, after the metal oxide semiconductor pattern and the protection pattern are formed on the substrate, the method further includes:
depositing a source drain metal layer on the substrate with the metal oxide semiconductor pattern and the protection pattern, and carrying out a third photoetching process to form a source electrode and a drain electrode; depositing at least one silicon oxide film layer on the substrate with the source electrode, the drain electrode, the metal oxide semiconductor pattern and the protective pattern by using second film forming equipment; wherein, the silicon oxide film layer close to the substrate base plate is a high-density silicon oxide film layer;
in the step of depositing the high-density silicon oxide film layer, the film forming power of second film forming equipment is 8 kW-16 kW, and SiH introduced into the second film forming equipment4And N2The flow ratio of the O gas is (30-50): 1, the temperature of a film forming chamber in the second film forming equipment is 220-280 ℃.
In a possible implementation mode, in the step of depositing the high-density silicon oxide film layer, the film forming power of the second film forming equipment is 10 kW-14 kW, and SiH introduced into the second film forming equipment4And N2The flow ratio of the O gas is (35-45): 1, the temperature of a film forming chamber in the second film forming equipment is 220-260 ℃.
In one possible implementation manner, at least one silicon oxide film layer is deposited on the substrate base plate on which the source electrode, the drain electrode, the metal oxide semiconductor pattern and the protection pattern are formed, and the method specifically comprises the step of sequentially depositing a high-density silicon oxide film layer and a low-density silicon oxide film layer on the substrate base plate on which the source electrode, the drain electrode, the metal oxide semiconductor pattern and the protection pattern are formed.
In one possible implementation manner, after depositing at least one silicon oxide film layer, the method further includes:
depositing at least one silicon nitride film layer on the at least one silicon oxide film layer by using second film forming equipment;
wherein, at least one layer of silicon nitride film layer comprises a high-density silicon nitride film layer;
in the step of depositing the high-density silicon nitride film layer, the film forming power of second film forming equipment is 8 kW-16 kW, and NH in the second film forming equipment3And SiH4The gas flow ratio of (30-40): 1, the temperature of a film forming chamber in the second film forming equipment is 220-280 ℃.
In a possible implementation manner, in the step of depositing the high-density silicon nitride film layer, the film forming power of the second film forming equipment is 10 kW-14 kW, and NH in the second film forming equipment3And SiH4The gas flow rate ratio of (30-36)): 1, the temperature of a film forming chamber in the second film forming equipment is 220-260 ℃.
In one possible implementation manner, the method further comprises the following steps after the metal oxide semiconductor pattern and the protection pattern are formed on the substrate base plate:
depositing a source drain metal layer on the substrate with the metal oxide semiconductor pattern and the protection pattern, and carrying out a third photoetching process to form a source electrode and a drain electrode;
depositing at least one silicon oxide film layer on the substrate with the source electrode, the drain electrode, the metal oxide semiconductor pattern and the protective pattern by using second film forming equipment; wherein, the silicon oxide film layer close to the substrate base plate is a high-density silicon oxide film layer;
in the step of depositing the high-density silicon oxide film layer, the film forming power of second film forming equipment is 8 kW-16 kW, and SiH introduced into the second film forming equipment4And N2The flow ratio of the O gas is (30-50): 1, the temperature of a film forming chamber in the second film forming equipment is 220-280 ℃.
In a possible implementation mode, in the step of depositing the high-density silicon oxide film layer, the film forming power of the second film forming equipment is 10 kW-14 kW, and SiH introduced into the second film forming equipment4And N2The flow ratio of the O gas is (35-45): 1, the temperature of a film forming chamber in the second film forming equipment is 220-260 ℃.
In one possible implementation mode, at least one silicon oxide film layer is deposited on a substrate with a source electrode, a drain electrode, a metal oxide semiconductor pattern and a protective pattern, and the method specifically comprises the following steps,
and sequentially depositing a high-density silicon oxide film layer and a low-density silicon oxide film layer on the substrate with the source electrode, the drain electrode, the metal oxide semiconductor pattern and the protective pattern.
The second aspect of the present invention provides an array substrate manufactured by the above manufacturing method.
The third aspect of the present invention provides a display panel, which includes a color film substrate, a liquid crystal layer and the array substrate, wherein the liquid crystal layer is sandwiched between the color film substrate and the array substrate.
The embodiment provides an array substrate, a display panel and a manufacturing method of the array substrate. The manufacturing method of the array substrate comprises the following steps: preheating a substrate, wherein a grid electrode and a grid electrode insulating layer are formed in the substrate, and the preheating time of the substrate is 10-50 s; depositing a metal oxide semiconductor layer on a substrate by using a first film forming device; depositing a protective layer on the metal oxide semiconductor layer by using first film forming equipment, and carrying out a photoetching process to form a metal oxide semiconductor pattern and a protective pattern on the substrate; in the step of depositing the protective layer, the content of film forming oxygen in the first film forming equipment is 2% -14%, the film forming power is 20 kW-40 kW, and the film forming pressure is 0.1 MPa-0.7 MPa.
The substrate is preheated for 10 s-50 s before the metal oxide semiconductor layer is deposited, the protective layer is deposited under the conditions that the content of film forming oxygen in first film forming equipment is 2% -14%, the film forming power is 20 kW-40 kW, and the film forming pressure is 0.1 MPa-0.7 MPa, so that the film compactness of the protective layer can be improved, the film stress is reduced, the film quality deterioration risk of a metal oxide semiconductor pattern is reduced, the voltage resistance of a thin film transistor device is improved, the impedance is increased, the electric leakage risk is reduced, the normal work of the device is ensured, the conditions that the array substrate is burnt in the detection process and the like are avoided, and the yield of the array substrate is improved.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without inventive labor.
Fig. 1 is a schematic flow chart illustrating a manufacturing method of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a substrate in an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of the array substrate in a first state in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 4a is a schematic structural diagram of an array substrate in a second state in a manufacturing method of the array substrate according to an embodiment of the invention;
fig. 4b is a schematic structural diagram of another structure of the array substrate in the second state in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 5 is a schematic structural diagram of the array substrate in a third state in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 6 is a schematic structural diagram of another structure of the array substrate in a third state in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 7 is a schematic structural diagram of a structure of the array substrate in a fourth state in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 8 is a schematic structural diagram of another structure of the array substrate in a fourth state in the manufacturing method of the array substrate according to the first embodiment of the present invention;
fig. 9 is a schematic structural diagram of an array substrate with a first structure according to a second embodiment of the present invention;
fig. 10 is a schematic structural diagram of an array substrate with a second structure according to a second embodiment of the present invention;
fig. 11 is a schematic structural diagram of an array substrate with a third structure according to a second embodiment of the present invention;
fig. 12 is a graph showing transfer characteristics of thin film transistors in an array substrate of three structures according to a second embodiment of the present invention and a related art array substrate;
fig. 13 is a graph showing impedance characteristics of the array substrate having three structures according to the second embodiment of the present invention and the thin film transistor in the array substrate of the prior art;
fig. 14 is a graph showing the voltage endurance characteristics of the thin film transistors in the array substrate of the second embodiment of the present invention and the array substrate of the prior art.
Reference numerals:
100. 101, 102, 103-an array substrate; 10-a substrate base plate; 11-a glass substrate; 12-a gate; 13-a gate insulating layer; 14-a metal oxide semiconductor layer; 2-metal oxide semiconductor pattern; 3-protecting the graph; 4-a first protection pattern; 5-a source electrode; 6-a drain electrode; 8-a silicon oxide film layer; 80-a passivation layer; 81-high density silicon oxide film layer; 82-low density silicon oxide film layer; 83-a channel; 91-high density silicon nitride film layer; 92-low density silicon nitride film.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The existing preparation process of the array substrate has the problems that the voltage breakdown resistance of a thin film transistor device is insufficient, and the array substrate is easily burnt and the like due to the influence of voltage of electric detection equipment in an electric detection step in the production process.
The reason is that the metal oxide semiconductor thin film transistor is prepared by adopting a JAS (organic insulating film) -free process in the metal oxide semiconductor in the prior art, and the etching barrier film layer and the insulating film in the array substrate have poor film quality, large stress, more impurity ions and poor insulating property. Therefore, in the preparation process of the array substrate, water vapor, cleaning agent, etching solution and the like are easy to permeate into the oxide semiconductor film layer, so that the film quality of the thin film transistor device is deteriorated, the voltage resistance is smaller and the impedance is lower, and in the subsequent electrical test step, the instantaneous large voltage or instantaneous large current can cause the thin film transistor device to burn, thereby causing poor quality of the array substrate.
According to the invention, the film quality of the protective layer and the passivation layer is improved and the film stress of the film layer is reduced by optimizing the film forming process conditions of the protective pattern and the passivation layer which play a role in etching the barrier film layer, so that the risk of deterioration of the metal oxide semiconductor pattern is reduced, the voltage resistance of the thin film transistor device is improved, the impedance is increased, the electric leakage risk is reduced, the normal work of the device is ensured, the conditions of burning and the like of the array substrate in the detection process are avoided, and the yield of the array substrate is improved.
Example one
Fig. 1 is a schematic flow chart of a manufacturing method of an array substrate according to an embodiment of the present invention, and referring to fig. 1, the manufacturing method of an array substrate according to the embodiment includes:
s10, preheating a substrate, wherein a grid electrode and a grid electrode insulating layer are formed in the substrate, and the preheating time of the substrate is 10-50S.
And S20, depositing a metal oxide semiconductor layer on the substrate base plate by using the first film forming equipment.
S30, depositing a protective layer on the metal oxide semiconductor layer by utilizing first film forming equipment, and carrying out a photoetching process to form a metal oxide semiconductor pattern and a protective pattern on the substrate; the first film forming equipment comprises 2-14% of film forming oxygen, 20-40 kW of film forming power and 0.1-0.7 MPa of film forming pressure.
In the scheme, the substrate is preheated for 10-50 s before the metal oxide semiconductor layer is deposited, the protective layer is deposited under the conditions that the film forming oxygen content in first film forming equipment is 2% -14%, the film forming power is 20 kW-40 kW, and the film forming pressure is 0.1 MPa-0.7 MPa, so that the film compactness of the protective layer can be improved, the film stress is reduced, the film quality deterioration risk of a metal oxide semiconductor pattern is reduced, the voltage resistance of a thin film transistor device is improved, the impedance is increased, the electric leakage risk is reduced, the normal work of the device is ensured, the conditions that the array substrate is burnt in the detection process and the like are avoided, and the yield of the array substrate is improved.
In the embodiment of the present application, in step S10, the substrate is preheated, and after the temperature of the substrate is raised, the metal oxide semiconductor layer and the protective layer are deposited again, so that the adhesion of the metal oxide semiconductor layer and the protective layer to the substrate is better, thereby increasing the compactness of the protective layer, improving the protection of the protective layer to the metal oxide semiconductor pattern, and reducing the risk of deterioration of the film quality of the metal oxide semiconductor pattern.
Wherein the preheating time of the substrate base plate is 10 s-50 s. The preheating time of the substrate is more than or equal to 10s and less than or equal to 50s, so that the protective layer can obtain better compactness, the metal oxide semiconductor layer can be protected better, and the infiltration of external water vapor, cleaning agents and the like can be prevented.
For example, the preheating time of the substrate base plate can be 20 s-40 s.
Specifically, the preheating time of the substrate base plate may be 30 seconds.
Fig. 2 is a schematic structural diagram of a substrate in an array substrate according to an embodiment of the present invention.
Referring to fig. 2, in the embodiment of the present application, a gate electrode 12 and a gate insulating layer 13 are formed in a base substrate 10. Specifically, the substrate 10 may include a glass substrate 11, a gate electrode 12, a gate line (scan line) formed on the glass substrate 11, and a gate insulating layer 13 covering the glass substrate 11, the gate electrode 12, and the gate line.
The method for manufacturing the substrate base plate 10 may include:
depositing a gate metal layer on the glass substrate 11, and performing a photolithography process to form a gate electrode 12 on the glass substrate 11; a gate insulating layer 13 is deposited on the glass substrate 11 on which the gate electrode 12 is formed.
Fig. 3 is a schematic structural diagram of the array substrate in the first state in the manufacturing method of the array substrate according to the first embodiment of the present invention.
In S20, referring to fig. 3, the metal oxide semiconductor layer 14 is deposited on the base substrate 10 using the first film formation apparatus. The metal oxide semiconductor layer may be deposited by a physical vapor deposition method such as sputtering or thermal evaporation. The first film forming apparatus herein may be a physical vapor deposition apparatus, or a magnetron sputtering apparatus or the like.
The metal oxide semiconductor layer 14 may be amorphous IGZO, HIZO, IZO, a-InZnO, or ZnO F, In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2Nb, Cd-Sn-O or other metal oxides.
In the above steps, the process conditions of the first film forming apparatus may adopt the process conditions in the prior art.
Fig. 4a is a schematic structural diagram of the array substrate in the second state in the manufacturing method of the array substrate according to the first embodiment of the present invention. Referring to fig. 4a, in S30, a protective layer is deposited on the metal oxide semiconductor layer 14 using a first film forming apparatus on the basis of the array substrate in the first state shown in fig. 3, and a photolithography process is performed once to form the metal oxide semiconductor pattern 2 and the protective pattern 3 on the base substrate 10.
When the protective layer is deposited, the process conditions of the first film forming equipment are set as follows, the content of film forming oxygen is 2% -14%, the film forming power is 20 kW-40 kW, and the film forming pressure is 0.1 MPa-0.7 MPa. The film layer of the protective layer generated under the condition is compact, the stress of the film layer can be reduced, the film quality deterioration risk of the metal oxide semiconductor pattern 2 is further reduced, the voltage resistance of the thin film transistor device is improved, the impedance is increased, the electric leakage risk is reduced, the normal work of the device is ensured, the conditions that the array substrate 100 is burnt and the like in the detection process are avoided, and the yield of the array substrate 100 is improved.
Illustratively, in the step of depositing the protective layer on the metal oxide semiconductor layer 14, the film forming oxygen content in the first film forming device is 5% to 13%, the film forming power is 25kW to 35kW, and the film forming pressure is 0.3MPa to 0.5 MPa.
Specifically, in the step of depositing the protective layer on the metal oxide semiconductor layer 14, the film formation oxygen content in the first film formation device is 12%, the film formation power is 35kW, and the film formation pressure is 0.5 MPa.
In the embodiment of the present application, the film quality of the protective pattern 3 functioning as an etching stopper is improved, and thus the breakdown resistance of the thin film transistor device can be improved.
After step S30, the source electrode 5, the drain electrode 6, the passivation layer 80, etc. may be formed on the basis of the array substrate in the second state shown in fig. 4a, similarly to the prior art, to form the array substrate 100 in the first structure described in fig. 9, which will not be described again.
In the embodiment of the present application, in addition to the improvement of the film quality of the protective pattern 3 functioning as an etching barrier layer, a scheme of optimizing the film quality of the passivation layer 80 is also included.
For example, fig. 4b is a schematic structural diagram of another structure when the array substrate is in the second state in the manufacturing method of the array substrate according to the first embodiment of the present invention, and the difference between the array substrate in the second state shown in fig. 4b and fig. 4a is that the forming process of the protection patterns of the two are different, and the rest is the same as that in fig. 4 a. In the array substrate of another structure in the second state shown in fig. 4b, the protective layer is formed by a film forming process of the prior art, and the first protective pattern 4 with low density is formed.
After the metal oxide semiconductor pattern 2 and the protective pattern 3 (the first protective pattern 4) are formed, a silicon oxide layer and a silicon nitride layer used as a passivation layer need to be formed, and a process described later may be performed on the basis of the array substrate in the second state shown in fig. 4a or on the basis of the array substrate in the second state shown in fig. 4 b.
Fig. 5 is a schematic structural diagram of the array substrate in a third state in the manufacturing method of the array substrate according to the first embodiment of the present invention.
Referring to fig. 5, the method of the present application further includes: depositing a source-drain metal layer on the substrate 10 (based on the array substrate in the second state shown in fig. 4 a) on which the metal oxide semiconductor pattern 2 and the protection pattern 3 are formed, and performing a third photolithography process to form a source electrode 5 and a drain electrode 6;
and depositing at least one silicon oxide film layer 8 on the substrate base plate 10 formed with the source electrode 5 and the drain electrode 6, the metal oxide semiconductor pattern 2 and the protective pattern 3 by using a second film forming device to form the array base plate in the third state shown in fig. 5, wherein the silicon oxide film layer 8 close to the substrate base plate 10 is a high-density silicon oxide film layer 81.
In the step of depositing the high-density silicon oxide film layer 81, the film forming power of the second film forming equipment is 8 kW-16 kW, and SiH introduced into the second film forming equipment4And N2The flow ratio of the O gas is (30-50): 1, the temperature of a film forming chamber in the second film forming equipment is 220-280 ℃.
Therefore, the silicon oxide film layer close to the substrate base plate 10 can be formed into a high-density film layer, the stress of the film layer can be reduced, the film quality deterioration risk of the metal oxide semiconductor pattern 2 is reduced, the voltage resistance of the thin film transistor device is improved, the impedance is increased, the leakage risk is reduced, the normal work of the device is ensured, the conditions of burning and the like of the array base plate in the detection process are avoided, and the yield of the array base plate is improved.
It should be noted that the highly dense silicon oxide film layer 81 described in this application refers to: the film forming power of the second film forming equipment is 8 kW-16 kW, and SiH introduced into the second film forming equipment4And N2The flow ratio of the O gas is (30-50): 1, depositing the silicon oxide film layer in the second film forming equipment under the condition that the temperature of a film forming cavity is 220-280 ℃.
In the embodiment of the present application, silicon oxide and silicon nitride are deposited by a chemical vapor deposition method, such as a plasma chemical vapor deposition method, and thus the second film forming apparatus may be a chemical vapor deposition apparatus.
In the case where only one highly dense silicon oxide film layer 81 is deposited, the array substrate in the third state as shown in fig. 5 may be formed.
Fig. 6 is a schematic structural diagram of another structure of the array substrate in the third state in the manufacturing method of the array substrate according to the first embodiment of the present invention. Of course, in the case of depositing two silicon oxide film layers 8, an array substrate of another structure of the third state as shown in fig. 6 may be formed.
Specifically, at least one silicon oxide film layer 8 is deposited on a substrate 10 on which a source electrode 5 and a drain electrode 6, a metal oxide semiconductor pattern 2, and a protective pattern 3 are formed, specifically including,
a high-density silicon oxide film layer 81 and a low-density silicon oxide film layer 82 are sequentially deposited on the substrate 10 on which the source electrode 5 and the drain electrode 6, the metal oxide semiconductor pattern 2, and the protective pattern 3 are formed. It is to be understood that the low-density silicon oxide film layer 82 described herein may be a film layer formed using a prior art process. The low-density silicon oxide film layer 82 is such that, with respect to the high-density silicon oxide film layer 81, the density of the low-density silicon oxide film layer 82 is lower than that of the high-density silicon oxide film layer 81.
In the embodiment of the present application, the following process is performed based on the array substrate shown in fig. 6, and the following process performed based on the array substrate shown in fig. 5 is similar to this and is not repeated here.
Illustratively, in the step of depositing the highly dense silicon oxide film layer 81, the film forming power of the second film forming equipment may be 10kW to 14kW, and SiH introduced into the second film forming equipment4And N2The flow ratio of the O gas is (35-45): 1, the temperature of a film forming chamber in the second film forming equipment is 220-260 ℃.
Specifically, in the step of depositing the highly dense silicon oxide film layer 81, the film forming power of the second film forming apparatus may be 10kW, and SiH introduced into the second film forming apparatus4And N2The flow ratio of O gas was 35: 1, the temperature of the film forming chamber in the second film forming apparatus is 230 ℃.
Fig. 7 is a schematic structural diagram of a structure of an array substrate in a fourth state in a manufacturing method of the array substrate according to an embodiment of the present invention, where the method further includes, after depositing at least one silicon oxide film layer 8:
and depositing at least one silicon nitride film layer on at least one silicon oxide film layer 8 by using a second film forming device, namely on the array substrate in the third state shown in fig. 6, so as to form the array substrate in the fourth state shown in fig. 7.
Wherein, at least one layer of silicon nitride film comprises a high-density silicon nitride film 91;
in the high aspect of depositionIn the step of densifying the silicon nitride film layer 91, the film forming power of the second film forming equipment is 8 kW-16 kW, and NH in the second film forming equipment3And SiH4The gas flow ratio of (30-40): 1, the temperature of a film forming chamber in the second film forming equipment is 220-280 ℃.
It is understood that the highly dense silicon nitride film layer 91 described herein refers to: the film forming power of the second film forming equipment is 8 kW-16 kW, and NH in the second film forming equipment3And SiH4The gas flow ratio of (30-40): 1, depositing a silicon nitride film layer in a film forming chamber of the second film forming equipment under the condition that the temperature of the film forming chamber is 220-280 ℃.
Therefore, the silicon nitride film layer on the silicon oxide film layer 8 can be formed into a high-density film layer, the stress of the film layer can be reduced, the film quality deterioration risk of the metal oxide semiconductor pattern 2 is reduced, the voltage resistance of the thin film transistor device is improved, the impedance is increased, the leakage risk is reduced, the normal work of the device is ensured, the conditions of burning and the like of the array substrate in the detection process are avoided, and the yield of the array substrate is improved.
In the case where only one highly dense silicon nitride film layer 91 is deposited, the array substrate in the fourth state as shown in fig. 7 may be formed.
Fig. 8 is a schematic structural diagram of another structure of the array substrate in the fourth state in the manufacturing method of the array substrate according to the first embodiment of the present invention. Of course, in the case of depositing two silicon nitride film layers, an array substrate of another structure of the fourth state as shown in fig. 8 may be formed.
Specifically, depositing at least one silicon nitride film layer on at least one silicon oxide film layer 8 includes,
on the at least one silicon oxide film layer 8, that is, on the array substrate in the third state shown in fig. 6, a low-density silicon nitride film layer 92 and a high-density silicon nitride film layer 91 are sequentially deposited on the low-density silicon oxide film layer 82. It is to be understood that the low-density silicon nitride film 92 described herein may be a film formed using a prior art process. The low-density silicon nitride film layer 92 has a density lower than that of the high-density silicon nitride film layer 91 with respect to the high-density silicon nitride film layer 91.
In the embodiment of the present application, the following process is performed based on the array substrate shown in fig. 8, and the following process performed based on the array substrate shown in fig. 7 is similar to this and is not repeated herein.
Illustratively, in the step of depositing the high-density silicon nitride film layer 91, the film forming power of a second film forming device may be 10kW to 14kW, and NH in the second film forming device3And SiH4The gas flow ratio of (30-36): 1, the temperature of a film forming chamber in the second film forming equipment is 220-260 ℃.
Specifically, in the step of depositing the highly dense silicon nitride film layer 91, the film forming power of the second film forming apparatus may be 12kW, and NH in the second film forming apparatus3And SiH4The gas flow ratio of (2) is 30: 1, the temperature of the film forming chamber in the second film forming apparatus is 230 ℃.
In the embodiment of the present application, after depositing at least one silicon nitride film on at least one silicon oxide film 8, the method further includes:
a photolithography process is performed to form a conductive via (not shown) in the region above the drain 6 on the at least one silicon oxide film layer 8 and the silicon nitride film layer. And a transparent conductive film is deposited on at least one silicon nitride film layer on which the conductive via hole is formed, and a photolithography process is performed to form a pixel electrode (not shown) and electrically connect the pixel electrode with the drain electrode 6 via the conductive via hole.
In the above-described film quality improvement process for the silicon oxide film layer 8 and the silicon nitride film layer, the process described later is performed on the basis of the array substrate in the second state shown in fig. 4a to form the array substrate in the second structure shown in fig. 10, and the process described later is performed on the basis of the array substrate in the second state shown in fig. 4b to form the array substrate in the third structure shown in fig. 11. And will not be described in detail herein.
Example two
Fig. 9 is a schematic structural diagram of an array substrate with a first structure according to a second embodiment of the present invention. Referring to fig. 9, the present invention provides an array substrate 101, and the array substrate 101 is formed by the method for manufacturing an array substrate according to the first embodiment.
Specifically, the array substrate 101 of the present embodiment includes: a glass substrate 11, a gate electrode 12, a gate insulating layer 13, a metal oxide semiconductor pattern 2, a first protection pattern 4, source and drain electrodes 5 and 6, a passivation layer 80, a pixel electrode, and a conductive via. The gate 12 is disposed on the glass substrate 11, the gate insulating layer 13 covers the gate 12 and the glass substrate 11, the metal oxide semiconductor pattern 2 covers part of the gate insulating layer 13 and is located above the gate 12, the first protection pattern 4 covers the metal oxide semiconductor pattern 2, the source 5 and the drain 6 are disposed above the metal oxide semiconductor pattern 2 and the first protection pattern 4, the source 5 and the drain 6 both cover the metal oxide semiconductor pattern 2 at least partially, and the channel 83 is disposed between the source 5 and the drain 6.
The passivation layer 80 covers the gate insulating layer 13 where the source and drain electrodes 5 and 6 are formed. A conductive via is formed on the passivation layer 80 in the region above the drain electrode 6. And a pixel electrode is formed on the passivation layer 80 and electrically connected with the drain electrode 6 via a conductive via.
Fig. 10 is a schematic structural diagram of an array substrate with a second structure according to a second embodiment of the present invention. The method for manufacturing the array substrate shown in fig. 10 is formed by implementing the method for manufacturing the array substrate described above.
Referring to fig. 10, in detail, the array substrate 102 includes: the pixel structure comprises a glass substrate 11, a grid 12, a grid insulating layer 13, a metal oxide semiconductor pattern 2, a protective pattern 3, a source electrode 5, a drain electrode 6, a high-density silicon oxide film layer 81, a low-density silicon oxide film layer 82, a low-density silicon nitride film layer 92, a high-density silicon nitride film layer 91, a pixel electrode and a conductive through hole.
Wherein, the grid 12 is arranged on the glass substrate 11, the grid insulating layer 13 covers the grid 12 and the glass substrate 11, the metal oxide semiconductor pattern 2 covers part of the grid insulating layer 13 and is positioned above the grid 12, the protection pattern 3 covers the metal oxide semiconductor pattern 2, the source electrode 5 and the drain electrode 6 are arranged above the metal oxide semiconductor pattern 2 and the protection pattern 3, the source electrode 5 and the drain electrode 6 both at least partially cover the metal oxide semiconductor pattern 2, and a channel 83 is arranged between the source electrode 5 and the drain electrode 6.
The high-density silicon oxide film layer 81, the low-density silicon oxide film layer 82, the low-density silicon nitride film layer 92 and the high-density silicon nitride film layer 91 sequentially cover the gate insulating layer 13 on which the source electrode 5 and the drain electrode 6 are formed.
And forming conductive through holes in the areas above the drain electrode 6 on the high-density silicon oxide film layer 81, the low-density silicon oxide film layer 82, the low-density silicon nitride film layer 92 and the high-density silicon nitride film layer 91. And a pixel electrode is formed on the highly dense silicon nitride film layer 91, and the pixel electrode is electrically connected to the drain electrode 6 via a conductive via hole.
Fig. 11 is a schematic structural diagram of an array substrate with a third structure according to a second embodiment of the present invention, and the manufacturing method of the array substrate shown in fig. 11 is implemented by the manufacturing method of the array substrate described above.
Referring to fig. 11, in detail, the array substrate 103 includes: the pixel structure comprises a glass substrate 11, a grid 12, a grid insulating layer 13, a metal oxide semiconductor pattern 2, a first protection pattern 4, a source electrode 5, a drain electrode 6, a high-density silicon oxide film layer 81, a low-density silicon oxide film layer 82, a low-density silicon nitride film layer 92, a high-density silicon nitride film layer 91, a pixel electrode and a conductive through hole.
The gate 12 is disposed on the glass substrate 11, the gate insulating layer 13 covers the gate 12 and the glass substrate 11, the metal oxide semiconductor pattern 2 covers part of the gate insulating layer 13 and is located above the gate 12, the first protection pattern 4 covers the metal oxide semiconductor pattern 2, the source 5 and the drain 6 are disposed above the metal oxide semiconductor pattern 2 and the first protection pattern 4, the source 5 and the drain 6 both cover the metal oxide semiconductor pattern 2 at least partially, and the channel 83 is disposed between the source 5 and the drain 6.
The high-density silicon oxide film layer 81, the low-density silicon oxide film layer 82, the low-density silicon nitride film layer 92 and the high-density silicon nitride film layer 91 sequentially cover the gate insulating layer 13 on which the source electrode 5 and the drain electrode 6 are formed.
And forming conductive through holes in the areas above the drain electrode 6 on the high-density silicon oxide film layer 81, the low-density silicon oxide film layer 82, the low-density silicon nitride film layer 92 and the high-density silicon nitride film layer 91. And a pixel electrode is formed on the highly dense silicon nitride film layer 91, and the pixel electrode is electrically connected to the drain electrode 6 via a conductive via hole.
Next, characteristics of the thin film transistors in the array substrate having the first, second, and third structures shown in fig. 9, 10, and 11 are verified and compared with those of the thin film transistors in the array substrate in the related art.
In this embodiment, in the array substrate 101 having the first structure, in the step of depositing the first protective layer on the metal oxide semiconductor layer, the film formation oxygen content in the first film formation device is 12%, the film formation power is 35kW, and the film formation pressure is 0.5 MPa.
In the array substrate 102 with the second structure, in the step of depositing the first protective layer on the metal oxide semiconductor layer, the film forming oxygen content in the first film forming device is 12%, the film forming power is 35kW, and the film forming pressure is 0.5 MPa; in the step of depositing the highly dense silicon oxide film layer 81, the film forming power of the second film forming apparatus may be 10kW, and SiH introduced into the second film forming apparatus4And N2The flow ratio of O gas was 35: 1, the temperature of a film forming cavity in second film forming equipment is 230 ℃; in the step of depositing the highly dense silicon nitride film 91, the film forming power of the second film forming apparatus may be 12kW, and NH in the second film forming apparatus3And SiH4The gas flow ratio of (2) is 30: 1, the temperature of the film forming chamber in the second film forming apparatus is 230 ℃.
In the array substrate 103 with the third structure, in the step of depositing the highly dense silicon oxide film layer 81, the film forming power of the second film forming apparatus may be 10kW, and SiH introduced into the second film forming apparatus4And N2The flow ratio of O gas was 35: 1, the temperature of a film forming cavity in second film forming equipment is 230 ℃; in the step of depositing the highly dense silicon nitride film 91, the film forming power of the second film forming apparatus may be 12kW, and NH in the second film forming apparatus3And SiH4The gas flow ratio of (2) is 30: 1, the firstThe temperature of the film forming chamber in the two film forming apparatuses was 230 ℃.
Fig. 12 is a graph showing transfer characteristics of thin film transistors in an array substrate of three structures according to a second embodiment of the present invention and an array substrate of the related art, fig. 13 is a graph showing impedance characteristics of thin film transistors in an array substrate of three structures according to a second embodiment of the present invention and an array substrate of the related art, and fig. 14 is a graph showing withstand voltage characteristics of thin film transistors in an array substrate of three structures according to a second embodiment of the present invention and an array substrate of the related art.
Refer to the transfer characteristic graph of fig. 12. The transfer characteristic curve is a curve that the source-drain current Id changes along with the gate voltage Vg under a certain source-drain voltage, and the thin film transistor device in the prior art is conducted, so that the thin film transistor is easy to burn and lose the electrostatic protection effect. In the array substrate with the first structure, the second structure and the third structure, the Id-Vg transfer characteristic curve of the thin film transistor is good, and the thin film transistor has good characteristics. The non-conduction of the thin film transistor can be realized, and the purpose of electrostatic protection is achieved.
Referring to the impedance characteristic graph shown in fig. 13, in the array substrate of the prior art, the first structure, the second structure, and the third structure, the impedances of the thin film transistors are respectively: 3.37E +04 Ω, 2.54E +05 Ω, 1.05E +06 Ω, 3.80E +05 Ω, it can be seen that the thin film transistors of the second, third, and first structures all have better impedance performance, which is much higher than the impedance of the prior art. The risk of electric leakage of the thin film transistor device in operation can be effectively prevented. And the thin film transistor with high impedance can effectively resist impurity ions in the insulating film and the air, and has stronger electrostatic protection effect.
Referring to the voltage characteristic graph shown in fig. 14, in the array substrate of the prior art, the first structure, the second structure, and the third structure, the voltage withstand voltages of the thin film transistors are respectively: the voltage endurance of the thin film transistors of the second structure, the third structure and the first structure is better and much higher than that of the prior art, namely 20V, 40V, more than 100V and 56V. The voltage endurance of the thin film transistor is improved from 20V to more than 100V. The voltage breakdown resistance of the thin film transistor can be remarkably improved, the thin film transistor is not easily influenced by instantaneous large voltage or instantaneous large current, the burn of the thin film transistor device can be avoided, and the yield of the array substrate is improved.
EXAMPLE III
The present embodiment provides a display panel, which includes the array substrate 101, the array substrate 102, and the array substrate 103 in the second embodiment, wherein the specific structure and function of the array substrate have been described in detail in the second embodiment, and thus are not described herein again.
The display panel may be a liquid crystal display panel, and at this time, the display panel includes a color film substrate, a liquid crystal layer, and the array substrate according to the second embodiment, where the liquid crystal layer is sandwiched between the color film substrate and the array substrate.
The display panel may also be an organic light emitting diode display panel, and in this case, the display panel includes the array substrate, the encapsulation layer, and the organic layer described in the second embodiment, where the organic layer is sandwiched between the array substrate and the encapsulation layer.
Another aspect of this embodiment further provides a display device, including the display panel, where the display device may be a flexible display device, and in this embodiment, the display device may be an electronic paper, a tablet computer, or a liquid crystal display.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (13)
1. A manufacturing method of an array substrate is characterized by comprising the following steps:
preheating a substrate, wherein a grid electrode and a grid electrode insulating layer are formed in the substrate, and the preheating time of the substrate is 10-50 s;
depositing a metal oxide semiconductor layer on a substrate by using a first film forming device;
depositing a protective layer on the metal oxide semiconductor layer by using the first film forming equipment, and carrying out a photoetching process to form a metal oxide semiconductor pattern and a protective pattern on the substrate; in the step of depositing the protective layer on the metal oxide semiconductor layer, the content of film forming oxygen in the first film forming equipment is 2% -14%, the film forming power is 20 kW-40 kW, and the film forming pressure is 0.1 MPa-0.7 MPa.
2. The method of claim 1, wherein the step of forming the array substrate comprises forming a first metal layer on the substrate,
the preheating time of the substrate base plate is 20 s-40 s,
in the step of depositing the protective layer on the metal oxide semiconductor layer, the film forming oxygen content in the first film forming equipment is 5% -13%, the film forming power is 25 kW-35 kW, and the film forming pressure is 0.3 MPa-0.5 MPa.
3. The method of claim 1, wherein the step of forming the array substrate comprises forming a first metal layer on the substrate,
the method also comprises the following steps after the metal oxide semiconductor pattern and the protective pattern are formed on the substrate base plate:
depositing a source drain metal layer on the substrate with the metal oxide semiconductor pattern and the protection pattern, and carrying out a third photoetching process to form a source electrode and a drain electrode;
depositing at least one silicon oxide film layer on the substrate with the source electrode, the drain electrode, the metal oxide semiconductor pattern and the protective pattern by using second film forming equipment; wherein, the silicon oxide film layer close to the substrate base plate is a high-density silicon oxide film layer;
wherein in the step of depositing the high-density silicon oxide film layer, the film forming power of the second film forming equipment is 8 kW-16 kW, and the second film forming equipment is internally provided with the filmIntroduced SiH4And N2The flow ratio of the O gas is (30-50): 1, the temperature of a film forming chamber in the second film forming equipment is 220-280 ℃.
4. The method for manufacturing an array substrate according to claim 3,
in the step of depositing the high-density silicon oxide film layer, the film forming power of the second film forming equipment is 10 kW-14 kW, and SiH introduced into the second film forming equipment4And N2The flow ratio of the O gas is (35-45): 1, the temperature of a film forming chamber in the second film forming equipment is 220-260 ℃.
5. The method for manufacturing an array substrate according to claim 3,
depositing at least one silicon oxide film layer on the substrate with the source electrode, the drain electrode, the metal oxide semiconductor pattern and the protective pattern, specifically comprising the following steps,
and sequentially depositing a high-density silicon oxide film layer and a low-density silicon oxide film layer on the substrate with the source electrode, the drain electrode, the metal oxide semiconductor pattern and the protective pattern.
6. The method for manufacturing an array substrate according to any one of claims 3 to 5,
the method also comprises the following steps after the deposition of at least one silicon oxide film layer:
depositing at least one silicon nitride film layer on at least one silicon oxide film layer by using second film forming equipment;
wherein at least one layer of silicon nitride film comprises a high-density silicon nitride film;
in the step of depositing the high-density silicon nitride film layer, the film forming power of the second film forming equipment is 8 kW-16 kW, and NH in the second film forming equipment3And SiH4The gas flow ratio of (30-40): 1, the temperature of a film forming chamber in the second film forming equipment is 220-280 ℃.
7. The method of claim 6, wherein the step of forming the array substrate comprises forming a first metal layer on the substrate,
in the step of depositing the high-density silicon nitride film layer, the film forming power of the second film forming equipment is 10 kW-14 kW, and NH in the second film forming equipment3And SiH4The gas flow ratio of (30-36): 1, the temperature of a film forming chamber in the second film forming equipment is 220-260 ℃.
8. The method of claim 6, wherein the step of forming the array substrate comprises forming a first metal layer on the substrate,
the depositing at least one silicon nitride film layer on at least one silicon oxide film layer by using the second film forming equipment specifically comprises,
and sequentially depositing a low-density silicon nitride film layer and a high-density silicon nitride film layer on at least one silicon oxide film layer.
9. The method of claim 2, wherein the step of forming the array substrate comprises forming a first metal layer on the substrate,
the method also comprises the following steps after the metal oxide semiconductor pattern and the protective pattern are formed on the substrate base plate:
depositing a source drain metal layer on the substrate with the metal oxide semiconductor pattern and the protection pattern, and carrying out a third photoetching process to form a source electrode and a drain electrode;
depositing at least one silicon oxide film layer on the substrate with the source electrode, the drain electrode, the metal oxide semiconductor pattern and the protective pattern by using second film forming equipment; wherein, the silicon oxide film layer close to the substrate base plate is a high-density silicon oxide film layer;
wherein in the step of depositing the high-density silicon oxide film layer, the film forming power of the second film forming equipment is 8 kW-16 kW, and SiH introduced into the second film forming equipment4And N2The flow ratio of the O gas is (30-50): 1, the temperature of a film forming chamber in the second film forming equipment is 220-280 ℃.
10. The method of claim 9, wherein the step of forming the array substrate comprises forming a first metal layer on the substrate,
in the step of depositing the high-density silicon oxide film layer, the film forming power of the second film forming equipment is 10 kW-14 kW, and SiH introduced into the second film forming equipment4And N2The flow ratio of the O gas is (35-45): 1, the temperature of a film forming chamber in the second film forming equipment is 220-260 ℃.
11. The method of claim 9, wherein the step of forming the array substrate comprises forming a first metal layer on the substrate,
depositing at least one silicon oxide film layer on the substrate with the source electrode, the drain electrode, the metal oxide semiconductor pattern and the protective pattern, specifically comprising the following steps,
and sequentially depositing a high-density silicon oxide film layer and a low-density silicon oxide film layer on the substrate with the source electrode, the drain electrode, the metal oxide semiconductor pattern and the protective pattern.
12. An array substrate manufactured by the method for manufacturing an array substrate according to any one of claims 1 to 11.
13. A display panel, comprising a color filter substrate, a liquid crystal layer and the array substrate of claim 12, wherein the liquid crystal layer is sandwiched between the color filter substrate and the array substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011214667.3A CN112038289B (en) | 2020-11-04 | 2020-11-04 | Array substrate, display panel and manufacturing method of array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011214667.3A CN112038289B (en) | 2020-11-04 | 2020-11-04 | Array substrate, display panel and manufacturing method of array substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112038289A true CN112038289A (en) | 2020-12-04 |
| CN112038289B CN112038289B (en) | 2021-02-02 |
Family
ID=73573145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011214667.3A Active CN112038289B (en) | 2020-11-04 | 2020-11-04 | Array substrate, display panel and manufacturing method of array substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112038289B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114141881A (en) * | 2021-11-24 | 2022-03-04 | 深圳市华星光电半导体显示技术有限公司 | Drive substrate and display panel |
| WO2022267043A1 (en) * | 2021-06-25 | 2022-12-29 | 京东方科技集团股份有限公司 | Oxide thin-film transistor and preparation method therefor, and display device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070264843A1 (en) * | 2006-05-09 | 2007-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation and applications of nitrogen-free silicon carbide in semiconductor manufacturing |
| CN102709189A (en) * | 2012-05-21 | 2012-10-03 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method of thin film transistor, and array substrate |
| US20120248470A1 (en) * | 2004-07-30 | 2012-10-04 | Semiconductor Energy Laboratory Co., Ltd. | Display device and method for manufacturing the same |
| CN202957251U (en) * | 2012-12-13 | 2013-05-29 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and display device |
| CN105702587A (en) * | 2010-04-23 | 2016-06-22 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor device |
| CN107408579A (en) * | 2015-03-03 | 2017-11-28 | 株式会社半导体能源研究所 | Semiconductor device, the manufacture method of the semiconductor device or the display device including the semiconductor device |
| CN107978560A (en) * | 2017-11-21 | 2018-05-01 | 深圳市华星光电半导体显示技术有限公司 | Carry on the back channel etch type TFT substrate and preparation method thereof |
| CN108258021A (en) * | 2018-01-22 | 2018-07-06 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), preparation method, array substrate and display device |
-
2020
- 2020-11-04 CN CN202011214667.3A patent/CN112038289B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120248470A1 (en) * | 2004-07-30 | 2012-10-04 | Semiconductor Energy Laboratory Co., Ltd. | Display device and method for manufacturing the same |
| US20070264843A1 (en) * | 2006-05-09 | 2007-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation and applications of nitrogen-free silicon carbide in semiconductor manufacturing |
| CN105702587A (en) * | 2010-04-23 | 2016-06-22 | 株式会社半导体能源研究所 | Method for manufacturing semiconductor device |
| CN102709189A (en) * | 2012-05-21 | 2012-10-03 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method of thin film transistor, and array substrate |
| CN202957251U (en) * | 2012-12-13 | 2013-05-29 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and display device |
| CN107408579A (en) * | 2015-03-03 | 2017-11-28 | 株式会社半导体能源研究所 | Semiconductor device, the manufacture method of the semiconductor device or the display device including the semiconductor device |
| CN107978560A (en) * | 2017-11-21 | 2018-05-01 | 深圳市华星光电半导体显示技术有限公司 | Carry on the back channel etch type TFT substrate and preparation method thereof |
| CN108258021A (en) * | 2018-01-22 | 2018-07-06 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), preparation method, array substrate and display device |
Non-Patent Citations (1)
| Title |
|---|
| 王海宏等: "铟镓锌氧化物薄膜晶体管制备及性能研究 ", 《真空科学与技术学报》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022267043A1 (en) * | 2021-06-25 | 2022-12-29 | 京东方科技集团股份有限公司 | Oxide thin-film transistor and preparation method therefor, and display device |
| CN114141881A (en) * | 2021-11-24 | 2022-03-04 | 深圳市华星光电半导体显示技术有限公司 | Drive substrate and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112038289B (en) | 2021-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101627136B1 (en) | Thin film transistor substrate, method of manufacturing the same and display device comprising the same | |
| KR101158896B1 (en) | Substrate having thin film transistor and method for making the substrate, and liquid crystal display panel and electro luminescence display panel having the transistor | |
| CN102456696B (en) | Display unit and manufacture method thereof | |
| US11335709B2 (en) | Array substrate, display panel, display device and method for forming array substrate | |
| US10186617B2 (en) | Thin film transistor, method of fabricating the same, array substrate and display device | |
| CN112038289B (en) | Array substrate, display panel and manufacturing method of array substrate | |
| KR20080017965A (en) | Method of manufacturing panel for flexible display device | |
| KR20120084133A (en) | Thin film transistor array panel | |
| CN110729313A (en) | Display panel, display panel preparation method and display device | |
| US9553176B2 (en) | Semiconductor device, capacitor, TFT with improved stability of the active layer and method of manufacturing the same | |
| KR20120021602A (en) | Display substrateand method of manufacturing the same | |
| KR101132119B1 (en) | array substrate of liquid crystal display and fabrication method thereof | |
| KR20150050051A (en) | Array substrate for Liquid crystal display device and Method for manufacturing the same | |
| CN212010934U (en) | Array substrate and display panel | |
| CN210723028U (en) | Display panel and display device | |
| CN102723359A (en) | Thin-film transistor, manufacture method of thin-film transistor, array substrate and display device | |
| CN105428423A (en) | Thin film transistor and method of manufacturing the same | |
| CN104752464A (en) | Organic light emitting display and preparation method thereof | |
| CN109728003A (en) | The manufacturing method of display base plate, display device and display base plate | |
| CN111508895B (en) | Array substrate, display panel and manufacturing method of array substrate | |
| CN111403488B (en) | Thin film transistor, preparation method thereof, display substrate and display device | |
| CN111308796A (en) | Display panel and manufacturing method thereof | |
| WO2022148260A1 (en) | Thin-film transistor array substrate and preparation method therefor, and display panel | |
| CN211743124U (en) | Array substrate and display panel | |
| CN108288652B (en) | Thin film transistor, manufacturing method thereof, array substrate and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: No. 1778, Qinglan Road, Huangjia Street, Shuangliu District, Chengdu, Sichuan 610200 Patentee after: Chengdu BOE Display Technology Co.,Ltd. Country or region after: China Address before: No. 1778, Qinglan Road, Gongxing street, Shuangliu District, Chengdu, Sichuan 610200 Patentee before: CHENGDU ZHONGDIAN PANDA DISPLAY TECHNOLOGY Co.,Ltd. Country or region before: China |
|
| CP03 | Change of name, title or address |