CN111308796A

CN111308796A - Display panel and manufacturing method thereof

Info

Publication number: CN111308796A
Application number: CN202010246517.4A
Authority: CN
Inventors: 孙学军; 刘翔; 杨松; 李广圣
Original assignee: Chengdu CEC Panda Display Technology Co Ltd
Current assignee: Chengdu CEC Panda Display Technology Co Ltd
Priority date: 2020-03-31
Filing date: 2020-03-31
Publication date: 2020-06-19

Abstract

The invention provides a display panel and a manufacturing method of the display panel. The display panel includes: the display panel comprises an array substrate, an opposite side substrate and frame glue clamped and attached between the array substrate and the opposite side substrate, wherein the array substrate and the opposite side substrate are arranged oppositely, and the frame glue is arranged between the opposite side substrate and the opposite side substrate in a clamped mode, and/or a concave-convex structure is arranged on the surface, facing the frame glue, of the opposite side substrate and/or the surface, facing the frame glue, of the array substrate. The invention can improve the reliability of the display panel.

Description

Display panel and manufacturing method thereof

Technical Field

The invention relates to the technical field of display, in particular to a display panel and a manufacturing method of the display panel.

Background

With the development of display technology, display panels are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, and notebook computers, and become the mainstream of display devices. In recent years, the demand for display panels has become higher and higher, and the frame of the display panel tends to become narrower.

The display panel, such as a liquid crystal display panel, comprises a first substrate and a second substrate which are oppositely arranged, and liquid crystal and frame glue which are clamped between the first substrate and the second substrate, wherein the frame glue is arranged around the liquid crystal to play a role in preventing the liquid crystal from overflowing and preventing external water vapor from entering the liquid crystal. The display panel comprises a display area and a non-display area arranged on the outer side of the display area in a surrounding mode, and the arrangement position of the frame glue corresponds to the non-display area. At present, for example, narrow-bezel televisions and full-screen mobile phones, the non-display area at the edge of the display panel is narrowed, so that the display area is increased, and the screen occupation ratio is improved. In order to reduce the width of the frame, in addition to reducing the peripheral circuit wiring, another effective method is to reduce the width of the sealant.

However, since the width of the sealant is reduced, the sealant has poor sealing capability against water vapor, and the external water vapor easily enters the liquid crystal through the sealant, thereby reducing the reliability of the display panel.

Disclosure of Invention

The invention provides a display panel and a manufacturing method of the display panel, which improve the sealing capability of frame glue to water vapor, thereby improving the reliability of the display panel.

A first aspect of the present invention provides a display panel comprising: the array substrate and the opposite substrate are oppositely arranged, the frame glue is clamped and attached between the array substrate and the opposite substrate, and a concave-convex structure is arranged on the surface of the opposite substrate facing the frame glue and/or the surface of the array substrate facing the frame glue.

Optionally, the concave-convex structure includes a protrusion disposed on a surface of the opposite substrate facing the sealant; and/or the concave-convex structure comprises a bulge arranged on the surface of the array substrate facing the frame glue.

Optionally, when the concave-convex structure includes a protrusion disposed on a surface of the opposite side substrate facing the sealant, the protrusion on the opposite side substrate is formed by extending at least a part of the structure of the opposite side substrate toward the array substrate.

Optionally, the opposite substrate includes a black matrix, a color resist material and a spacer,

the protrusion on the opposite substrate is formed by extending at least one of the black matrix, the color-resistant material, and the spacer toward the array substrate.

Optionally, when the concave-convex structure comprises a protrusion arranged on the surface of the array substrate facing the frame adhesive,

the protrusion on the array substrate is formed by extending at least partial layer of the array substrate towards the direction of the opposite substrate.

Optionally, the array substrate comprises a gate insulating layer and a passivation layer,

the protrusion on the array substrate is formed by extending the gate insulating layer and/or the passivation layer toward the opposite substrate.

Optionally, the portion of the array substrate located in the display region includes: the anti-oxidation graph comprises a CuNx graph, and the CuNx graph is positioned on the surface, close to the passivation layer, of the source electrode and the drain electrode containing the Cu element;

the grid insulation layer covers the grid, the blocking pattern, the source electrode and the drain electrode containing the Cu element and the anti-oxidation pattern are arranged above the metal oxide semiconductor pattern, projections of the blocking pattern, the source electrode and the drain electrode containing the Cu element and the anti-oxidation pattern on the substrate are overlapped, and a channel region is arranged between the source electrode and the drain electrode.

Optionally, the metal oxide semiconductor pattern includes a first semiconductor pattern and a second semiconductor pattern overlapping each other, and a conductivity of the first semiconductor pattern is higher than a conductivity of the second semiconductor pattern.

A second aspect of the present invention provides a method for manufacturing a display panel, where the display panel includes an array substrate and a counter substrate that are disposed opposite to each other, and a sealant that is sandwiched and attached between the array substrate and the counter substrate, and the method for manufacturing the display panel includes: forming a concave-convex structure on at least one of a surface of the counter substrate facing the array substrate and a surface of the array substrate facing the counter substrate; and frame glue covering the concave-convex structure is arranged between the opposite substrate and the array substrate.

Optionally, the step for forming the array substrate includes:

depositing a grid metal layer on the substrate base plate, and carrying out a first photoetching process to form a grid and a grid line on the substrate base plate;

sequentially depositing a grid insulation layer, a metal oxide semiconductor layer, a blocking layer, a source drain metal layer containing Cu element and a protective layer on a substrate with a grid and a grid line, and carrying out a second photoetching process to form a metal oxide semiconductor pattern on the metal oxide semiconductor layer, form an anti-diffusion pattern between the metal oxide semiconductor pattern and a source electrode and a drain electrode on the blocking layer, form a source electrode and a drain electrode on the source drain metal layer, and form an anti-oxidation pattern above the source electrode and the drain electrode on the protective layer;

alternatively, the step for forming the array substrate includes:

sequentially depositing a gate insulating layer, a metal oxide semiconductor layer, a blocking layer and a source drain metal layer containing a Cu element on a substrate base plate on which a gate and a gate line are formed, and forming an anti-oxidation layer containing a CuNx layer on the source drain metal layer containing the Cu element;

and carrying out a second photoetching process on the metal oxide semiconductor layer, the barrier layer, the source and drain metal layers containing the Cu element and the anti-oxidation layer to enable the metal oxide semiconductor layer to form a metal oxide semiconductor pattern, enable the barrier layer to form an anti-diffusion pattern between the metal oxide semiconductor pattern and the source and drain electrodes, enable the source and drain metal layers containing the Cu element to form the source and drain electrodes and enable the anti-oxidation layer to form the anti-oxidation pattern.

Optionally, the metal oxide semiconductor layer includes a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer has higher conductivity than the second semiconductor layer.

The present embodiment provides a display panel and a manufacturing method of the display panel, wherein the display panel includes: the display panel comprises an array substrate, an opposite side substrate and frame glue clamped and attached between the array substrate and the opposite side substrate, wherein the array substrate and the opposite side substrate are arranged oppositely, and the frame glue is arranged between the opposite side substrate and the opposite side substrate in a clamped mode, and/or a concave-convex structure is arranged on the surface, facing the frame glue, of the opposite side substrate and/or the surface, facing the frame glue, of the array substrate. The area through being equipped with concave-convex structure on array substrate and/or the contralateral substrate is full of the frame gum, when external steam etc. want to get into display panel inside through the boundary position department of frame gum and array substrate and/or contralateral substrate, concave-convex structure's setting is equivalent to the length that has increased the infiltration route of steam, and the width of frame gum is increased in the equivalence promptly to the vapour ability that blocks water of frame gum in the narrow frame display panel has been promoted, and then display panel's reliability has been promoted.

Drawings

In order to more clearly illustrate the technical solutions of the present invention or the prior art, the following briefly introduces the drawings needed for the embodiments or the prior art descriptions, and obviously, the drawings in the following description are some embodiments of the present invention, and those skilled in the art can obtain other drawings according to the drawings without inventive labor.

Fig. 1 is a top view of a display panel according to a first embodiment of the invention;

fig. 2 is a cross-sectional view of a display panel according to an embodiment of the invention;

fig. 3 is a cross-sectional view of another structure of a display panel according to an embodiment of the invention;

fig. 4 is a cross-sectional view of another structure of a display panel according to an embodiment of the invention;

fig. 5 is a schematic structural diagram of a concave-convex structure including a groove in a display panel according to an embodiment of the present invention;

fig. 6 is a schematic diagram of another structure in which the concave-convex structure of the display panel includes grooves according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the invention, in which the concave-convex structure includes a protrusion;

fig. 8 is a schematic diagram of another structure in which the concave-convex structure of the display panel includes protrusions according to an embodiment of the invention;

fig. 9 is a schematic structural diagram of an array substrate in a display panel according to an embodiment of the invention;

fig. 10 is a schematic flowchart illustrating a manufacturing method of a display panel according to a second embodiment of the present invention;

fig. 11 is a schematic structural diagram of a display panel in a first state in a manufacturing method of the display panel according to the second embodiment of the present invention;

fig. 12 is a schematic structural diagram of a display panel in a second state in the manufacturing method of the display panel according to the second embodiment of the present invention;

fig. 13 is a schematic structural diagram of a display panel in a third state in the manufacturing method of the display panel according to the second embodiment of the present invention;

fig. 14 is a schematic structural diagram of a display panel in a fourth state in a manufacturing method of the display panel according to the second embodiment of the present invention;

fig. 15 is a schematic flowchart illustrating a manufacturing method of an array substrate according to a second embodiment of the invention;

fig. 16 is a schematic structural view of the array substrate in a fifth state in the manufacturing method of the array substrate according to the second embodiment of the present invention;

fig. 17 is another schematic structural diagram of the array substrate in a fifth state in the manufacturing method of the array substrate according to the second embodiment of the present invention;

fig. 18 is a schematic structural view of the array substrate in a sixth state in the manufacturing method of the array substrate according to the second embodiment of the present invention;

fig. 19 is another schematic structural diagram of the array substrate in a sixth state in the manufacturing method of the array substrate according to the second embodiment of the present invention;

fig. 20 is a schematic structural view of the array substrate in a seventh state in the manufacturing method of the array substrate according to the second embodiment of the present invention;

fig. 21 is another schematic structural diagram of the array substrate in a seventh state in the manufacturing method of the array substrate according to the second embodiment of the present invention;

fig. 22 is a schematic structural view of the array substrate in an eighth state in the manufacturing method of the array substrate according to the second embodiment of the present invention;

fig. 23 is a schematic structural view of the array substrate in a ninth state in the manufacturing method of the array substrate according to the second embodiment of the present invention;

fig. 24 is a schematic structural view of the array substrate in a tenth state in the manufacturing method of the array substrate according to the second embodiment of the present invention;

fig. 25 is a schematic structural diagram of the array substrate in an eleventh state in the manufacturing method of the array substrate according to the second embodiment of the present invention;

fig. 26 is a schematic structural view of the array substrate in a twelfth state in the manufacturing method of the array substrate according to the second embodiment of the present invention;

fig. 27 is a structural diagram illustrating a final state of the array substrate in the method for manufacturing the array substrate according to the second embodiment of the invention.

Reference numerals:

100-a display panel; 101-a liquid crystal layer; 1-an array substrate; 11-a gate insulating layer; 12-a passivation layer; 13. 25, 81, 60-substrate base plate; 2-a counter substrate; 20-a color film substrate; 21-a spacer; 22-a color-resist material; 23-black matrix; 24-a planarization layer; 3-frame glue; 31-the outer edge of the frame glue; 32-inner edge of frame glue; 41-anti-oxidation pattern; 43-channel region; 5. 51, 52-relief structure; 5' -a metal oxide semiconductor layer; 51' -a first semiconductor pattern; 52' -a second semiconductor pattern; 511. 521-a groove; 512. 522-projection; 53-a first semiconductor layer; 54-a second semiconductor layer; 6-a barrier layer; 6' -a barrier pattern; 761-glass substrate; 62-metal oxide semiconductor pattern; 63-pattern of adhesion layer; 8' -a source drain metal layer containing Cu element; 80-CuNx layers; 80' -CuNx pattern; 81-a protective layer; 81' -protection pattern; 82-a gate; 83-semiconductor active islands; 84-source electrode; 85-drain electrode; 88-scan line; 89-data line; 86-conductive vias; 87-pixel electrodes; 90-a first photoresist pattern; 91-complete photoresist retention area; 92-partial photoresist retention area; 93-complete removal of photoresist region; 94-second photoresist pattern.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example one

Fig. 1 is a top view of a display panel according to a first embodiment of the invention; fig. 2 is a cross-sectional view of a display panel according to an embodiment of the invention. As shown in fig. 1 and 2, the display panel 100 according to the embodiment of the present application includes: the display panel comprises an array substrate 1, an opposite substrate 2 and frame glue 3 which is clamped and attached between the array substrate 1 and the opposite substrate 2, wherein the array substrate and the opposite substrate 2 are oppositely arranged. The surface of the opposite substrate 2 facing the frame glue 3 and/or the surface of the array substrate 1 facing the frame glue 3 are/is provided with a concave-convex structure 5.

In the above scheme, the region that is equipped with concave-convex structure 5 on array substrate 1 and/or the offside substrate 2 is full of frame gum 3, outside steam etc. want to get into display panel 100 inside through frame gum 3 and array substrate 1 and/or offside substrate 2's boundary position department, concave-convex structure 5's setting is equivalent to the length that has increased the infiltration route of steam, the equivalent width that increases frame gum 3 promptly, thereby the vapour-blocking ability of frame gum 3 in the narrow frame display panel has been promoted, and then display panel's reliability has been promoted.

In the embodiment of the present disclosure, the display panel 100 may be, for example, a liquid crystal display panel, the opposite substrate 2 may be a color film substrate 20, a liquid crystal layer 101 and a sealant 3 are interposed between the array substrate 1 and the color film substrate 20, and the sealant 3 surrounds the liquid crystal layer 101.

In other examples, the display panel 100 may also be an oled display panel, the opposite substrate 2 may be an encapsulation layer, the sealant 3 may be a glass encapsulation, for example, the organic layer and the encapsulation are sandwiched between the array substrate 1 and the encapsulation layer, and the encapsulation surrounds the encapsulation layer.

In the following description, the display panel 100 is described as an example of a liquid crystal display panel. In the case where the display panel 100 is an organic light emitting diode display panel, the description thereof is omitted here, similarly to the liquid crystal display panel.

In the embodiment of the present application, as shown in fig. 1 and fig. 2, the display panel 100 includes a display area and a non-display area surrounding the display area, where the display area is denoted by a reference numeral "AA" and the non-display area is denoted by a reference numeral "NAA". The frame sealant 3 is sandwiched between the array substrate 1 and the color filter substrate 20, and is located in a region corresponding to the non-display region, so as to avoid affecting the normal display of the display region.

Referring to fig. 1 and 2, an outer edge 31 and an inner edge 32 of the sealant both correspond to the non-display region NAA of the display panel. An outer edge of the liquid crystal layer may be positioned within the display area AA, or an outer edge of the liquid crystal layer may be positioned within the non-display area NAA, or an outer edge of the liquid crystal layer may be positioned at a boundary position of the display area AA and the non-display area NAA.

The frame glue 3 serves to seal the liquid crystal cell, prevent liquid crystal overflow and water vapor intrusion, maintain the thickness of the peripheral box of the liquid crystal cell, and adhere the array substrate 1 and the color film substrate 20, so that the top end of the frame glue 3 is attached to the lower surface of the color film substrate 20, and the bottom end of the frame glue 3 is attached to the upper surface of the array substrate 1.

The main component of the frame glue 3 is resin, and additives such as heat-cured single crystal resin, phenol resin, epoxy resin which is cross-linked by ultraviolet irradiation, and the like can be added. The sealant 3 is generally classified into a thermosetting type and an ultraviolet curing type according to the kind of the additive.

In the manufacturing process of the display panel 100, generally, the liquid crystal is dropped on the array substrate 1, the liquid sealant 3 is coated on the color filter substrate 20, then the array substrate 1 and the color filter substrate 20 are aligned in a vacuum environment, and finally the liquid sealant 3 is cured by uv curing and thermal curing, so that the array substrate 1 and the color filter substrate 20 are adhered to each other. Since the sealant 3 is coated on the color film substrate 20 in a liquid state and is aligned with the array substrate, even if the sealant 3 of the opposite substrate 2 and/or the sealant 3 of the array substrate 1 has the concave-convex structure 5, the sealant 3 can be well filled between the concave-convex structures 5, thereby achieving better sealing performance.

In the embodiment of the present application, the step of providing the concave-convex structure 5 on the surface of the opposite substrate 2 facing the sealant 3 and/or the surface of the array substrate 1 facing the sealant 3 may include the following three schemes:

as shown in fig. 2, the array substrate 1 has a concave-convex structure 51 on the surface facing the sealant 3, and the opposite substrate 2 (color filter substrate 20) has a concave-convex structure 52 on the surface facing the sealant 3; or,

as shown in the cross-sectional view of another structure of the display panel 100 in fig. 3, only the surface of the array substrate 1 facing the sealant 3 has the concave-convex structure 51, the upper surface of the array substrate 1 is bonded to the sealant 3 through the concave-convex structure 51, and the lower surface of the color filter substrate 20 is directly attached to the sealant 3; or,

as shown in the cross-sectional view of another structure of the display panel 100 in fig. 4, only the surface of the opposite substrate 2 (color filter substrate 20) facing the sealant 3 has the concave-convex structure 52, the upper surface of the array substrate 1 is directly attached to the sealant 3, and the lower surface of the color filter substrate 20 is bonded to the sealant 3 through the concave-convex structure 52.

In the embodiment of the present application, the concave-convex structure 5 may be configured as a ring around the liquid crystal layer 101, for example, as shown in fig. 1 and 4, when the surface of the color film substrate 20 facing the sealant 3 has the concave-convex structure 52, the concave-convex structure 52 is extended along the circumferential direction of the surface of the color film substrate 20 facing the sealant 3, which makes all positions of the sealant 3 in the circumferential range have the effect of lengthening the moisture intrusion path, compared with the scheme of only partially configuring the concave-convex structure 52, so that the sealant 3 has better sealing performance in the entire circumferential range. In addition, optionally, a plurality of, for example, three concave-convex structures 52 are provided on the color filter substrate 20, and the three concave-convex structures 52 are arranged at intervals in a direction from the center of the display panel 100 to the edge of the display panel 100. Therefore, when the water vapor enters the display panel 100 from the outside through the boundary region between the color film substrate 20 and the sealant 3, the water vapor passes through the concave-convex structure 52 three times continuously no matter where the water vapor enters, so that the water vapor passes through a longer path as much as possible.

As another alternative, as shown in fig. 1 and 3, when the surface of the array substrate 1 facing the sealant 3 has the concave-convex structure 51, the concave-convex structure 51 extends along the circumferential direction of the surface of the array substrate 1 facing the sealant 3, which makes the sealant 3 have a longer vapor invasion path at all positions in the circumferential range and makes the sealant 3 have better sealing performance in the entire circumferential range compared to the case where the concave-convex structure 51 is only partially provided. In addition, optionally, a plurality of, for example, three concave-convex structures 51 are provided on the array substrate 1, and the three concave-convex structures 51 are arranged at intervals in a direction from the center of the display panel 100 to the edge of the display panel 100. Therefore, when the water vapor enters the display panel 100 from the outside through the boundary area between the array substrate 1 and the frame glue 3, the water vapor passes through the concave-convex structure 51 three times continuously no matter where the water vapor enters, so that the passing path of the water vapor is as long as possible.

In the embodiment of the present application, as shown in fig. 2, when the surface of the color filter substrate 20 facing the sealant 3 and the surface of the array substrate 1 facing the sealant 3 both have the concave-convex structure 5, the concave-convex structure 52 on the opposite substrate 2 and the concave-convex structure 51 on the array substrate 1 are vertically disposed opposite to each other. Specifically, when the color filter substrate 20 is coated with the frame glue 3, after the array substrate 1 and the color filter substrate 20 are vacuum-sealed, the structure in which the concave-convex structure 52 on the color filter substrate 20 and the concave-convex structure 51 on the array substrate 1 are vertically arranged in a relative manner is beneficial to the contact between the top end of the frame glue 3 and the concave-convex structure 51 on the array substrate 1.

In the embodiment of the present application, the concave-convex structure 5 may be a protrusion or a groove. Fig. 5 is a schematic diagram illustrating a structure of a concave-convex structure of a display panel according to a first embodiment of the present invention, and fig. 6 is a schematic diagram illustrating another structure of a concave-convex structure of a display panel according to a first embodiment of the present invention, as shown in fig. 5, as an alternative embodiment, the concave-convex structure includes a groove 511 disposed on a surface of the array substrate 1 facing the sealant 3. The groove 511 may be formed by a photolithography process. For example, the array substrate 1 includes a substrate 13, a gate insulating layer 11, and a passivation layer 12, which are sequentially stacked, wherein the passivation layer 12 is closest to the liquid crystal layer 101. The groove 511 may be formed on the passivation layer 12, for example, in the same photolithography process as a conductive via (not shown) formed on the passivation layer 12, so that the groove 511 may be formed without adding an additional process, and the cost may be reduced as much as possible, wherein a transparent conductive layer may be deposited in the conductive via for electrically connecting the pixel electrode and the drain electrode.

Alternatively, the groove 511 may also be opened on both the passivation layer 12 and the gate insulating layer 11, i.e. the groove 511 may extend onto the gate insulating layer 11. The opening position of the groove 511 can be located in the non-display area NAA to avoid affecting the normal display of the display area.

In addition, a groove structure can be formed at a position corresponding to the frame adhesive 3 on the array substrate 1 by forming the groove 511 on the array substrate 1, so as to lengthen an intrusion path of the water vapor, wherein the groove 511 can be designed according to requirements, the number of the grooves can be in a range of 1 to 10, for example, 2 to 3, and the width of the groove 511 is between 0.05 mm and 0.8mm, and further, 0.05 mm and 0.1 mm. The depth of the groove 511 may be determined by the thicknesses of the gate insulating layer 11 and the passivation layer 12, where

In the meantime.

As shown in fig. 6, as another alternative embodiment, the concave-convex structure includes a groove 521 disposed on a surface of the opposite substrate 2 facing the sealant 3, and the groove 521 may be formed by a photolithography process. The color filter substrate 20 includes a substrate base 25, color-resisting materials 22 and a black matrix 23 disposed on the substrate base 25, and the color-resisting materials 22 are disposed at intervals by the black matrix 23, and a planarization layer 24 covers the color-resisting materials 22 and the black matrix 23, wherein the planarization layer 24 is closest to the liquid crystal layer 101. A recess 521 may be opened in the planarization layer 24.

Alternatively, the groove 521 may be opened on both the planarization layer 24 and the black matrix 23, that is, the groove 521 may extend to the black matrix 23. The opening position of the groove 521 can be located in the non-display area NAA to avoid affecting the normal display of the display area.

In addition, a groove structure can be formed at a position, corresponding to the frame adhesive 3, on the color film substrate 20 by forming the groove 521 on the color film substrate 20, so that an intrusion path of water vapor is lengthened, the groove 521 can be designed as required, the number of the grooves can be in a range of 1 to 10, for example, 2 to 3, the width of the groove 521 is between 0.05 mm and 0.8mm, and further, the width of the groove 521 can be 0.05 mm to 0.1 mm. The depth of the recess 521 may be determined by the thickness of the planarization layer 24 and the black matrix 23

In the meantime.

It can be understood that the groove 511 may also be disposed on the array substrate 1, and the groove 521 may also be disposed on the color filter substrate 20, so that the groove 511 and the groove 521 are opposite in the vertical direction of the display panel 100. So that the sealing effect of the frame glue 3 is better.

In this embodiment, the concave-convex structure 5 may also include a protrusion, specifically, as shown in fig. 7, the protrusion 512 may be formed on the array substrate 1 and formed by extending at least part of layers of the array substrate 1 toward the color filter substrate 20. For example, the protrusion 512 on the array substrate 1 is formed by extending the gate insulating layer 11 and/or the passivation layer 12 toward the color filter substrate 20.

Specifically, the concave-convex structure 5 may include a protrusion 512 disposed on a surface of the array substrate 1 facing the sealant 3. The protrusion 512 may be formed by a photolithography process, and the opening position of the protrusion 512 may be located in the non-display area NAA to avoid affecting the normal display of the display area. In addition, the bump 512 may be formed by the passivation layer 12, and since the bump 512 is formed in the same process as the passivation layer 12, an additional process is not required to be added, so that the cost can be reduced as much as possible.

It is understood that the protrusion 512 may also be formed by the gate insulating layer 11, and in this case, a relief space, such as a relief hole, needs to be formed on the passivation layer 12 so as to expose the protrusion 512 formed by the gate insulating layer 11. In the process of forming the protrusion 512, the protrusion 512 and the gate insulating layer 11 may be formed in the same photolithography process, and the corresponding relief space on the passivation layer 12 and the conductive via on the passivation layer 12 may be formed in the same photolithography process, so that additional processes are not required to form the protrusion 512, and the cost can be reduced as much as possible.

Or, the protrusion 512 may be formed by both the gate insulating layer 11 and the passivation layer 12, and in the forming process of the protrusion 512, a part of the structure of the protrusion 512 may be formed in the same photolithography process as the gate insulating layer 11, and another part of the structure may be formed in the same photolithography process as the passivation layer 12, so that no additional process is required to form the protrusion 512, and the cost can be reduced as much as possible.

It can be understood that the groove structure can be formed at the position corresponding to the frame adhesive 3 on the array substrate 1 by forming the protrusions 512 on the array substrate 1, so as to lengthen the intrusion path of the water vapor, where the protrusions 512 can be designed according to the requirement, the number of the protrusions 512 can be in the range of 1-10, for example, 2-3, and the distance between the protrusions 512 is 0.05-0.8 mm, and further, can be 0.05-0.1 mm. The height of the bump 512 may be determined by the thickness of the gate insulating layer 11 and the passivation layer 12, where

In the meantime.

In this embodiment, as shown in fig. 8, the concave-convex structure may further include protrusions 522 disposed on a surface of the opposite substrate 2 (the color filter substrate 20) facing the sealant 3. The bumps 522 on the color filter substrate 20 are formed by extending at least a part of the structure of the color filter substrate 20 toward the array substrate 1. For example, the protrusion on the color filter substrate 20 is formed by extending at least one of the black matrix 23, the color resist 22, and the spacer 21 toward the array substrate 1.

Optionally, the protrusion 522 may be formed by a photolithography process, and the opening position of the protrusion 522 may be located in the non-display area NAA, so as to avoid affecting the normal display of the display area.

Referring to fig. 8, as an alternative embodiment, the protrusion 522 may be formed by the spacer 21, and since the protrusion 522 is formed in the same process as the spacer 21, no additional process is required to form the protrusion 522, so that the cost can be reduced as much as possible.

It is understood that in other examples, the protrusion 522 may be formed by the black matrix 23 and/or the color-resisting material 22, and an avoiding space, such as an avoiding hole, needs to be provided on the planarization layer 24 to expose the protrusion 522 formed by the black matrix 23 and/or the color-resisting material 22. In the process of forming the protrusion 522, the protrusion 522 may be formed in the same photolithography process as the black matrix 23 and/or the color resistance material 22, so that the protrusion 522 may be formed without adding an additional process, and the cost may be reduced as much as possible.

Alternatively, the protrusion 522 may be formed by any two of the spacer 21, the black matrix 23, and the color resist material 22, and in the process of forming the protrusion 522, each layer structure of the protrusion 522 may be formed in the same photolithography process as any two of the spacer 21, the black matrix 23, and the color resist material 22, so that the protrusion 522 is formed without adding an additional process, and the cost can be reduced as much as possible.

Alternatively, the protrusion 522 may be formed of three components, that is, the spacer 21, the black matrix 23, and the color resist material 22, and in the process of forming the protrusion 522, each layer structure of the protrusion 522 may be formed in the same photolithography process as the spacer 21, the black matrix 23, and the color resist material 22, so that an additional process is not required to form the protrusion 522, and the cost can be reduced as much as possible.

It can be understood that a groove structure can be formed at a position corresponding to the frame adhesive 3 on the color film substrate 20 by forming the protrusions 522 on the color film substrate 20, so that an intrusion path of water vapor is lengthened, the protrusions 522 here can be designed as required, the number of the protrusions 522 can be in a range of 1 to 10, for example, 2 to 3, and the distance between the protrusions 522 is 0.05 to 0.8mm, and further, can be 0.05 to 0.1 mm. The height of the protrusion 522 may be determined by the thickness of the color-resist material 22, the black matrix 23, or the spacer 21

In the meantime.

In the embodiment of the present application, in the area of the array substrate corresponding to the display area, in the case that the metal of the source electrode 84 and the metal of the drain electrode 85 include copper, it may be considered to provide a protective layer for the source electrode 84 and the drain electrode 85 to prevent the source electrode 84 and the drain electrode 85 from being oxidized by SiOx in the passivation layer 12.

Fig. 9 is a schematic structural diagram of an array substrate in a display panel according to an embodiment of the invention; as shown in fig. 9, a portion of the array substrate 1 corresponding to the display area AA includes: the semiconductor device comprises a substrate base plate 60, and a grid 82, a grid insulating layer 11, a metal oxide semiconductor pattern 62 (namely a semiconductor active island 83), a barrier pattern 6', a source 84 and a drain 85 containing Cu element, an anti-oxidation pattern 41 and a passivation layer 12 which are sequentially arranged on the substrate base plate 60, wherein the anti-oxidation pattern 41 comprises a CuNx pattern 80', and the CuNx pattern 80' is positioned on the surface, close to the passivation layer 12, of the source 84 and the drain 85 containing Cu element.

The gate insulating layer 11 covers the gate 82, the barrier pattern 6', the source 84 and the drain 85 containing Cu elements, and the oxidation preventing pattern 41 are disposed above the metal oxide semiconductor pattern 62, the projections of the barrier pattern 6', the source 84 and the drain 85 containing Cu elements, and the oxidation preventing pattern 41 on the substrate 60 are overlapped, a channel region is formed between the source 84 and the drain 85, and a conductive via 86 is formed in the display region AA.

In the non-display area NAA, a groove 511 is formed in the passivation layer 12.

Wherein, the groove 511 is ring-shaped and arranged around the center of the display panel, the number of the grooves is 1-10, further 2-3, the width of the groove 511 is 0.05-0.8 mm, the depth of the groove 511 is determined by the thickness of the passivation layer 12, the groove 511 is arranged on the passivation layer 12

In the meantime.

In the above-described embodiment, the oxidation preventing pattern 41 including the CuNx pattern 80' is formed on the surface of the source and drain

electrodes

84 and 85 close to the passivation layer 12, so that when SiOx is contained in the passivation layer 12 on the surface of the source and drain

electrodes

84 and 85, the CuNx can protect the source and drain

electrodes

84 and 85 and prevent the source and drain

electrodes

84 and 85 from being oxidized by the passivation layer 12 containing SiOx, thereby preventing the source and drain

electrodes

84 and 85 from being peeled off and improving the reliability of the array substrate 1.

Specifically, the substrate base plate 60 in the present application may be directly the glass base plate 61, and the gate electrode 82 is directly deposited on the substrate base plate 60. In other examples, for example, in the case where the gate 82 includes Cu element, the substrate base plate 60 may also include a glass base plate 61 and an adhesion layer (adhesion layer pattern 63) deposited on the glass base plate 61, the adhesion layer being disposed adjacent to the gate 82 and serving to increase adhesion of the gate 82 and the substrate base plate 60. The gate electrode 82 can also be prevented from peeling off to some extent due to the increased adhesion between the gate electrode 82 and the glass substrate 61.

In the embodiment of the present application, the material of the adhesion layer may include at least one of Cr (chromium element), W (tungsten element), Ti (titanium element), Ta (tantalum element), Mo (molybdenum element), for example, the adhesion layer may be Mo alloy, Ti alloy, etc., and the thickness of the adhesion layer is about the same

Mainly for increasing the adhesion of Cu in the gate 82 and the base substrate 60.

In the embodiment of the present application, the gate 82 may include Cu, and the thickness of the gate 82 is aboutIs composed of

The gate insulating layer 11 may be an oxide, nitride or oxynitride, and the corresponding reaction gas may be SiH₄、NH₃、N₂Or SiH₂Cl₂、NH₃、N₂。

In addition, the metal oxide semiconductor pattern 62 may be amorphous IGZO, and the metal oxide semiconductor pattern 62 may be formed using amorphous IGZO, HIZO, IZO, a-InZnO, ZnO: F, In₂O₃:Sn、In₂O₃:Mo、Cd₂SnO₄、 ZnO:Al、TiO₂Nb, Cd-Sn-O or other metal oxides.

Optionally, the barrier pattern 6' has a thickness of

In addition, the material of the barrier pattern 6 'may include at least one of Cr, W, Ti, Ta, and Mo, for example, the barrier pattern 6' may also be a Mo alloy, a Ti alloy, or the like. The barrier pattern 6' serves as a diffusion preventing layer for Cu elements in the source electrode 84 and the drain electrode 85, so that Cu elements in the source electrode 84 and the drain electrode 85 can be prevented from diffusing into the metal oxide semiconductor pattern 62, and at the same time, the adhesion between Cu elements in the source electrode 84 and the drain electrode 85 and the metal oxide semiconductor pattern 62 can be increased, and the occurrence of peeling of the source electrode 84 and the drain electrode 85 can be reduced.

In addition, the source electrode 84 and the drain electrode 85 may both contain a Cu element, or one of them may contain a Cu element. For example, the source 84 and drain 85 may be of a thickness

Further, in order to prevent the Cu element in the source and drain

electrodes

84 and 85 from being oxidized, a CuNx pattern 80' may be formed on the surfaces of the source and drain

electrodes

84 and 85 adjacent to the passivation layer 12.

The CuNx pattern 80' may be formed by surface-treating the surfaces of the source and drain

electrodes

84 and 85. The plasma gas used in the surface treatment process may be N₂Plasma body,Or may be NH₃Or is H₂It is understood that the material layer formed on the surface of the source electrode 84 or the drain electrode 85 is different when the surface is treated with different gases.

In addition, the surface treatment described above may be carried out using different equipment, for example, N in a dry etching apparatus₂CuNx is generated by plasma treatment, the corresponding radio frequency power is 15 KW-35 KW, the air pressure is 100 mT-1500 mT, and the flow of gas is 600-2500 sccm; n in PECVD (plasma enhanced chemical vapor deposition) equipment₂CuNx is generated by plasma processing, the corresponding radio frequency power is 7 KW-20 KW, the air pressure is 800 mT-1500 mT, and the flow of the gas is 8000-40000 sccm.

In addition, alternatively, the thickness of the CuNx pattern 80 'may be less than the thickness of the barrier pattern 6'. By making the CuNx pattern 80' thinner, it is advantageous for the source 84 and drain 85 to be well patterned during etching.

In the embodiment of the present application, the thickness of the passivation layer 12 is

The passivation layer 12 may be an oxide, a nitride, or an oxynitride, and may be a single layer or a multi-layer, and the reaction gas corresponding to the silicon oxide may be SiH₄，N₂O; nitride or oxynitride corresponding to SiH as the gas₄、NH₃、N₂Or SiH₂Cl₂、NH₃、N₂. It is understood that in the prior art, the passivation layer 12 is usually made of silicon nitride, and the characteristics of the metal oxide thin film transistor are sensitive to nitrogen, which may even cause the metal oxide thin film transistor to lose its characteristics. Therefore, at least the portion of the passivation layer 12 in contact with the TFT channel region needs to be an oxide of silicon to improve the stability of the TFT.

In addition, a pixel electrode 87 is further provided on the passivation layer 12, and the thickness of the pixel electrode 87 is set to

The pixel electrode 87 mayThe transparent conductive film may be indium tin oxide ITO or indium zinc oxide IZO, or other transparent metal oxides, as the transparent conductive film.

For the above layers, the gate insulating layer 11 covers the entire layer of the base substrate 60 and covers the gate 82, and the barrier pattern 6', the source and drain

electrodes

84 and 85 containing Cu, and the oxidation preventing pattern 41 are provided above the metal oxide semiconductor pattern 62. The barrier pattern 6 'is overlapped with the projections of the source electrode 84 and the drain electrode 85 containing Cu element on the substrate 60, specifically, the barrier pattern 6' and the source electrode 84 and the drain electrode 85 can be etched and formed simultaneously in the same process, and the channel region between the source electrode 84 and the drain electrode 85 exposes a part of the metal oxide semiconductor pattern 62 and contacts the passivation layer 12.

In the embodiment of the present application, the metal oxide semiconductor pattern 62 includes, but is not limited to, one layer, and may be formed of two layers. For example, in the TFT device using the back channel etching, in order to prevent the metal oxide semiconductor pattern 62 from being damaged by an etching medium in an etching process of the source electrode 84 and the drain electrode 85, the metal oxide semiconductor pattern 62 may include a first semiconductor pattern 51 'and a second semiconductor pattern 52' overlapping each other, and the first semiconductor pattern 51 'has a higher conductivity than the second semiconductor pattern 52'.

By making the metal oxide semiconductor pattern 62 include the first semiconductor pattern 51' with higher conductivity and the second semiconductor pattern 52' with lower conductivity, the second semiconductor pattern 52' with lower conductivity is directly in contact with the source-drain metal layer, so that the contact resistance between the metal oxide semiconductor pattern 62 and the source and drain

electrodes

84 and 85 can be reduced, and the on-state current of the metal oxide thin film transistor can be increased; the first semiconductor pattern 51' having a higher conductivity is in direct contact with the gate insulating layer 11 to form a channel of the thin film transistor, so that the performance of the thin film transistor can be more stable.

In the above scheme, optionally, the thickness of the first semiconductor pattern 51' may be

Thickness of the second semiconductor pattern 52Can also be

For the control of the conductivity of each semiconductor pattern, it may be controlled according to the oxygen content in the semiconductor pattern, for example, the oxygen content of the second semiconductor pattern 52 'may be lower than that of the first semiconductor pattern 51' so that the conductivity of the second semiconductor pattern 52 'is lower than that of the first semiconductor pattern 51'. In addition, since the first semiconductor pattern 51 'has high conductivity, the conductivity is poor, and the first semiconductor pattern 51' can be regarded as a conductor. The second semiconductor pattern 52' has a low conductivity and can be regarded as a semiconductor.

In this embodiment, in order to further improve the oxidation resistance of Cu in the source electrode 84 and the drain electrode 85, the oxidation prevention pattern 41 may further include a protection pattern 81' located between the CuNx pattern 80' and the passivation layer 12, where the protection pattern 81' is used to prevent oxidation of Cu elements contained in the source electrode 84 and the drain electrode 85, and projections of the protection pattern 81' and the barrier pattern 6' on the substrate 60 are overlapped, that is, the protection pattern 81', the barrier pattern 6', the source electrode 84, and the drain electrode 85 may be formed through the same etching process in the same process.

Optionally, the material of the protection pattern 81' may include at least one of Cr, W, Ti, Ta, and Mo, and the at least one of Cr, W, Ti, Ta, and Mo may form a dense oxide film after being oxidized, so as to coat the surface of the source electrode 84 and the drain electrode 85 to prevent Cu in the source electrode 84 and the drain electrode 85 from being oxidized. In addition, the thickness of the protective pattern 81' may be

It should be understood that although the oxidation resistance of Cu in the source 84 and drain 85 is exemplified in the embodiments of the present application, in the manufacturing process of the actual array substrate 1, the scan line 88 (gate line) and the gate 82 are formed simultaneously with the gate 82 in the same manufacturing process, and the data line 89 (source 84 or drain 85 trace) and the source 84 or drain 85 are formed simultaneously with the source 84 or drain 85 in the same manufacturing process. Therefore, the oxidation prevention for the scan line 82 and the data line 83 can also be formed by forming a CuNx pattern 80' on the surface of the source electrode 84 and the drain electrode 85 near the passivation layer 12, or further forming a protection pattern 81' on the CuNx pattern 80', which has similar steps and processes as the source electrode 84 and the drain electrode 85, and will not be described herein again.

In addition, in practice, the array substrate 1 may include a plurality of sub-pixel regions defined by scan lines and data lines, each of the sub-pixel regions is provided with a thin film transistor device, for convenience of description, in the drawings of the present application, only a schematic diagram of one of the sub-pixel regions is drawn, it can be understood that the array substrate 1 in the present application includes a plurality of sub-pixel regions, and therefore, in the manufacturing process of the array substrate 1 in the present application, the reference to forming the gate 82 and the gate line on the substrate 60 specifically means forming the gate 82 and the gate line in the region of the array substrate 1 corresponding to each of the sub-pixel regions. Similar to the source 84, the drain 85, and the mos pattern 62, the description thereof is omitted here.

In the embodiment of the present application, the array substrate 1 includes: the anti-oxidation circuit comprises a substrate base plate 60, and a grid 82, a grid insulating layer 11, a metal oxide semiconductor pattern 62, a blocking pattern 6', a source 84 and a drain 85 containing Cu elements, an anti-oxidation pattern and a passivation layer 12 which are sequentially arranged on the substrate base plate 60, wherein the anti-oxidation pattern comprises a CuNx pattern 80', and the CuNx pattern 80' is positioned on the surface, close to the passivation layer 12, of the source 84 and the drain 85 containing Cu elements; the gate insulating layer 11 covers the gate 82, the barrier pattern 6', the source 84 and the drain 85 containing Cu, and the oxidation preventing pattern 41 are disposed above the metal oxide semiconductor pattern 62, the projection of the barrier pattern 6', the source 84 and the drain 85 containing Cu, and the oxidation preventing pattern on the substrate 60 are overlapped, and a channel region is formed between the source 84 and the drain 85. By forming the CuNx patterns 80' on the surfaces of the source and drain

electrodes

84 and 85 close to the passivation layer 12 and by including SiOx in the passivation layer 12 on the surfaces of the source and drain

electrodes

84 and 85, the CuNx can protect the source and drain

electrodes

84 and 85 and prevent the source and drain

electrodes

84 and 85 from being oxidized by the passivation layer 12 including SiOx, so that the source and drain

electrodes

84 and 85 can be prevented from being peeled off and the reliability of the array substrate 1 can be improved.

In this embodiment, the display panel includes: the array substrate and the opposite substrate are oppositely arranged, the frame glue is clamped and attached between the array substrate and the opposite substrate, and a concave-convex structure is arranged on the surface of the opposite substrate facing the frame glue and/or the surface of the array substrate facing the frame glue. The area through being equipped with concave-convex structure on array substrate and/or the contralateral substrate is full of the frame gum, when wanting to get into display panel inside through the boundary position department of frame gum and array substrate and/or contralateral substrate in external steam etc. when, concave-convex structure's setting is equivalent to the length that has increased the infiltration route of steam, and the width of frame gum is increased in the equivalence promptly to the vapour ability that blocks water of frame gum in the narrow frame display panel has been promoted, and then display panel's reliability has been promoted.

Example two

Fig. 10 is a flowchart illustrating a manufacturing method of a display panel according to a second embodiment of the present invention. As shown in fig. 10, the present embodiment provides a method for manufacturing a display panel, which is used to manufacture and implement the display panel. The detailed description of the specific structure and principle of the display panel has been given in the first embodiment, and will not be repeated herein.

As described in the description of the display panel in the first embodiment, the display panel of the present embodiment includes an array substrate and a counter substrate that are disposed opposite to each other, and a sealant sandwiched and attached between the array substrate and the counter substrate.

The manufacturing method of the display panel of the embodiment includes:

s10, forming a concave-convex structure on at least one of a surface of the counter substrate facing the array substrate and a surface of the array substrate facing the counter substrate;

and S20, arranging frame glue covering the concave-convex structure between the opposite substrate and the array substrate.

In the method, the frame glue is covered by the area of the array substrate and/or the opposite substrate provided with the concave-convex structure, when external water vapor and the like want to enter the display panel through the boundary position of the frame glue and the array substrate and/or the opposite substrate, the concave-convex structure is arranged to increase the length of a permeation path of the water vapor, namely, the width of the frame glue is equivalently increased, so that the water vapor blocking capability of the frame glue in the narrow-frame display panel is improved, and the reliability of the display panel is further improved.

In step S10, since there are a plurality of forming positions and forming methods of the concave-convex structure, the forming methods will be described below with respect to the respective concave-convex structures described in the examples. Note that the array substrate here may be a normal array substrate, or may be an array substrate provided with layers of barrier patterns 6', CuNx patterns 80', and the like as described in fig. 9. First, the case where the concave-convex structure portion is provided on a general array substrate will be described.

For the display panel shown in fig. 5, the concave-convex structure includes a groove 511 disposed on the surface of the array substrate 1 facing the sealant 3, and the groove 511 may be opened on the passivation layer 12. The manufacturing steps of the display panel 100 may include:

depositing a passivation layer 12 on the substrate 13 on which the gate insulating layer 11, the semiconductor active island, the source electrode and the drain electrode are formed; and

a photolithography process is performed to form a groove 511 at a position corresponding to the non-display area NAA on the passivation layer 12, and to form a conductive via hole at a position corresponding to the display area AA on the passivation layer 12.

The grooves 511 and the conductive vias can be formed in the same photolithographic process, so that additional processes are not required to be added for forming the grooves 511, and the cost can be reduced as much as possible.

In other examples, the groove 511 may open on the passivation layer 12 and the gate insulating layer 11, i.e., the groove 511 may extend onto the gate insulating layer 11. The manufacturing steps of the display panel 100 may include:

depositing a gate insulating layer 11 on the substrate base plate on which the gate is formed;

forming a semiconductor active island, a source electrode and a drain electrode on the gate insulating layer 11;

a photolithography process is performed to form a groove 511 at a position corresponding to the non-display area NAA on the passivation layer 12 and the gate insulating layer 11, and to form a conductive via hole at a position corresponding to the display area AA on the passivation layer 12.

For the display panel shown in fig. 6, the concave-convex structure includes a groove 521 disposed on the surface of the color film substrate 20 facing the sealant 3, and the groove 521 may be formed on the planarization layer 24. The manufacturing steps of the display panel 100 may include:

depositing a planarization layer 24 on a substrate 25 on which the black matrix 23 and the color resist material 22 are formed;

a photolithography process is performed to form a groove 521 on the planarization layer 24 at a position corresponding to the non-display area NAA.

In other examples, the groove may open on both the planarization layer 24 and the black matrix 23, i.e., the groove may extend onto the black matrix 23. The manufacturing steps of the display panel 100 may include:

depositing a planarization layer 24 on the substrate base plate 25 on which the black matrix 23 and the color resist material 22 are formed;

a photolithography process is performed to form grooves on the planarization layer 24 and the black matrix 23 at positions corresponding to the non-display regions NAA.

In some other examples, in the case that the grooves are disposed on both the array substrate 1 and the color filter substrate 20, the manufacturing steps of the display panel may include:

the groove 511 is formed in the array substrate 1;

the groove 521 is formed in the color film substrate 20;

dripping liquid crystal on the array substrate 1, and coating the frame glue 3 on the color film substrate 20, wherein the frame glue 3 covers the groove 521;

the

grooves

511 and 521 enable the array substrate 1 and the color film substrate 20 to be vacuum paired with each other under the condition that the display panel is vertically opposite to each other;

and curing the frame glue 3.

For the display panel shown in fig. 7, the concave-convex structure is a protrusion 512, and the protrusion 512 may be formed on the array substrate 1 and extend from the passivation layer 12 toward the color filter substrate 20. Specifically, the manufacturing method of the display panel 100 includes:

a photolithography process is performed to form a protrusion 512 on the passivation layer 12 at a position corresponding to the non-display area NAA, and to form a conductive via hole on the passivation layer 12 at a position corresponding to the display area AA.

The bump 512 and the conductive via can be formed in the same photolithography process, so that the groove 511 can be formed without adding an additional process, thereby reducing the cost as much as possible.

In other examples, the protrusion 512 may be disposed on the passivation layer 12 and the gate insulating layer 11. The manufacturing steps of the display panel may include:

forming a first protrusion on the gate insulating layer by a photolithography process;

and performing a photolithography process to form a second protrusion on the passivation layer 12 at a position corresponding to the first protrusion, and forming a conductive via hole on the passivation layer 12 at a position corresponding to the display area AA, where the first protrusion and the second protrusion overlap to form a protrusion 512.

It is understood that the protrusion 512 may also be formed by the gate insulating layer 11, and the manufacturing process of the display panel may include:

forming a protrusion 512 on the gate insulating layer by a photolithography process;

depositing a passivation layer on the substrate on which the gate insulating layer 11, the semiconductor active island, the source electrode and the drain electrode are formed, through a photolithography process; and

and performing a photolithography process to form an avoiding space at a position corresponding to the protrusion 512 on the passivation layer 12, and forming a conductive via hole at a position corresponding to the display area AA on the passivation layer 12.

In the display panel shown in fig. 8, the concave-convex structure is a protrusion 522, and the protrusion 522 may be formed on the color filter substrate 20 and extend from the spacer 21 toward the array substrate 1. The manufacturing method of the display panel 100 may include:

depositing a spacer layer on the substrate formed with the black matrix 23, the color resist material 22 and the planarization layer 24;

a photolithography process is performed to form spacers 21 at positions on the spacer layer corresponding to the display regions AA, and to form protrusions 522 at positions on the spacer layer corresponding to the non-display regions.

In other examples, the protrusion 522 may also be formed by the black matrix 23 and/or the color-resisting material 22, and in this case, an avoiding space, such as an avoiding hole, needs to be provided on the planarization layer 24 so as to expose the protrusion 522 formed by the black matrix 23 and/or the color-resisting material 22. Taking an example in which the protrusion 522 is formed of the black matrix 23, the method for manufacturing the display panel 100 includes:

depositing a black matrix layer on the base substrate 25;

performing a photolithography process to form a black matrix 23 at a position on the black matrix layer corresponding to the display area AA, and to form a protrusion 522 at a position on the black matrix layer corresponding to the non-display area NAA;

forming a color resist material 22 on a base substrate 25;

a planarization layer 24 is deposited on the color resist material 22, and a photolithography process is performed to form an avoiding hole in a portion of the planarization layer 24 corresponding to the protrusion 522.

In the case where the protrusion 522 is formed by any two of the spacer 21, the black matrix 23, and the color resist material 22, or by three of the spacer 21, the black matrix 23, and the color resist material 22, the description thereof is omitted here, similarly to the above description.

Next, a method for manufacturing the display panel of the present embodiment is described with reference to fig. 11 to 14. In this example, the recess is formed on the array substrate 1 as an example, and it should be noted that the array substrate may be a normal array substrate, or may be an array substrate provided with layers of barrier patterns 6', CuNx patterns 80', and the like as described in fig. 9. The following description will be given taking an example in which the concave-convex structure portion is formed on a general array substrate.

It can be understood that, in practice, for an array substrate applied to a liquid crystal display panel, the array substrate includes a plurality of sub-pixel regions defined by scan lines and data lines, and each sub-pixel region is provided with at least one thin film transistor device, for convenience of description, in fig. 11 to 14, only a schematic diagram of manufacturing one of the sub-pixel regions adjacent to the non-display region NAA is drawn, and it can be understood that the array substrate in the present application includes a plurality of sub-pixel regions, and therefore, in the manufacturing process of the array substrate in the present application, the mentioned forming a gate on the substrate specifically refers to forming a gate in a region of the array substrate corresponding to each sub-pixel region. Similar to this, source, drain, and semiconductor active islands are not described in detail herein.

Referring to fig. 11, a transparent glass substrate or quartz substrate 81 is first deposited by sputtering or thermal evaporation to a thickness of about

The gate metal layer can be Cr, W, Ti, Ta, Mo alloy, Ti alloy, etc., and has a thickness of about

The gate metal layer is Cu with a thickness of about

The gate electrode 82 and the gate scan line (not shown) are formed by a first photolithography process, thereby forming the display panel in the first state as shown in fig. 11.

Step two, continuously depositing the thickness of the display panel in the first state after the step one by a plasma enhanced chemical vapor deposition method

And a gate insulating layer 11, and successively depositing a thickness of

A high conductivity metal oxide film is then deposited by sputtering or thermal evaporation to a thickness of about

The source drain metal layer.

The gate insulating layer 11 may be an oxide, a nitride, or an oxynitride, and the corresponding reaction gas may be SiH₄，NH₃，N₂Or SiH₂Cl₂，NH₃，N₂. The metal oxide semiconductor film may be amorphous IGZO, or amorphous IGZO, HIZO, IZO, a-InZnO, or ZnO F, In₂O3:Sn、In₂O₃:Mo、Cd₂SnO₄、ZnO:Al、TiO₂Nb, Cd-Sn-O or other metal oxides.

Through a gray tone or halftone mask lithography process, the metal oxide thin film is formed into the semiconductor active island 83, and the source and drain metal layers are formed into the source 84 and the drain 85, so that the display panel in the second state shown in fig. 12 is obtained.

Step three, continuously depositing the thickness of the display panel in the second state after the step two by a plasma enhanced chemical vapor deposition method

The passivation layer 12 may be an oxide, a nitride, or an oxynitride, may be a single layer or a multilayer, and the reaction gas corresponding to the silicon oxide may be SiH₄，N₂O; nitride or oxynitride corresponding to SiH as the gas₄，NH₃，N₂Or SiH₂C_l2，NH₃，N₂. And a groove 511 is formed in the non-display area NAA through a photolithography process and a conductive via 86 is formed in the display area to form the display panel in the third state shown in fig. 13.

In the meantime.

Step four, as shown in fig. 14, a transparent conductive layer is deposited on the basis of the display panel in the third state of step three, and a pixel electrode 87 is formed on the passivation layer 12 by a photolithography process.

In this embodiment, the method for manufacturing the display panel includes: forming a concave-convex structure on at least one of a surface of the counter substrate facing the array substrate and a surface of the array substrate facing the counter substrate; and frame glue covering the concave-convex structure is arranged between the opposite substrate and the array substrate. In the method, the frame glue is covered by the area of the array substrate and/or the opposite substrate provided with the concave-convex structure, when external water vapor and the like want to enter the display panel through the boundary position of the frame glue and the array substrate and/or the opposite substrate, the concave-convex structure is arranged to increase the length of a water vapor permeation path, namely, the width of the frame glue is equivalently increased, so that the water vapor blocking capability of the frame glue in the narrow-frame display panel is improved, and the reliability of the display panel is further improved.

A method of forming a groove on a passivation layer on the array substrate 1 shown in fig. 9 will be described as an example.

Fig. 15 is a schematic flowchart of a manufacturing method of an array substrate according to a second embodiment of the present invention, and as shown in fig. 15, the manufacturing method of an array substrate according to the second embodiment includes:

s30, depositing a gate metal layer on the substrate base plate, and carrying out a first photoetching process to form a gate and a gate line on the substrate base plate;

fig. 16 is a schematic structural diagram of the array substrate in the fifth state in the manufacturing method of the array substrate according to the second embodiment of the present invention, and as shown in fig. 16, a substrate 60 is first sequentially deposited by sputtering or thermal evaporation to a thickness of about

And performing a first photolithography process on the gate metal layer to form a gate electrode 82 and a gate line in the switching region of the array substrate.

In addition, it should be understood that, in practice, for the array substrate 1 applied to the liquid crystal display panel, the array substrate 1 includes a plurality of sub-pixel regions defined by the scan lines 88 and the data lines 89, and each sub-pixel region is provided with at least one thin film transistor device, for convenience of description, in the drawings of the present application, a schematic diagram of manufacturing only one sub-pixel region is drawn, and it can be understood that, the array substrate 1 in the present application includes a plurality of sub-pixel regions, and therefore, in the manufacturing process of the array substrate 1 in the present application, the reference to forming the gate electrode 82 and the gate line on the substrate 60 specifically means forming the gate electrode 82 and the gate line in the regions of the array substrate 1 corresponding to each sub-pixel region. Similar to the source 84, the drain 85, and the mos pattern 62, the description thereof is omitted here.

For the gate metal layer, when the gate metal layer contains Cu, the gate 82 and the substrate 60 are likely to have poor adhesion, and in order to avoid this, an adhesion layer may be disposed below the gate metal layer, and fig. 17 is another schematic structural diagram of the array substrate in the fifth state in the manufacturing method of the array substrate according to the second embodiment of the present invention.

As shown in FIG. 17, a glass substrate 61 or quartz is first deposited by sputtering or thermal evaporation to a thickness of about

And an adhesion layer of about thickness

And performing a first photolithography process on the adhesion layer and the gate metal layer to form a gate electrode 82 and an adhesion layer pattern 63 overlapping the gate electrode 82 in the switching region of the array substrate.

It will be appreciated that the adhesion layer is on the side of the glass substrate adjacent to the gate metal layer to increase adhesion between the gate metal layer and the substrate and prevent the gate 82 from peeling off. The material of the adhesion layer may include at least one of Cr, W, Ti, Ta, Mo, for example the adhesion layer may be a Mo alloy, a Ti alloy, or the like.

Next, the gate insulating layer 11 is deposited on the array substrate in the fifth state, and the following processes are described in the following description by taking the array substrate with the adhesion layer formed as shown in fig. 17 as an example, it can be understood that the following processes may also be performed on the basis of the array substrate shown in fig. 16, and the process is similar to the following processes performed on the basis of fig. 16, and therefore, the description is omitted here.

Specifically, the manufacturing process of the array substrate further includes:

s40, sequentially depositing a gate insulating layer, a metal oxide semiconductor layer, a barrier layer and a source drain metal layer containing Cu element on the substrate base plate on which the gate and the gate line are formed; and forming an oxidation prevention layer containing a CuNx layer on the source and drain metal layer containing the Cu element, preferably performing plasma treatment on the source and drain metal layer containing the Cu element to form the CuNx layer on the surface of the source and drain metal layer containing the Cu element.

Fig. 18 is a schematic structural view of the array substrate in the sixth state in the manufacturing method of the array substrate according to the second embodiment of the present invention, as shown in fig. 18, specifically, first of all, fig.17 is formed by vapor deposition of Plasma Enhanced Chemical Vapor Deposition (PECVD) on the array substrate in the fifth state

The gate insulating layer 11 may be an oxide, a nitride or an oxynitride, and the corresponding reaction gas may be SiH₄、NH₃、N₂Or SiH₂Cl₂、NH₃、N₂。

Further, the gate insulating layer 11 is deposited to a thickness of about

The metal oxide semiconductor layer 5' of (2) may be amorphous IGZO, HIZO, IZO, a-InZnO, ZnO: F, In₂O₃:Sn、In₂O₃:Mo、Cd₂SnO₄、ZnO:Al、TiO₂Nb, Cd-Sn-O or other metal oxides.

Fig. 19 is another schematic structural diagram of the array substrate in the sixth state in the manufacturing method of the array substrate according to the second embodiment of the present invention, as shown in fig. 19, as a possible implementation manner, the metal oxide semiconductor layer 5 'includes but is not limited to the above-mentioned one layer, and may further include two layers, for example, the metal oxide semiconductor layer 5' may include a first semiconductor layer 53 and a second semiconductor layer 54, and the conductivity of the first semiconductor layer 53 is higher than that of the second semiconductor layer 54. The step of depositing the metal oxide semiconductor layer 5' may further include:

on the gate insulating layer 11 is successively deposited by a sputtering method to a thickness of

And a first semiconductor layer 53 having a thickness of

And a second semiconductor layer 54.

The conductivity of each semiconductor layer can be effectively controlled by controlling the content of oxygen during deposition, the content of oxygen in the deposited semiconductor layer is high, and the conductivity of the formed semiconductor layer is good and close to that of a conductor; the deposited semiconductor layer has low oxygen content, and the formed semiconductor layer has poor conductivity and is a semiconductor. That is, the oxygen content of the second semiconductor layer 54 is lower than that of the first semiconductor layer 53.

In the embodiment of the present application, the conductivity of the first semiconductor layer 53 is higher than that of the second semiconductor layer 54, so that the first semiconductor layer 53 having a higher conductivity is directly in contact with the gate insulating layer 11, and the channel of the thin film transistor is formed in the first semiconductor layer 53 and the second semiconductor layer 54, thereby stabilizing the performance of the thin film transistor. The second semiconductor layer 54 with lower conductivity is directly contacted with the source-drain metal layer, so that the contact resistance between the metal oxide semiconductor layer 5' and the source-drain metal layer can be reduced, and the on-state current of the metal oxide thin film transistor can be improved.

Next, the barrier layer 6 is deposited on the array substrate in the sixth state, and the following processes are described in the following description by taking the array substrate with two semiconductor layers formed as shown in fig. 19 as an example, it can be understood that the following processes may also be performed on the basis of the array substrate shown in fig. 18, and the process is similar to the following processes performed on the basis of fig. 19, and therefore, the description is omitted here.

Fig. 20 is a schematic structural view of the array substrate in the seventh state in the manufacturing method of the array substrate according to the first embodiment of the present invention, and as shown in fig. 20, after the metal oxide semiconductor layer 5 'is formed, the thickness of the metal oxide semiconductor layer 5' is continuously deposited by sputtering or thermal evaporation to be about

The material of the barrier layer 6 may include at least one of Cr, W, Ti, Ta, Mo, for example, the barrier layer 6 may be a Mo alloy, a Ti alloy, and the like. The barrier layer 6 can prevent the diffusion of Cu into the MOS and increase the Cu content in the source 84 and drain 85 and the MOS5' adhesion.

After forming the barrier layer 6, as shown in fig. 20, it may be successively deposited to a thickness of about by sputtering or thermal evaporation

The Cu metal of (1) is used as the source-drain metal layer 8 'containing the Cu element, and then an oxidation preventing layer is formed on the source-drain metal layer 8' containing the Cu element, for example, the surface of the source-drain metal layer 8 'containing the Cu element may be subjected to plasma gas surface treatment to convert the surface portion of the source-drain metal layer 8' close to the passivation layer 12 into the CuNx layer 80.

Alternatively, after the deposition of the source/drain metal layer 8 'containing the Cu element, a first protective layer (not shown) may be deposited directly on the source/drain metal layer 8' containing the Cu element, and the first protective layer may be formed as an oxidation prevention layer over the source electrode 84 and the drain electrode 85. And the oxidation resistance of the source electrode 7 and the drain electrode 8 can be further enhanced by forming the first protective layer by the source electrode 84 and the drain electrode 85.

Optionally, the first protection layer is deposited continuously by sputtering or thermal evaporation, and the material of the first protection layer may include at least one of Cr, W, Ti, Ta, Mo, for example, the first protection layer may be a Mo alloy, a Ti alloy, or the like. At least one of Cr, W, Ti, Ta, and Mo may form a dense oxide film after being oxidized, and the cladding covers the surface of the source 84 and the drain 85 to prevent Cu in the source 84 and the drain 85 from being oxidized. The first protective layer may have a thickness of

Further, in order to form a good pattern of the source electrode 84 and the drain electrode 85 at the time of etching, the thickness of the first protection layer may be made smaller than that of the barrier layer 6, that is, the thickness of the first protection layer may be thin. The first protective layer has a thickness of

For example, can be

The barrier layer 6 is relatively thick, primarily to prevent Cu diffusion, and may be, for example

The first protective layer may then be patterned by a photolithography process to form an oxidation-resistant pattern over the source and drain electrodes.

Optionally, the process of generating CuNx by surface treatment may be performed in a dry etching apparatus, for example, a dry etching apparatus for reactive ion etching, enhanced capacitive coupling plasma etching, and inductively coupled plasma etching, or an apparatus for performing plasma enhanced chemical vapor deposition, where the surface treatment performed in different apparatuses has different process parameters.

For example, the surface-treated plasma gas may be N₂Plasma, NH as well₃Or is H₂The surface is treated with different gases, resulting in different species.

Performing N in a dry etching apparatus₂CuNx is generated through plasma treatment, the corresponding radio frequency power is 15 kW-35 kW, the air pressure is 100 mT-1500 mT, and the flow rate of gas is 600-2500 sccm; n in a plasma enhanced chemical vapor deposition apparatus₂CuNx is generated by plasma treatment, the corresponding radio frequency power is 7 kW-20 kW, the gas pressure is 800 mT-1500 mT, and the flow of the gas is 8000-40000 sccm.

In the above method, the CuNx layer 80 is formed on the surface of the source/drain metal layer 8' containing Cu, and when the passivation layer 12 containing SiOx is deposited on the surface of the source electrode 84 and the drain electrode 85 in the subsequent process, the CuNx layer can protect the source electrode 84 and the drain electrode 85, and prevent the Cu element in the source electrode 84 and the drain electrode 85 from being oxidized by the passivation layer 12 containing SiOx, so that the reliability of the array substrate 1 can be improved.

Further, in order to form a good pattern of the source electrode 84 and the drain electrode 85 when etching, the thickness of the barrier layer 6 may be made larger than the thickness of the CuNx layer 80, i.e., the thickness of the CuNx layer 80 may be thinner. Protective layer81 a thickness of

For example, can be

Fig. 21 is another schematic structural diagram of the array substrate in the seventh state in the manufacturing method of the array substrate according to the first embodiment of the present invention, as shown in fig. 21, as an optional implementation manner, the oxidation prevention layer may further include a protection layer 81 located on the CuNx layer 80, the manufacturing method further includes a step of depositing the protection layer 81 on the CuNx layer 80 before performing the second photolithography process, and the oxidation prevention performance of the source 84 and the drain 85 may be further enhanced by forming the protection layer 81 on the CuNx layer 80.

Alternatively, the protective layer 81 is deposited continuously by sputtering or thermal evaporation, and the material of the protective layer 81 may include at least one of Cr, W, Ti, Ta, and Mo, for example, the protective layer 81 may be a Mo alloy, a Ti alloy, or the like. At least one of Cr, W, Ti, Ta, and Mo may form a dense oxide film after being oxidized, and the cladding covers the surface of the source 84 and the drain 85 to prevent Cu in the source 84 and the drain 85 from being oxidized.

Specifically, as shown in fig. 21, the thickness is approximately the same as that of the CuNx layer 80 by sputtering or thermal evaporation to be continuously deposited on the CuNx layer 80 after the step of forming the CuNx layer 80

The passivation layer 81 of (1) can effectively prevent the Cu element in the source and drain

electrodes

84 and 85 and the data line 89 from being oxidized when the passivation layer 12 containing SiOx is deposited.

The second photolithography is performed on the array substrate in the seventh state, and the following processes are described by taking the array substrate with the protective layer 81 formed as shown in fig. 21 as an example, it is understood that the following processes may also be performed on the basis of the array substrate shown in fig. 20, and the process is similar to the following processes performed on the basis of fig. 21, and thus, the details are not repeated here.

Specifically, the manufacturing process of the array substrate 1 further includes:

and S50, carrying out a second photoetching process on the metal oxide semiconductor layer, the barrier layer, the source and drain metal layers containing the Cu element and the anti-oxidation layer, so that the metal oxide semiconductor layer forms a metal oxide semiconductor pattern, the barrier layer forms an anti-diffusion pattern positioned between the metal oxide semiconductor pattern and the source and drain electrodes, the source and drain metal layers containing the Cu element form the source and drain electrodes, and the anti-oxidation layer forms an anti-oxidation pattern.

In the above method, the CuNx layer 80 is formed as an oxidation prevention layer on the surface of the source/drain metal layer 8 'containing Cu, so that the CuNx pattern 80' is formed on the surface of the source electrode 84 and the drain electrode 85 formed by etching, and when the passivation layer 12 containing SiOx is deposited on the surface of the source electrode 84 and the drain electrode 85 in the subsequent process, the CuNx can protect the source electrode 84 and the drain electrode 85 and prevent the source electrode 84 and the drain electrode 85 from being oxidized by the passivation layer 12 containing SiOx. Therefore, the peeling of the source electrode 84 and the drain electrode 85 can be prevented, and the reliability of the array substrate 1 can be improved. The second photolithography process may include a gray-tone mask process or a halftone mask process. Thus, the metal oxide semiconductor pattern 62, the source electrode 84 and the drain electrode 85 can be simultaneously formed by one photolithography process, so that one photolithography process is saved and the production efficiency is improved compared with the conventional photolithography process in the prior art.

Specifically, fig. 22 is a schematic structural diagram of the array substrate in an eighth state in the manufacturing method of the array substrate according to the first embodiment of the present invention, fig. 23 is a schematic structural diagram of the array substrate in a ninth state in the manufacturing method of the array substrate according to the first embodiment of the present invention, fig. 24 is a schematic structural diagram of the array substrate in a tenth state in the manufacturing method of the array substrate according to the first embodiment of the present invention, fig. 25 is a schematic structural diagram of the array substrate in an eleventh state in the manufacturing method of the array substrate according to the first embodiment of the present invention, fig. 26 is a schematic structural diagram of the array substrate in a twelfth state in the manufacturing method of the array substrate according to the first embodiment of the present invention, and fig. 27 is a schematic structural diagram of the final state of the array substrate in the manufacturing method of the array substrate according to the first embodiment of the present invention.

In the array substrate in the seventh state shown in fig. 21, a photoresist is coated on the protective layer 81, and a first photoresist pattern 90 is formed after exposure and development, that is, the array substrate in the eighth state shown in fig. 22 is formed, wherein the first photoresist pattern 90 includes a photoresist complete-remaining region 91, a photoresist partial-remaining region 92, and a photoresist complete-removed region 93.

The photoresist full reserved region 91 corresponds to the source 84, the drain 85 and the data line 89; the photoresist portion remaining region 92 corresponds to a channel region between the source electrode 84 and the drain electrode 85, that is, a channel region of a thin film transistor on the array substrate; the photoresist completely removed region 93 corresponds to a region on the photoresist except for the photoresist completely remaining region 91 and the photoresist partially remaining region 92.

With respect to the array substrate in the eighth state shown in fig. 22, a first etching is performed on a portion of the protective layer 81, the source-drain metal layer 8 'on which the CuNx layer 80 is formed, the barrier layer 6, and the metal oxide semiconductor layer 5' (including the second semiconductor layer 54 and the first semiconductor layer 53) located in the photoresist completely removed region 93, using the first photoresist pattern 90 as a mask, so as to form the array substrate in the ninth state shown in fig. 23.

For the array substrate in the ninth state shown in fig. 23, the first photoresist pattern 90 is ashed to remove the photoresist in the photoresist partial region 92 and reduce the photoresist in the photoresist complete region 91, and the array substrate in the tenth state shown in fig. 24 is formed, and then the second photoresist pattern 94 ashed by the first photoresist pattern 90 is used as a mask to etch the portion corresponding to the photoresist partial region 92, which is ashed and removed, so as to immediately etch away the portion corresponding to the photoresist partial region 92, which is ashed and removed, in the protective layer 81, the CuNx layer 80, the source and drain metal layer, and the barrier layer 6, thereby forming the channel region 43 of the TFT. And then the remaining photoresist is stripped to form the array substrate in the eleventh state shown in fig. 25.

In addition, a dry etching process may be employed in forming the TFT channel region, since the use of the dry etching process has a high selectivity, which may reduce corrosion of the metal oxide semiconductor layer 5' under the source and drain

electrodes

84 and 85.

It can be understood that, since the protective layer 81, the source-drain metal layer on which the CuNx layer 80 is formed, and the barrier layer 6 are etched using the same mask, the projections of the formed protective pattern 81', the CuNx pattern 80', the source electrode 84, the drain electrode 85, and the barrier pattern 6' on the substrate coincide with each other.

In addition, after the second photolithography process in step S50, the method may further include:

depositing a passivation layer 12 on the gate insulating layer 11 formed with the source electrode 84, the drain electrode 85 and the metal oxide semiconductor pattern 62, and performing a third photolithography process to form a conductive via hole 86 in a region of the passivation layer 12 above the drain electrode 85; a groove 511 is formed in the non-display area NAA to form the array substrate in the twelfth state shown in fig. 26.

In the meantime.

A transparent conductive layer is deposited on the passivation layer 12, and a fourth photolithography process is performed to form the pixel electrode 87 from the transparent conductive layer, and the pixel electrode 87 and the drain electrode 85 are communicated through the conductive via 86.

Specifically, for the array substrate in the eleventh state shown in fig. 25, the thickness is deposited by the vapor deposition method of plasma enhanced chemical

The passivation layer 12 may be selected from oxide, nitride or oxynitrideThe compound may be a single layer or multiple layers, and the reaction gas corresponding to the silicon oxide may be SiH₄、NH₃、 N₂Or SiH₂Cl₂、NH₃、N₂The conductive via 86 and the groove 511 are formed by a common photolithography process once, and the twelfth state shown in fig. 26 is formed.

For the array substrate in the twelfth state shown in fig. 26, the array substrate is continuously deposited by sputtering or thermal evaporation

The transparent conductive layer may be ITO or IZO, or other transparent metal oxide, and then a transparent pixel electrode 87 is formed by a common photolithography process, so as to form the final state of the array substrate 1 shown in fig. 27.

In the embodiment of the present application, in the second photolithography process of step S50, after forming the TFT channel region 43, the method further includes:

the portion of the metal oxide semiconductor pattern 62 located in the TFT channel region 43 is processed using NO to repair damage to the oxide semiconductor pattern during the etching of the source 84 and drain 85 electrodes, thereby improving the performance of the TFT device.

The embodiment provides a manufacturing method of an array substrate, which includes: depositing a gate metal layer on the base substrate 60 and performing a first photolithography process to form a gate electrode 82 and a gate line on the base substrate 60; a gate insulating layer 11, a metal oxide semiconductor layer 5', a blocking layer 6, and a source-drain metal layer 8' containing Cu are sequentially deposited on a substrate base plate 60 on which a gate 82 and a gate line are formed, an oxidation prevention layer including a CuNx layer is formed on the source-drain metal layer 8' containing Cu, a second photolithography process is performed on the metal oxide semiconductor layer 5', the blocking layer 6, the source-drain metal layer 8' containing Cu, and the oxidation prevention layer, so that a metal oxide semiconductor pattern 62 is formed on the metal oxide semiconductor layer 5', a diffusion prevention pattern is formed on the blocking layer 6 between the metal oxide semiconductor pattern 62 and the source 84 and drain 85, a source 84 and a drain 85 are formed on the source-drain metal layer 8' containing Cu, and an oxidation prevention pattern is formed on the oxidation prevention layer. An oxidation prevention layer containing a CuNx layer 80 is formed on the surface of the source-drain metal layer 8 'containing Cu, so that a CuNx pattern 80' is formed on the surfaces of the source electrode 84 and the drain electrode 85 formed by etching, and when the passivation layer 12 containing SiOx is deposited on the surfaces of the source electrode 84 and the drain electrode 85 in the subsequent process, the CuNx can protect the source electrode 84 and the drain electrode 85 and prevent the source electrode 84 and the drain electrode 85 from being oxidized by the passivation layer 12 containing SiOx. Therefore, the peeling of the source electrode 84 and the drain electrode 85 can be prevented, and the reliability of the array substrate 1 can be improved. And the TFT is formed by two photoetching processes, so that the number of working procedures is reduced, and the cost is reduced.

Although the above description has been given by taking the example of forming the concave-convex structure on the passivation layer, for other forming methods of the concave-convex structure, for example, the method of forming the concave-convex structure on the passivation layer and the gate insulating layer, reference is made to the above method of forming the non-display region NAA, and details thereof are not repeated.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A display panel, comprising: the display panel comprises an array substrate, a counter substrate and a frame adhesive, wherein the array substrate and the counter substrate are arranged oppositely, and the frame adhesive is clamped and attached between the array substrate and the counter substrate.

2. The display panel according to claim 1, wherein the concave-convex structure includes a protrusion provided on a surface of the opposite substrate facing the sealant; and/or

The concave-convex structure comprises protrusions arranged on the surface of the array substrate facing the frame glue.

3. The display panel according to claim 2, wherein the rugged structure comprises bumps provided on a surface of the opposite substrate facing the sealant,

the projection on the opposite side substrate is formed by extending at least part of the structure of the opposite side substrate towards the direction of the array substrate.

4. The display panel according to claim 3, wherein the counter substrate includes a black matrix, a color resist material, and a spacer which are laminated,

5. The display panel according to claim 1, wherein the concave-convex structure includes a groove provided on a surface of the opposite substrate facing the sealant; and/or

The concave-convex structure comprises a groove arranged on the surface of the array substrate facing the frame glue.

6. The display panel according to any one of claims 1 to 5,

the array substrate comprises a display area and a non-display area which is arranged outside the display area in a surrounding mode, and the arrangement position of the frame glue corresponds to the non-display area;

the portion of the array substrate located in the display area includes: the anti-oxidation graph comprises a CuNx graph, and the CuNx graph is positioned on the surface, close to the passivation layer, of the source electrode and the drain electrode containing the Cu element;

the gate insulating layer covers the gate, the blocking pattern, the source electrode and the drain electrode containing the Cu element and the anti-oxidation pattern are arranged above the metal oxide semiconductor pattern, projections of the blocking pattern, the source electrode and the drain electrode containing the Cu element and the anti-oxidation pattern on the substrate are overlapped, and a channel region is arranged between the source electrode and the drain electrode.

7. The display panel according to claim 6, wherein the metal oxide semiconductor pattern comprises a first semiconductor pattern and a second semiconductor pattern which overlap with each other, and wherein a conductivity of the first semiconductor pattern is higher than a conductivity of the second semiconductor pattern.

8. A manufacturing method of a display panel comprises an array substrate, an opposite side substrate and frame glue, wherein the array substrate and the opposite side substrate are arranged oppositely, and the frame glue is clamped and attached between the array substrate and the opposite side substrate, and the manufacturing method is characterized by comprising the following steps:

forming a concave-convex structure on at least one of a surface of the opposite-side substrate facing the array substrate and a surface of the array substrate facing the opposite-side substrate;

and frame glue covering the concave-convex structure is arranged between the opposite side substrate and the array substrate.

9. The method for manufacturing a display panel according to claim 8,

the step for forming the array substrate includes:

depositing a grid metal layer on a substrate base plate, and carrying out a first photoetching process to form a grid and a grid line on the substrate base plate;

sequentially depositing a grid insulation layer, a metal oxide semiconductor layer, a barrier layer, a source drain metal layer containing Cu element and a protective layer on the substrate with the grid and the grid line, and carrying out a second photoetching process to form a metal oxide semiconductor pattern on the metal oxide semiconductor layer, form an anti-diffusion pattern between the metal oxide semiconductor pattern and the source and drain electrodes on the barrier layer, form the source and drain metal layers into the source and drain electrodes, and form an anti-oxidation pattern above the source and drain electrodes on the protective layer;

or, the step for forming the array substrate includes:

sequentially depositing a gate insulating layer, a metal oxide semiconductor layer, a barrier layer and a source drain metal layer containing a Cu element on the substrate base plate on which the gate and the gate line are formed, and forming an anti-oxidation layer containing a CuNx layer on the source drain metal layer containing the Cu element;

and carrying out a second photoetching process on the metal oxide semiconductor layer, the barrier layer, the source and drain metal layers containing the Cu element and the anti-oxidation layer, so that the metal oxide semiconductor layer forms a metal oxide semiconductor pattern, the barrier layer forms an anti-diffusion pattern positioned between the metal oxide semiconductor pattern and the source and drain electrodes, the source and drain metal layers containing the Cu element form the source and drain electrodes, and the anti-oxidation layer forms the anti-oxidation pattern.

10. The method for manufacturing a display panel according to claim 9, wherein the metal oxide semiconductor layer includes a first semiconductor layer and a second semiconductor layer, and wherein the first semiconductor layer has higher electrical conductivity than the second semiconductor layer.