CN112033583A - SiC capacitance pressure sensor with surface array boss structure and preparation method - Google Patents
SiC capacitance pressure sensor with surface array boss structure and preparation method Download PDFInfo
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- CN112033583A CN112033583A CN202010945844.9A CN202010945844A CN112033583A CN 112033583 A CN112033583 A CN 112033583A CN 202010945844 A CN202010945844 A CN 202010945844A CN 112033583 A CN112033583 A CN 112033583A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L1/00—Measuring force or stress, in general
- G01L1/14—Measuring force or stress, in general by measuring variations in capacitance or inductance of electrical elements, e.g. by measuring variations of frequency of electrical oscillators
- G01L1/142—Measuring force or stress, in general by measuring variations in capacitance or inductance of electrical elements, e.g. by measuring variations of frequency of electrical oscillators using capacitors
- G01L1/148—Measuring force or stress, in general by measuring variations in capacitance or inductance of electrical elements, e.g. by measuring variations of frequency of electrical oscillators using capacitors using semiconductive material, e.g. silicon
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
- G01L9/12—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in capacitance, i.e. electric circuits therefor
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Abstract
The invention provides a SiC capacitance pressure sensor with a surface array boss structure and a preparation method thereof, wherein the SiC capacitance pressure sensor comprises a SiC substrate, a p-type SiC layer, a SiC lower polar plate, an insulating layer, a SiC upper polar plate and a circuit connecting structure, wherein the p-type SiC layer, the SiC lower polar plate, the insulating layer and the SiC upper polar plate are sequentially formed on the SiC substrate; the SiC lower polar plate comprises a circular lower polar plate base body and a groove array arranged on the upper surface of the lower polar plate base body; the SiC upper polar plate comprises a circular upper polar plate matrix and a boss array; the upper polar plate base body covers the lower polar plate base body, a cavity is formed between the lower surface of the upper polar plate base body and the upper surface of the insulating layer, and the boss array is matched with the groove array. The boss array is adopted on the surface of the SiC upper polar plate, and the thickness of the matrix circular film is reduced on the premise of ensuring the structural reliability, so that higher linearity is obtained; the boss array is matched with the groove array, the dead area of the upper polar plate boss side wall and the lower polar plate groove side wall is increased when the sensor works, extra capacitance increment is generated, and the sensitivity of the sensor during working is greatly increased.
Description
Technical Field
The invention belongs to the technical field of wide bandgap semiconductor device preparation, and particularly relates to a SiC capacitance pressure sensor with a surface array boss structure and a preparation method thereof.
Background
With the exploration of extreme environments, particularly high-temperature, high-pressure and high-corrosion environments, the demand of sensors applied to severe environments is more and more urgent. However, the stability and reliability of the existing Si-based sensor in severe environments can be greatly reduced, and SiC, which is a representative of third-generation wide bandgap semiconductor materials, can still maintain excellent performance in extreme environments, and is an ideal material for manufacturing sensors in severe environments.
In addition, since the accuracy and precision of the existing piezoresistive pressure sensor are easily affected by the harsh environment, an additional device or circuit is required to eliminate the influence of temperature on the sensor. The capacitive pressure sensor has strong adaptability to severe environments such as high temperature, strong radiation, strong vibration and the like, and can bear great temperature change. When the traditional flat-plate capacitance pressure sensor adopts a thick diaphragm, although good linearity exists, the sensitivity of the traditional flat-plate capacitance pressure sensor is poor, when the thin diaphragm is adopted, the sensitivity of the traditional flat-plate capacitance pressure sensor can be greatly improved, but the linearity of the traditional flat-plate capacitance pressure sensor can be greatly reduced, so that the relation between the linearity and the sensitivity is difficult to balance by the traditional flat-plate capacitance pressure sensor, and the design of a capacitance pressure sensor structure with high linearity and high sensitivity compatibility is very necessary.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the SiC capacitance pressure sensor with the surface array boss structure and the preparation method thereof are provided, and the linearity and the sensitivity are improved.
The technical scheme adopted by the invention for solving the technical problems is as follows: a SiC capacitance pressure sensor with a surface array boss structure comprises a SiC substrate, a p-type SiC layer, a SiC lower pole plate, an insulating layer, a SiC upper pole plate and a circuit connecting structure, wherein the p-type SiC layer, the SiC lower pole plate, the insulating layer and the SiC upper pole plate are sequentially formed on the SiC substrate; wherein the content of the first and second substances,
the SiC lower polar plate comprises a circular lower polar plate base body and a groove array arranged on the upper surface of the lower polar plate base body;
the SiC upper polar plate comprises a circular upper polar plate base body and a boss array arranged on the lower surface of the upper polar plate base body;
the upper polar plate substrate is integrally covered on the lower polar plate substrate, so that a cavity is formed between the lower surface of the upper polar plate substrate and the upper surface of the insulating layer, and the boss array is matched with the groove array;
the circuit connecting structure comprises a SiC electrode, a connecting circuit and a metal bonding pad above the SiC electrode; the SiC electrode comprises a first SiC electrode and a second SiC electrode which are respectively arranged on the p-type SiC layer; the connecting circuit comprises a first connecting circuit and a second connecting circuit, a gap for the first connecting circuit to pass through is arranged on the upper polar plate substrate, the first connecting circuit is used for connecting the first SiC electrode and the lower polar plate substrate, and the second connecting circuit is used for connecting the second SiC electrode and the upper polar plate substrate; the metal bonding pad comprises a first metal bonding pad and a second metal bonding pad which are respectively arranged on the SiC upper electrode plate, the first metal bonding pad is in ohmic contact with the first SiC electrode, the second metal bonding pad is in ohmic contact with the second SiC electrode, and the first metal bonding pad and the second metal bonding pad are respectively used for forming electric contact with the outside;
the insulating layer covers the surfaces and the periphery of the SiC lower pole plate and the connecting circuit, and simultaneously surrounds the periphery of the SiC electrode and the metal bonding pad, so that the SiC upper pole plate, the SiC lower pole plate and the first connecting circuit are separated, and the SiC upper pole plate and the SiC lower pole plate form a capacitor structure.
According to the scheme, the upper surface of the lower pole plate base body and the lower surface of the upper pole plate base body are on the same plane, and the size of each groove in the groove array is slightly larger than that of each boss in the boss array, so that a gap exists between each groove and the corresponding boss; the depth of each groove is the same as the thickness of the boss.
According to the scheme, each boss in the boss array is in a strip shape penetrating through the circle center of the upper polar plate base body; each groove in the groove array is in a strip shape matched with the boss.
According to the scheme, each boss in the boss array is in a mutually vertical strip shape; each groove in the groove array is in a strip shape matched with the boss.
According to the scheme, each boss in the boss array is a plurality of strips which are parallel to each other; each groove in the groove array is in a strip shape matched with the boss.
According to the scheme, the first connecting circuit and the second connecting circuit are distributed in a 180-degree mode.
According to the scheme, the SiC electrode is n-type heavily doped SiC.
According to the scheme, the gap between the lower surface of the upper electrode plate substrate and the upper surface of the insulating layer is 2 microns.
According to the scheme, the upper surface of the SiC electrode is square, and the side length is at least 250 micrometers.
The preparation method of the SiC capacitance pressure sensor with the surface array boss structure comprises the following steps:
s1, sequentially extending a p-type SiC layer and an n-type SiC layer on the SiC substrate;
s2, patterning the n-type SiC layer according to the structures of the SiC lower pole plate, the SiC electrode and the connecting circuit to form the lower pole plate, the SiC electrode and the connecting circuit;
s3, depositing an insulating layer;
s4, depositing silicon on the insulating layer to serve as a sacrificial layer;
s5, patterning the sacrificial layer according to the shape of the SiC upper polar plate;
s6, depositing SiC on the patterned sacrificial layer to form the SiC upper electrode plate;
s7, patterning the SiC upper electrode plate to form an etching hole;
s8, releasing the sacrificial layer;
s9, burying the etching holes;
and S10, arranging a metal pad above the SiC upper plate.
The invention has the beneficial effects that: the boss array is adopted on the surface of the SiC upper electrode plate of the SiC capacitance pressure sensor, the number and the size of the array bosses are designed according to the design requirements of the sensor, the thickness of the matrix circular film is reduced on the premise of ensuring the structural reliability, and the sensor not only has stronger mechanical strength, but also has better high temperature resistance, higher working range and higher linearity; the array boss structure that SiC upper plate surface adopted cooperatees with the bottom plate recess, and the just area increase of upper plate boss lateral wall and bottom plate recess lateral wall when the sensor work, the sensor can produce extra electric capacity increment promptly, the sensitivity of the during operation of greatly increased sensor. In addition, the structure can be applied to a contact type capacitance pressure sensor, and the linearity and the sensitivity of the sensor can be greatly increased.
Drawings
Fig. 1 is a schematic three-dimensional structure diagram according to a first embodiment of the present invention.
Fig. 2 is a cross-sectional view of a first embodiment of the present invention.
Fig. 3 is a cross-sectional view and a partially enlarged view of the insulation layer removed according to an embodiment of the invention.
Fig. 4 is a three-dimensional schematic diagram of a SiC upper plate according to a first embodiment of the present invention.
Fig. 5 is a three-dimensional schematic diagram of a SiC bottom plate according to a first embodiment of the invention.
Fig. 6 is a sectional view of a three-dimensional structure of a general parallel plate capacitive pressure sensor.
FIG. 7 is a comparison graph of simulation data of an embodiment of the present invention and a conventional plate capacitive pressure sensor.
Fig. 8 is a schematic view of a manufacturing process according to a first embodiment of the invention.
Fig. 9 is a three-dimensional schematic view of a SiC upper plate according to a second embodiment of the present invention.
Fig. 10 is a three-dimensional schematic view of a SiC bottom plate according to a second embodiment of the present invention.
Fig. 11 is a three-dimensional schematic view of an SiC upper plate according to a third embodiment of the present invention.
Fig. 12 is a three-dimensional schematic view of a SiC bottom plate according to a third embodiment of the present invention.
In the figure: a 1-SiC substrate; a 2-p type SiC layer; 3-SiC lower pole plate; 31-lower plate substrate; 32-groove array; 4-an insulating layer; 5-SiC upper pole plate; 51-upper plate base body; 52-boss array; a 6-SiC electrode; 61 — a first SiC electrode; 62-a second SiC electrode; 7-connecting a circuit; 71-first connection circuit; 72-a second connection circuit; 8-metal pads; 81-a first metal pad; 82-second metal pads; 811. 821-pad bottom metal; 812. 822-pad top layer metal.
Detailed Description
The invention is further illustrated by the following specific examples and figures.
The first embodiment is as follows:
the invention provides a SiC capacitance pressure sensor with a surface array boss structure, which comprises a SiC substrate 1, a p-type SiC layer 2, a SiC lower pole plate 3, an insulating layer 4 and a SiC upper pole plate 5 which are sequentially formed on the SiC substrate 1, and a circuit connecting structure, as shown in figures 1 to 5. The SiC lower pole plate 3 comprises a circular lower pole plate base body 31 and a groove array 32 arranged on the upper surface of the lower pole plate base body 31; the SiC upper plate 5 comprises a circular upper plate base body 51 and a boss array 52 arranged on the lower surface of the upper plate base body 51. The upper plate substrate 51 is integrally covered on the lower plate substrate 31, so that a cavity is formed between the lower surface of the upper plate substrate 51 and the upper surface of the insulating layer 4, and the boss array 52 is matched with the groove array 32.
The circuit connecting structure comprises an SiC electrode 6, a connecting circuit 7 and a metal bonding pad 8 above the SiC electrode 6; the SiC electrode 6 comprises a first SiC electrode 61 and a second SiC electrode 62 which are respectively arranged on the p-type SiC layer 2; the connecting circuit 7 comprises a first connecting circuit 71 and a second connecting circuit 72, a gap for the first connecting circuit 7 to pass through is arranged on the upper electrode plate base body 51, the first connecting circuit 7 is used for connecting the first SiC electrode 61 and the lower electrode plate base body 31, and the second connecting circuit 72 is used for connecting the second SiC electrode 62 and the upper electrode plate base body 51; the metal pad 8 includes a first metal pad 81 and a second metal pad 82 respectively disposed on the SiC upper plate 5, the first metal pad 81 forms an ohmic contact with the first SiC electrode 61, the second metal pad 82 forms an ohmic contact with the second SiC electrode 62, and the first metal pad 81 and the second metal pad 82 are respectively configured to form an electrical contact with the outside. The first SiC electrode 61 is connected to the positive electrode of an external power supply, and the second SiC electrode 62 is grounded.
The insulating layer 4 covers the surfaces and the periphery of the SiC lower electrode plate 3 and the connecting circuit 7, and simultaneously surrounds the periphery of the SiC electrode 6 and the metal bonding pad 8, so that the SiC upper electrode plate 5, the SiC lower electrode plate 3 and the first connecting circuit 71 are separated, and the SiC upper electrode plate 5 and the SiC lower electrode plate 3 form a capacitor structure.
In this embodiment, the upper surface of the lower plate substrate 31 and the lower surface of the upper plate substrate 51 are on the same plane, and the size of each groove in the groove array 32 is slightly larger than that of each boss in the boss array 52, so that a gap exists between each groove and the corresponding boss; the depth of each groove is the same as the thickness of the boss. Each boss in the boss array 52 is in a strip shape penetrating through the circle center of the upper pole plate base body 51; each groove in the groove array 32 is a strip shape matched with the boss.
The first connecting circuit 71 and the second connecting circuit 72 are distributed in 180 degrees.
In the present embodiment, the p-type SiC layer 2 has a thickness of 1.5 μm. + -. 0.1. mu.m. The SiC electrode 6 is n-type heavily doped SiC, the upper surfaces of the first SiC electrode 61 and the second SiC electrode 62 are both square, and the side length is at least 250 mu m.
The radius of the upper plate substrate 51 is 100 μm, and the thickness is 3 μm; the number of bosses in the boss array 52 was 10, the width was 8 μm, and the thickness was 2 μm. The number of grooves in the groove array 32 was 10, the width was 10 μm, and the depth was 2 μm. The gap between the lower surface of the upper plate substrate 51 and the upper surface of the insulating layer 4 is 2 μm.
In this embodiment, each of the first metal pad 81 and the second metal pad 82 is composed of a pad bottom layer metal 811 and 821 and a pad top layer metal 812 and 822, the pad bottom layer metals 811 and 821 are metals having good ohmic contact performance, have a thickness of 300nm ± 20nm, and form good ohmic contact with the electrode 6 by high temperature annealing; the top metal 812, 822 of the bonding pad adopts metal with good electrical contact performance and corrosion resistance, has the thickness of 700nm +/-50 nm, and is electrically contacted with the outside through a welding lead. Preferably, the metal of the bottom layer of the bonding pad can adopt nickel Ni, and the metal of the top layer of the bonding pad can adopt platinum Pt and gold Au.
Preferably, the material of the insulating layer 4 may be SiO2。
As shown in fig. 8, the preparation method of the SiC capacitive pressure sensor with the surface array boss structure includes the following steps:
s1, sequentially extending a p-type SiC layer 2 and an n-type SiC layer on the SiC substrate 1;
s2, patterning an n-type SiC layer according to the structures of the SiC lower electrode plate 3, the SiC electrode 6 and the connecting circuit 7 to form the SiC lower electrode plate 3, the SiC electrode 6 and the connecting circuit 7;
s3, depositing an insulating layer 4;
s4, depositing silicon on the insulating layer 4 to serve as a sacrificial layer;
s5, patterning the sacrificial layer according to the shape of the SiC upper polar plate 5;
s6, depositing SiC on the patterned sacrificial layer to form the SiC upper electrode plate 5;
s7, patterning the SiC upper electrode plate 5 to form an etching hole;
s8, releasing the sacrificial layer;
s9, burying the etching holes;
s10, a metal pad 8 is provided above the SiC upper plate 5.
Fig. 7 is a comparison graph of simulation of operating data of the SiC capacitive pressure sensor with the surface array mesa structure according to the first embodiment of the present invention and the ordinary parallel plate capacitive pressure sensor shown in fig. 6, and it can be seen that the sensor provided by the present invention has both high linearity and high sensitivity compared to the ordinary parallel plate capacitive pressure sensor.
Example two:
the structure and principle of the present embodiment are the same as or similar to those of the first embodiment, and the differences are as follows: as shown in fig. 9 and 10, each boss in the boss array 52 is a plurality of strips parallel to each other; each groove in the groove array 32 is a strip shape matched with the boss.
Example three:
the structure and principle of the present embodiment are the same as or similar to those of the first embodiment, and the differences are as follows: as shown in fig. 11 and 12, each boss in the boss array 52 is a mutually perpendicular bar shape; each groove in the groove array is in a strip shape matched with the boss.
The working principle of the SiC capacitance pressure sensor with the surface array boss structure is as follows: when the SiC upper electrode plate is subjected to external pressure, the SiC upper electrode plate bends downwards, the electrode plate distance between the SiC upper electrode plate and the SiC lower electrode plate is reduced, in addition, due to the existence of the upper electrode plate boss and the lower electrode plate groove, the dead area of the electrode plate between the SiC upper electrode plate and the SiC lower electrode plate is also increased, and the capacitance value of the sensor is increased under the condition of neglecting the edge effect according to a capacitance calculation formula. Along with external pressure's crescent, the interval between the upper and lower polar plate of sensor reduces gradually, and the polar plate between SiC upper plate and the SiC bottom plate is just to the area crescent, and the sensor capacitance value crescent, the capacitance value of sensor becomes positive correlation promptly, through external detection circuitry, can turn into the change of voltage with the capacitance value of sensor, reaches pressure detection's purpose.
The technical scheme of the invention adopts SiC material as the matrix material, and has higher reliability and stability in severe environment; the surface of the SiC upper pole plate adopts an array boss structure, and the number and the size of the array bosses are reasonably designed, so that the SiC upper pole plate has stronger mechanical strength, better high-temperature resistance, higher working range and higher linearity; the array boss structure that SiC upper plate surface adopted cooperatees with the bottom plate recess, and the just area increase of upper plate boss lateral wall and bottom plate recess lateral wall when the sensor work, the sensor can produce extra electric capacity increment promptly, the sensitivity of the during operation of greatly increased sensor. In addition, the structure can be applied to a contact type capacitance pressure sensor, and the linearity and the sensitivity of the sensor can be greatly increased.
The above embodiments are only used for illustrating the design idea and features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the content of the present invention and implement the present invention accordingly, and the protection scope of the present invention is not limited to the above embodiments. Therefore, all equivalent changes and modifications made in accordance with the principles and concepts disclosed herein are intended to be included within the scope of the present invention.
Claims (10)
1. A SiC capacitance pressure sensor with a surface array boss structure is characterized in that: the SiC substrate is sequentially provided with a p-type SiC layer, a SiC lower polar plate, an insulating layer, a SiC upper polar plate and a circuit connecting structure; wherein the content of the first and second substances,
the SiC lower polar plate comprises a circular lower polar plate base body and a groove array arranged on the upper surface of the lower polar plate base body;
the SiC upper polar plate comprises a circular upper polar plate base body and a boss array arranged on the lower surface of the upper polar plate base body;
the upper polar plate substrate is integrally covered on the lower polar plate substrate, so that a cavity is formed between the lower surface of the upper polar plate substrate and the upper surface of the insulating layer, and the boss array is matched with the groove array;
the circuit connecting structure comprises a SiC electrode, a connecting circuit and a metal bonding pad above the SiC electrode; the SiC electrode comprises a first SiC electrode and a second SiC electrode which are respectively arranged on the p-type SiC layer; the connecting circuit comprises a first connecting circuit and a second connecting circuit, a gap for the first connecting circuit to pass through is arranged on the upper polar plate substrate, the first connecting circuit is used for connecting the first SiC electrode and the lower polar plate substrate, and the second connecting circuit is used for connecting the second SiC electrode and the upper polar plate substrate; the metal bonding pad comprises a first metal bonding pad and a second metal bonding pad which are respectively arranged on the SiC upper electrode plate, the first metal bonding pad is in ohmic contact with the first SiC electrode, the second metal bonding pad is in ohmic contact with the second SiC electrode, and the first metal bonding pad and the second metal bonding pad are respectively used for forming electric contact with the outside;
the insulating layer covers the surfaces and the periphery of the SiC lower pole plate and the connecting circuit, and simultaneously surrounds the periphery of the SiC electrode and the metal bonding pad, so that the SiC upper pole plate, the SiC lower pole plate and the first connecting circuit are separated, and the SiC upper pole plate and the SiC lower pole plate form a capacitor structure.
2. The SiC capacitive pressure sensor of claim 1, wherein: the upper surface of the lower pole plate base body and the lower surface of the upper pole plate base body are on the same plane, and the size of each groove in the groove array is slightly larger than that of each boss in the boss array, so that a gap exists between each groove and the corresponding boss; the depth of each groove is the same as the thickness of the boss.
3. The SiC capacitive pressure sensor of claim 2, wherein: each boss in the boss array is in a strip shape penetrating through the circle center of the upper polar plate substrate; each groove in the groove array is in a strip shape matched with the boss.
4. The SiC capacitive pressure sensor of claim 2, wherein: each boss in the boss array is in a mutually vertical strip shape; each groove in the groove array is in a strip shape matched with the boss.
5. The SiC capacitive pressure sensor of claim 2, wherein: each boss in the boss array is a plurality of strips which are parallel to each other; each groove in the groove array is in a strip shape matched with the boss.
6. The SiC capacitive pressure sensor of claim 1, wherein: the first connecting circuit and the second connecting circuit are distributed in an angle of 180 degrees.
7. The SiC capacitive pressure sensor of claim 1, wherein: the SiC electrode is n-type heavily doped SiC.
8. The SiC capacitive pressure sensor of claim 1, wherein: and the gap between the lower surface of the upper polar plate substrate and the upper surface of the insulating layer is 2 microns.
9. The SiC capacitive pressure sensor of claim 1, wherein: the upper surface of the SiC electrode is square, and the side length is at least 250 mu m.
10. The method for producing the SiC capacitive pressure sensor having the surface array boss structure of any one of claims 1 to 9, wherein: the method comprises the following steps:
s1, sequentially extending a p-type SiC layer and an n-type SiC layer on the SiC substrate;
s2, patterning an n-type SiC layer according to the structures of the SiC bottom plate, the SiC electrode and the connecting circuit to form the SiC bottom plate, the SiC electrode and the connecting circuit;
s3, depositing an insulating layer;
s4, depositing silicon on the insulating layer to serve as a sacrificial layer;
s5, patterning the sacrificial layer according to the shape of the SiC upper polar plate;
s6, depositing SiC on the patterned sacrificial layer to form the SiC upper electrode plate;
s7, patterning the SiC upper electrode plate to form an etching hole;
s8, releasing the sacrificial layer;
s9, burying the etching holes;
and S10, arranging a metal pad above the SiC upper plate.
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