CN112020206B - Signal connecting plate of high-density brain electrode, preparation method and equipment - Google Patents
Signal connecting plate of high-density brain electrode, preparation method and equipment Download PDFInfo
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- CN112020206B CN112020206B CN202010822822.3A CN202010822822A CN112020206B CN 112020206 B CN112020206 B CN 112020206B CN 202010822822 A CN202010822822 A CN 202010822822A CN 112020206 B CN112020206 B CN 112020206B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
Abstract
The application discloses a signal connecting plate of a high-density brain electrode, a preparation method and equipment, wherein the signal connecting plate comprises a substrate, a plurality of metal wiring layers and a plurality of insulating layers, wherein the plurality of metal wiring layers and the plurality of insulating layers are arranged on the substrate, the orthographic projection size of a second insulating part in each insulating layer in the thickness direction of the signal connecting plate is smaller than or equal to the orthographic projection size of a metal wiring part in an adjacent lower metal wiring layer in the thickness direction of the signal connecting plate, and the orthographic projection size of an adjacent upper metal wiring layer in the thickness direction of the signal connecting plate is larger than or equal to the orthographic projection size of the adjacent upper metal wiring layer in the thickness direction of the signal connecting plate. Therefore, the number of channels which can be connected by the signal circuit board can be increased, and the signal connection of the high-density brain-computer interface is realized.
Description
Technical Field
The invention relates to the technical field of brain-computer interfaces, in particular to a signal connecting plate of a high-density brain electrode, a preparation method and equipment.
Background
The brain, the most complex and advanced biological organs of the known universe, has created a myriad of fanciful thoughts that govern the body of an organism to perform various complex activities, but at present we are poorly aware of the principles of brain work. The development of brain science is promoted by the complex structure of the brain, researchers are constantly developing new tools and new methods to analyze brain activities, which depend on hundreds of millions of neurons, and the complex physiological activities of the neurons constitute complex brain circuits, so that the high-density acquisition of the neuron activities becomes an indispensable condition for precisely interpreting brain science.
In order to reduce the damage to the brain after implantation, the front-end acquisition devices are generally on the order of microns, and the back-end circuits are also generally miniaturized. In order to meet the requirement of high-density brain signal acquisition, the number of channels for acquiring brain electrical signals is increased from single digit to thousands of orders, so that Pad distances corresponding to thousands of brain electrical signals reach micrometer orders, and an ordinary printed circuit board cannot meet the requirement of high-density brain electrode signal connection, and other high-density connection modes are urgently needed.
In order to solve the above-mentioned needs, the related connection methods in the prior art mainly include the following two types:
the first connection mode is to use insulated micro-wire bundles as a device for acquiring brain electrical signals at the front end, and the connection method is to use a CMOS chip as a device for acquiring brain electrical signals at the rear end. In the mode, the grid electrode of the CMOS device is used as a bonding connection point of the microwire, the high integration level of the CMOS chip enables the matching of micron-sized intervals between the CMOS chip and the microwire to be possible, the CMOS chip is used for realizing signal connection, meanwhile, the rear-end processing of signals, such as amplification, filtering and the like, can be carried out, and the acquisition of front-end signals and the rear-end signal processing are connected through the bonding of the CMOS chip and the microwire. However, this connection method involves the design and processing of the back-end CMOS chip and the problem of the need for a self-made alignment bonding apparatus, which requires a lot of labor and financial resources to solve, and is not applicable to the front-end brain electrode device of the micro-wire harness, and is not universal, so it is difficult to apply to most other brain electrode devices.
The second connection mode is to adopt a connection cable as a connection plate of the front-end acquisition device and the back-end circuit, and the method better solves the problem that the high-density connection of the pressure welding points of the front-end acquisition device cannot be achieved by using a traditional printed circuit board as the connection plate. However, the number of channels which can be connected by a single connecting cable is only 256 at present, and the thousands of electroencephalogram signals can be acquired by assembling a plurality of devices, a plurality of connecting cables and a plurality of rear-end circuit boards to reach thousands of electroencephalogram channels. The connection mode has low integration level, and the larger volume and weight can have great influence on animal experiments, so that some improvements are needed.
Disclosure of Invention
In view of at least one of the problems of the prior art, an object of the present invention is to provide a signal connecting plate for a high-density brain electrode, a method for manufacturing the same, and an apparatus for manufacturing the same.
In order to solve the technical problem, a signal connecting board of a high-density brain electrode is provided, which is provided with a first connecting area, a second connecting area and a transition area positioned between the first connecting area and the second connecting area; the first connecting area comprises a plurality of first sub-areas which are sequentially distributed along the direction from the first connecting area to the second connecting area, and the second connecting area comprises a plurality of second sub-areas which are sequentially distributed along the direction from the second connecting area to the first connecting area; the signal connecting board comprises a substrate, and a plurality of metal wiring layers and a plurality of insulating layers which are arranged on the substrate;
each layer of metal wiring layer comprises a front end connecting part, a metal routing part and a rear end connecting part which are sequentially connected, the front end connecting part comprises a first silicon chip pin, and the rear end connecting part comprises a second silicon chip pin; the front end connecting parts in each layer of metal wiring layer are respectively positioned in the corresponding different first sub-areas in the first connecting area, and the rear end connecting parts in each layer of metal wiring layer are respectively positioned in the corresponding different second sub-areas in the second connecting area;
each insulating layer is arranged on the corresponding metal wiring layer, each insulating layer comprises a first insulating part and a second insulating part, and the first insulating part is provided with an opening for exposing the first silicon chip pin and the second silicon chip pin in the corresponding metal wiring layer;
the orthographic projection dimension of the second insulating part in the thickness direction of the signal connecting plate is smaller than or equal to the orthographic projection dimension of the metal routing part in the adjacent lower metal wiring layer in the thickness direction of the signal connecting plate, and is larger than or equal to the orthographic projection dimension of the adjacent upper metal wiring layer in the thickness direction of the signal connecting plate.
In some embodiments, the number of metal wiring layers and the number of insulating layers are both three layers;
the outline shape of the second insulating part in each insulating layer is matched with the outline shape of the upper metal wiring layer covered on the second insulating part;
the line width of each metal wiring on the metal wiring layer is micrometer.
In some embodiments, the first silicon chip pin is connected with a front-end acquisition device, and the second silicon chip pin is connected with a back-end circuit;
the distance between the adjacent first silicon chip pins is less than or equal to 0.5 mm; and/or
And the distance between the adjacent second silicon chip pins is less than or equal to 1 mm.
In some embodiments, the signal connection board further comprises a metal transition layer comprising:
one side of each first transition pin in the first transition part is connected with the corresponding first silicon chip pin in each metal wiring layer, and the other side of each first transition pin in the first transition part is used for being connected with a front-end acquisition device;
one side of each second transition pin in the second transition pins is connected with the corresponding second silicon chip pin in each layer of metal wiring layer, and the other side of each second transition pin is used for being connected with a back-end circuit;
the size of each first transition pin is larger than that of the corresponding first silicon chip pin, and the size of each second transition pin is larger than that of the corresponding second silicon chip pin.
In some embodiments, the signal connection board further comprises metal bumps;
the metal bump is located the multilayer on the metal wiring layer, it includes metal adhesion layer, well metal bump layer and last metal solder joint layer down, down the metal adhesion layer with front end connecting portion and/or rear end connecting portion connect, well metal bump layer set up in down the metal adhesion layer with go up between the metal solder joint layer, it can be connected with front end acquisition device and/or rear end circuit to go up the metal solder joint layer.
In some embodiments, the material of the substrate is a flexible polymer; and/or
The metal wiring layer is made of chromium/gold; and/or
The insulating layer is made of flexible polymer; and/or
The lower metal adhesion layer is made of metal nickel, the middle metal bump layer is made of metal copper, and the upper metal welding spot layer is made of lead-tin alloy.
The application also provides a preparation method of the signal connecting plate of the high-density brain electrode, which at least comprises the following steps:
providing a substrate, wherein a sacrificial layer is formed on the surface of the substrate;
forming a substrate with a preset shape on the surface of the sacrificial layer;
forming a patterned metal wiring layer on the substrate to obtain a first metal wiring layer; the first metal wiring layer comprises a front end connecting part, a metal routing part and a rear end connecting part which are sequentially connected, the front end connecting part comprises a first silicon chip pin, and the rear end connecting part comprises a second silicon chip pin;
forming an insulating layer on the first metal wiring layer to obtain a first insulating layer; the first insulating layer comprises a first insulating part and a second insulating part; openings for exposing the first silicon chip pins and the second silicon chip pins in the metal wiring layer of the corresponding layer are formed in the first insulating part; the orthographic projection size of the second insulating part in the thickness direction of the signal connecting plate is smaller than or equal to the orthographic projection size of the metal routing part in the first layer of metal wiring layer in the thickness direction of the signal connecting plate;
forming a patterned metal wiring layer on the second insulating part in the first insulating layer to obtain a second metal wiring layer;
forming an insulating layer on the second metal wiring layer to obtain a second insulating layer;
repeating the step of forming the metal wiring layer and the step of forming the insulating layer;
and when the formed metal wiring layer and the formed insulating layer meet the preset number of layers, releasing the sacrificial layer to obtain the signal connecting plate of the high-density brain electrode.
In some embodiments, the number of layers of the metal wiring layer and the insulating layer is three, and the method further includes, after repeating the step of forming the metal wiring layer and the step of forming the insulating layer and before the step of releasing the sacrificial layer:
forming a metal transition layer at the position of the opening in each insulating layer in the three-layer metal wiring layer; the center point of each transition pin in the metal transition layer is aligned with the center point of the corresponding silicon chip pin, and the size of each transition pin is larger than that of the corresponding silicon chip pin;
and the line width of each metal wiring on the first metal wiring layer, the second metal wiring layer and the third metal wiring layer is in a micrometer scale.
In some embodiments, the method further comprises:
forming metal bumps on the multiple metal transition layers; the metal bump comprises a lower metal adhesion layer, an intermediate metal bump layer and an upper metal welding point layer, wherein the lower metal adhesion layer is connected with the front end connecting part and/or the rear end connecting part, the intermediate metal bump layer is arranged between the lower metal adhesion layer and the upper metal welding point layer, and the upper metal welding point layer can be connected with the front end collecting device and/or the rear end circuit.
The application also provides electronic equipment which comprises the signal connecting plate of the high-density brain electrode or the signal connecting plate prepared by the preparation method of the signal connecting plate of the high-density brain electrode.
The signal connecting plate of the high-density brain electrode, the preparation method and the equipment at least have the following beneficial effects:
the front-end connecting part in each layer of metal wiring layer in the signal connecting plate of the high-density brain electrode provided by the embodiment of the application is respectively positioned in different first sub-areas corresponding to the first connecting areas in the signal connecting plate, and the rear-end connecting part in each layer of metal wiring layer is respectively positioned in different second sub-areas corresponding to the second connecting areas in the signal connecting plate; an opening for exposing a silicon chip pin in the metal wiring layer of the corresponding layer is formed in the first insulating part in the insulating layer, and the orthographic projection size of the second insulating part in the thickness direction of the signal connecting plate is smaller than or equal to the orthographic projection size of the metal routing part in the adjacent lower metal wiring layer in the thickness direction of the signal connecting plate and larger than or equal to the orthographic projection size of the adjacent upper metal wiring layer in the thickness direction of the signal connecting plate. Therefore, by arranging the multiple layers of metal wiring layers and the multiple layers of insulating layers, and arranging the two adjacent layers of metal wiring layers at two sides of the second insulating part in the insulating layer between the two layers of metal wiring layers in a staggered manner, the number of channels which can be connected by the signal circuit board can be increased, the connection of the EEG signals of a single signal connecting plate, which reach 2160 channels or even more, can be realized, a good and feasible scheme is provided for the high-density brain-computer interface signal connection, and the universality is high.
In addition, the metal wiring layer on the signal connecting plate is prepared by utilizing a photoetching technology and through multiple photoetching and metal evaporation processes, the wiring line width of the circuit connecting plate can be reduced to the micron level, the distance between the electroencephalogram electrode signals is greatly reduced, the connection of the electroencephalogram signals at the micron level is met, the connection of the electroencephalogram signals of thousands of channels can be met, and a new solution is provided for the collection of the electroencephalogram electrode signals with high density and high flux.
Drawings
In order to more clearly illustrate the technical solutions and advantages of the embodiments of the present application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic structural diagram of a signal connecting board of a high-density brain electrode according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a metal wiring layer in a signal connection board of a high-density brain electrode according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating the structure of an insulating layer in a signal connecting board of a high-density brain electrode according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a metal transition layer in a signal connecting board of a high-density brain electrode according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a part of a signal connecting board of a high-density brain electrode, which includes a metal transition layer and metal bumps according to an embodiment of the present application;
FIG. 6 is a schematic flow chart of a method for manufacturing a signal connecting plate of a high-density brain electrode according to an embodiment of the present application;
fig. 7 is a schematic process diagram of a method for manufacturing a signal connecting board of a high-density brain electrode according to an embodiment of the present application.
Wherein the reference numerals are:
a signal connecting plate-10;
a substrate-100;
a metal wiring layer-110, a front end connecting part-111, a rear end connecting part-112 and a metal routing part-113;
an insulating layer-120, a first insulating portion 121, a second insulating portion 122;
metal transition layer-130;
metal bump-140, lower metal adhesion layer-141, middle metal bump layer-142, and upper metal pad layer-143.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Reference hereinafter to "one embodiment" or "an embodiment," etc., refers to a particular feature, structure, or characteristic that may be included in at least one implementation of the invention. In the description of the present invention, it is to be understood that the terms "upper", "lower", "left", "right", "top", "bottom", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein.
It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the element, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. And, if the component is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
Fig. 1 is a schematic structural diagram of a signal connection board for high-density brain electrodes according to an embodiment of the present invention, fig. 2 is a schematic structural diagram of a metal wiring layer in the signal connection board for high-density brain electrodes according to the embodiment of the present invention, and fig. 3 is a schematic structural diagram of an insulating layer in the signal connection board for high-density brain electrodes according to the embodiment of the present invention. As shown in fig. 1 to 3, the signal connecting board 100 of the high-density brain electrode has a first connecting area a1, a second connecting area a2, and a transition area A3 between the first connecting area a1 and the second connecting area a 2; the first connection area a1 comprises several first sub-areas distributed in sequence along the first connection area a1 to the second connection area a2, and the second connection area a2 comprises several second sub-areas distributed in sequence along the second connection area a2 to the first connection area a 1. Continuing to fig. 1, the signal connection board 10 includes a substrate 100, and a metal wiring layer 110 and an insulating layer 120 disposed on the substrate.
The number n of layers of the metal wiring layers 110 is multiple, each layer of metal wiring layer 110 comprises a front end connecting portion 111, a metal routing portion 113 and a rear end connecting portion 112 which are sequentially connected, the front end connecting portion comprises a first silicon chip pin, and the rear end connecting portion comprises a second silicon chip pin.
The front end connecting parts in each layer of metal wiring layer are respectively positioned in the corresponding different first sub-areas in the first connecting area, and the rear end connecting parts in each layer of metal wiring layer are respectively positioned in the corresponding different second sub-areas in the second connecting area. The metal wire portion 113 communicates with the front end connection portion 111 and the rear end connection portion 112.
Continuing with any one of the metal wiring layers shown in fig. 2, the first silicon chip pin and the second silicon chip pin are respectively metal Pad arrays, the front-end connection portion 111 in the figure may include a first metal Pad array with a smaller lower portion and an end portion trace, the rear-end connection portion 112 may include a second metal Pad array with a larger upper portion and an end portion trace, and the metal trace portion 113 is a metal trace connecting the two Pad arrays of the upper portion and the lower portion and the end portion trace.
The number m of insulating layers 120 is multiple, each insulating layer 120 is disposed on a corresponding metal wiring layer, and each insulating layer includes a first insulating portion 121 and a second insulating portion 122.
The first insulating portion 121 is formed with an opening 1211 exposing the first silicon chip pin and the second silicon chip pin of the metal wiring layer of the corresponding layer.
The orthographic projection dimension of the second insulating part 122 in the thickness direction of the signal connecting board is smaller than or equal to the orthographic projection dimension of the metal routing parts in the adjacent lower metal wiring layers in the thickness direction of the signal connecting board, and is larger than or equal to the orthographic projection dimension of the adjacent upper metal wiring layers in the thickness direction of the signal connecting board. That is, two adjacent metal wiring layers are disposed with a shift on both sides of the second insulating portion in the insulating layer therebetween.
In a specific embodiment, the number of layers n and m are positive integers greater than 1. The number of layers n of the metal wiring layer 110 is related to the maximum number of channels of each metal wiring layer and the total number of channels of the front-end collecting device. The number m of insulating layers 120 is associated with the number of layers of metal wiring layers 110.
For example only, if the maximum number of channels of each metal wiring layer is the same and is 720 channels, and the total number of channels of the front-end collection device is 2160 channels, the number n of layers of the metal wiring layer is 3. In this embodiment, the maximum number of channels in each metal wiring layer is the same, that is, the number of Pad arrays in each metal wiring layer connected to the front-end acquisition device is the same. In other embodiments, the maximum number of channels in each metal wiring layer may not be completely the same, that is, the number of Pad arrays in each metal wiring layer connected to the front-end acquisition device is not completely the same.
In the present embodiment, the metal wiring layers are three layers, the corresponding insulating layers are three layers, and the number of the first sub-area and the second sub-area corresponding to the metal wiring layers is three, for example, as shown in fig. 1 to 3, the first sub-area includes a11, a12, and a13, and the second sub-area includes a21, a22, and a 23.
As shown in fig. 2, a in fig. 2 is a first metal wiring layer, b is a second metal wiring layer, and c is a third metal wiring layer. d is a partial amplification schematic diagram of a second silicon chip pin connected with the back-end circuit in the third metal wiring layer; e is a partial enlarged schematic diagram of a first silicon chip pin connected with the front-end collecting device in the third metal wiring layer. Wherein, the front end connection 111 and the back end connection 112 in the first metal wiring layer in a in fig. 2 are respectively located in the first sub-area a11 and the second sub-area a 21; the front-end connection 111 and the back-end connection 112 in the second metal wiring layer in b in fig. 2 are located in the first sub-area a12 and the second sub-area a22, respectively; the front end connection 111 and the back end connection 112 in the third metal wiring layer in c in fig. 2 are located in the first sub-area a13 and the second sub-area a23, respectively, and the metal routing portions 113 in each figure communicate with the front end connection 111 and the back end connection 112, respectively.
As shown in fig. 3, a ' in fig. 3 is a first insulating layer, b ' is a second insulating layer, and c ' is a third insulating layer. d' is a partial enlarged schematic diagram of a second opening (Pad hole site) exposing a second silicon chip pin connected with the back-end circuit; e' is a partially enlarged schematic view of the first opening (pad hole site) exposing the first silicon chip pin connected to the front end collecting device. Wherein, the first insulating portion 121 in the first insulating layer in a' in fig. 3 is disposed at two ends and located in the first sub-area a11 and the second sub-area a21, respectively; the first insulating portion 121 in b' of fig. 3 is also disposed at two ends, and is respectively located in the first sub-area a12 and the second sub-area a 22; the first insulating portion 121 in c' of fig. 3 is also disposed at two ends and located in the first sub-area a13 and the second sub-area a23, respectively. The first insulating portion 121 in each figure is provided with openings for exposing the first silicon chip pins and the second silicon chip pins in the metal wiring layer of the corresponding layer.
In practical applications, the first insulating layer is disposed between the first metal wiring layer and the second metal wiring layer, the second insulating layer is disposed between the second metal wiring layer and the third metal wiring layer, and the third insulating layer is disposed on the third metal wiring layer. With continued reference to fig. 1 to 3, the orthographic projection dimension of the second insulating portion 122 on the first insulating layer in the thickness direction of the signal connection board is smaller than or equal to the orthographic projection dimension of the metal routing portion in the adjacent first metal wiring layer (i.e. the lower metal wiring layer) in the thickness direction of the signal connection board, and is larger than or equal to the orthographic projection dimension of the adjacent second metal wiring layer (i.e. the upper metal wiring layer) in the thickness direction of the signal connection board. Similarly, the size of the orthographic projection of the second insulating part 122 on the second insulating layer in the thickness direction of the signal connecting board is smaller than or equal to the size of the orthographic projection of the metal routing part in the thickness direction of the signal connecting board in the adjacent second metal wiring layer (namely, the lower metal wiring layer), and is larger than or equal to the size of the orthographic projection of the adjacent third metal wiring layer (namely, the upper metal wiring layer) in the thickness direction of the signal connecting board. The orthographic projection size of the second insulating part 122 on the third insulating layer (namely, the uppermost insulating layer) in the thickness direction of the signal connecting board is smaller than or equal to the orthographic projection size of the metal routing part in the adjacent third metal wiring layer (namely, the lower metal wiring layer) in the thickness direction of the signal connecting board. That is, two adjacent metal wiring layers are arranged on two sides of the second insulating part in the insulating layer between the two metal wiring layers in a staggered manner, so that the first silicon chip pin and the second silicon chip pin on the multilayer metal wiring layers on the finally obtained signal connecting plate are exposed outside so as to be connected with the front-end acquisition device and the rear-end circuit respectively, and high-density brain-computer interface signal transmission is realized.
In some embodiments, the spacing between adjacent first silicon die pins is less than or equal to 0.5 mm, including, but not limited to, 0.1mm, 0.2mm, 0.25mm, 0.3mm, and the like, for example. And/or the spacing between adjacent second silicon chip pins is less than or equal to 1mm, such as but not limited to 0.1mm, 0.4mm, 0.6mm, 0.8mm, and the like.
It should be understood that the first silicon chip pin and the second silicon chip pin in each metal wiring layer may have the same size or different sizes. The size and shape of the first opening and the second opening on the insulating layer corresponding to each metal wiring layer can be the same as or different from the size and shape of the corresponding first silicon chip pin and second silicon chip pin.
In this embodiment, the first silicon chip pins and the second silicon chip pins in each metal wiring layer have the same size. The sizes of the first opening and the second opening on the insulating layer corresponding to each metal wiring layer can be respectively the same as the sizes of the corresponding first silicon chip pin and the corresponding second silicon chip pin. The pitch of the first silicon chip pins in each metal wiring layer is 0.25mm, and the size is 0.08mm multiplied by 0.08 mm. The pitch of the second silicon chip pins in each metal wiring layer is 0.8mm, and the size is 0.25mm multiplied by 0.25 mm.
Accordingly, the first openings have a size of 0.08mm × 0.08mm and a pitch of 0.25mm on the insulating layer. The size of the second openings is 0.25mm × 0.25mm, and the pitch is 0.8 mmm.
In some embodiments, the line width of each metal wiring on the metal wiring layer is in the order of micrometers. By way of example only, the line width of the connection portion on the metal wiring layer near the front-end pickup device is any value of 2 to 10 μm, for example, 5 μm, and the line width of the connection portion near the back-end circuit is any value of 10 to 20 μm, for example, 16 μm. It should be understood that the line width of the connection portion on the metal wiring layer is not limited thereto, and the specific value thereof may be adjusted accordingly according to the actual situation.
In some embodiments, the opening 1211 on the first insulating portion 121 in each insulating layer includes a first opening and a second opening, and the size of the first opening matches the size of the first silicon chip pin in the metal insulating layer covered by the insulating layer, so as to expose the first silicon chip pin, and thus the first silicon chip pin can be connected to the front end collecting device through the first opening. Illustratively, the front-end acquisition device may comprise a brain electrode acquisition device. The size of the second opening is matched with that of a second silicon chip pin in the metal insulating layer covered by the insulating layer, and the second opening is used for exposing the second silicon chip pin so that the second silicon chip pin is connected with the back-end circuit through the second opening. Illustratively, the back-end circuitry may include a printed circuit board or back-end processing circuitry, or the like.
In some embodiments, one side of the second insulating portion covers at least the metal wire routing portion in the lower metal wiring layer of the two adjacent metal wiring layers, and the upper metal wiring layer of the two adjacent metal wiring layers completely covers at least part of the other side of the second insulating portion.
In the present embodiment, the outline shape of the second insulating section in each insulating layer matches the outline shape of the upper-layer metal wiring layer covering it. That is, one side of the second insulating portion completely covers the area where the metal wiring portion in the lower metal wiring layer in the two adjacent metal wiring layers is located, and the upper metal wiring layer in the two adjacent metal wiring layers completely covers the area where the other side of the second insulating portion is located.
In some embodiments, the material of the metal wiring layer may be a noble metal or noble metal alloy, such as 5nm/100nm chromium/gold, 30nm/150nm chromium/gold, and the like.
The material of the insulating layer is flexible polymer, such as polyimide, polyethylene terephthalate, photoresist and the like.
It should be understood that the specific materials and thicknesses of the metal wiring layer and the insulating layer are not limited thereto, and may be adjusted accordingly according to actual conditions and requirements.
In some embodiments, the substrate material is a flexible polymer such as, but not limited to, polyimide, polyethylene terephthalate, and the like. Therefore, the prepared signal connecting plate is a flexible connecting plate, has good flexibility, and provides great convenience for subsequent animal experiments or implantation.
Of course, in other embodiments, the material of the substrate may be replaced by a hard material such as silicon wafer, glass, etc.
In some embodiments, to facilitate the connection of the signal connection board obtained by the subsequent manufacturing with the front-end acquisition device and the back-end circuit, as shown in fig. 4 and 5, the signal connection board further includes a metal transition layer 130, and the metal transition layer is located on the last insulating layer. The metal transition layer 130 includes a first transition portion and a second transition portion;
one side of each first transition pin in the first transition part is connected with the corresponding first silicon chip pin in each metal wiring layer, and the other side of each first transition pin in the first transition part is connected with a front-end acquisition device;
one side of each second transition pin in the second transition pins is connected with the corresponding second silicon chip pin in each layer of metal wiring layer, and the other side of each second transition pin is used for being connected with a back-end circuit;
the size of each first transition pin is larger than that of the corresponding first silicon chip pin, and the size of each second transition pin is larger than that of the corresponding second silicon chip pin.
In practical applications, the metal transition layer may be disposed on the last insulating layer by sputtering or the like. In order to reduce cost and improve efficiency, the metal transition layer is preferably formed only at the positions where the first and second silicon chip pins are exposed. Furthermore, one part of the metal transition layer is filled into the first opening and the second opening so as to be respectively connected with the first silicon chip pin and the second silicon chip pin, and the other part of the metal transition layer extends to the position, close to the opening, on each insulating layer.
In this embodiment, with continued reference to fig. 4, m in fig. 4 is a top view of the metal transition layer, n in the figure is a partially enlarged schematic diagram of the second transition portion connected to the back-end circuit, where the pin size is increased to 0.48mm × 0.48mm, and p in the figure is a partially enlarged schematic diagram of the first transition portion connected to the front-end capture device, where the pin size is increased to 0.15mm × 0.15 mm. Preferably, the center position of the pin in the first transition part is aligned with the center position of the first silicon chip pin in each metal wiring layer, and the center position of the pin in the second transition part is aligned with the center position of the second silicon chip pin in each metal wiring layer.
In the above embodiment, by disposing the metal transition layer on the last insulating layer, the size of the pin connected to the front-end pickup device can be increased from 0.08mm × 0.08mm to 0.15mm × 0.15mm, and the size of the pin connected to the front-end pickup device can be increased from 0.25mm × 0.25mm to 0.48mm × 0.48 mm. Therefore, the area of the pin Pad can be enlarged while metal wiring is carried out as much as possible, the connection with a front-end acquisition device and a rear-end circuit is facilitated, and the connection accuracy of the signal connection board is improved.
In one embodiment, the material of the metal transition layer is a noble metal or noble metal alloy, such as 30nm/30nm/150nm of chromium/nickel/gold, etc.
It should be understood that the specific material and thickness of the metal transition layer are not limited thereto, and can be adjusted accordingly according to the actual situation and requirement.
In some embodiments the signal connection board further comprises a shape-defining layer on the substrate for the purpose of patterning the substrate of the entire signal connection board, on which shape-defining layer subsequent metal conductors etc. are prepared, also being the overall shape of the final signal connection board. The material and thickness of the shape defining layer can be selected according to actual conditions.
In some embodiments, continuing to fig. 5, the signal connection board 10 may further include metal bumps 140.
The metal bump 140 is located in multiple layers on the metal wiring layer, and includes a lower metal adhesion layer 141, an inner metal bump layer 142 and an upper metal pad layer 143, the lower metal adhesion layer 141 and the front end connection portion and/or the rear end connection portion are connected, the inner metal bump layer 142 is disposed between the lower metal adhesion layer and the upper metal pad layer, and the upper metal pad layer 143 can be connected with a front end acquisition device and/or a rear end circuit.
For example only, the material of the lower metal adhesion layer 141 may be nickel metal, the material of the middle metal bump layer 142 is copper metal, and the material of the upper metal pad layer 143 is a lead-tin alloy. The thicknesses and materials of the lower metal adhesion layer 141, the middle metal bump layer 142, and the upper metal pad layer 143 are adjusted according to practical situations, and this is not particularly limited in this application.
The front-end connecting part in each layer of metal wiring layer in the signal connecting plate of the high-density brain electrode provided by the embodiment of the application is respectively positioned in different first sub-areas corresponding to the first connecting areas in the signal connecting plate, and the rear-end connecting part in each layer of metal wiring layer is respectively positioned in different second sub-areas corresponding to the second connecting areas in the signal connecting plate; an opening for exposing a silicon chip pin in the metal wiring layer of the corresponding layer is formed in the first insulating part in the insulating layer, and the orthographic projection size of the second insulating part in the thickness direction of the signal connecting plate is smaller than or equal to the orthographic projection size of the metal routing part in the adjacent lower metal wiring layer in the thickness direction of the signal connecting plate and larger than or equal to the orthographic projection size of the adjacent upper metal wiring layer in the thickness direction of the signal connecting plate. Therefore, by arranging the multiple layers of metal wiring layers and the multiple layers of insulating layers, and arranging the two adjacent layers of metal wiring layers at two sides of the second insulating part in the insulating layer between the two layers of metal wiring layers in a staggered manner, the number of channels which can be connected by the signal circuit board can be increased, the connection of the EEG signals of a single signal connecting plate, which reach 2160 channels or even more, can be realized, a good and feasible scheme is provided for the high-density brain-computer interface signal connection, and the universality is high.
In addition, the metal wiring layer on the signal connecting plate is prepared by utilizing a photoetching technology and through multiple photoetching and metal evaporation processes, the wiring line width of the circuit connecting plate can be reduced to the micron level, the distance between the electroencephalogram electrode signals is greatly reduced, the connection of the electroencephalogram signals at the micron level is met, the connection of the electroencephalogram signals of thousands of channels can be met, and a new solution is provided for the collection of the electroencephalogram electrode signals with high density and high flux.
The application also provides a preparation method of the signal connecting plate of the high-density brain electrode. Fig. 6 is a schematic flow chart of a method for manufacturing a signal connecting board of a high-density brain electrode according to an embodiment of the present application. As shown in fig. 6, the method at least includes:
s601, providing a substrate, wherein a sacrificial layer is formed on the surface of the substrate;
s603, forming a substrate with a preset shape on the surface of the sacrificial layer;
s605, forming a patterned metal wiring layer on the substrate to obtain a first metal wiring layer; the first metal wiring layer comprises a front end connecting part, a metal routing part and a rear end connecting part which are sequentially connected, the front end connecting part comprises a first silicon chip pin, and the rear end connecting part comprises a second silicon chip pin;
s607, forming an insulating layer on the first metal wiring layer to obtain a first insulating layer; the first insulating layer comprises a first insulating part and a second insulating part; openings for exposing the first silicon chip pins and the second silicon chip pins in the metal wiring layer of the corresponding layer are formed in the first insulating part; the orthographic projection dimension of the second insulating part in the thickness direction of the signal connecting plate is larger than or equal to the orthographic projection dimension of the metal routing part in the first layer of metal wiring layer in the thickness direction of the signal connecting plate;
s609, forming a patterned metal wiring layer on the second insulating part in the first insulating layer to obtain a second metal wiring layer;
s611, forming an insulating layer on the second metal wiring layer to obtain a second insulating layer;
s613, repeating the step of forming the metal wiring layer and the step of forming the insulating layer;
and S615, when the formed metal wiring layers and the formed insulating layers meet the preset number of layers, releasing the sacrificial layers to obtain the signal connecting plate of the high-density brain electrode.
Wherein the signal connecting board of the high-density brain electrode is provided with a first connecting area, a second connecting area and a transition area positioned between the first connecting area and the second connecting area; the first connection area comprises a plurality of first sub-areas which are sequentially distributed along the direction from the first connection area to the second connection area, and the second connection area comprises a plurality of second sub-areas which are sequentially distributed along the direction from the second connection area to the first connection area. The front end connecting parts in each metal wiring layer in the multiple metal wiring layer layers are respectively positioned in the first sub-areas corresponding to the first connection areas, and the rear end connecting parts in each metal wiring layer are respectively positioned in the second sub-areas corresponding to the second connection areas.
The preset number of the metal wiring layers is related to the maximum channel number of each metal wiring layer and the total channel number of the front-end acquisition device. The number m of insulating layers is correlated with the number of metal wiring layers.
For example only, if the maximum number of channels of each metal wiring layer is the same and is 720 channels, and the total number of channels of the front-end collection device is 2160 channels, the number n of layers of the metal wiring layer is 3. In this embodiment, the maximum number of channels in each metal wiring layer is the same, that is, the number of Pad arrays in each metal wiring layer connected to the front-end acquisition device is the same. In other embodiments, the maximum number of channels in each metal wiring layer may not be completely the same, that is, the number of Pad arrays in each metal wiring layer connected to the front-end acquisition device is not completely the same.
In this embodiment, the signal connection board is prepared by multiple photolithography and metal patterning. Of course, in other embodiments, the compound can be prepared by other feasible methods.
In some embodiments, the number of layers of the metal wiring layer and the insulating layer is three. At this time, after the repeating of the step of forming the metal wiring layer and the step of forming the insulating layer and before the step of releasing the sacrifice layer, the method further includes:
forming a metal transition layer at the position of the opening in each insulating layer in the three-layer metal wiring layer; the center point of each transition pin in the metal transition layer is aligned with the center point of the corresponding silicon chip pin, and the size of each transition pin is larger than that of the corresponding silicon chip pin;
and the line width of each metal wiring on the first metal wiring layer, the second metal wiring layer and the third metal wiring layer is in a micrometer scale.
In some embodiments, the method further comprises:
forming metal bumps on the multiple metal transition layers; the metal bump comprises a lower metal adhesion layer, an intermediate metal bump layer and an upper metal welding point layer, wherein the lower metal adhesion layer is connected with the front end connecting part and/or the rear end connecting part, the intermediate metal bump layer is arranged between the lower metal adhesion layer and the upper metal welding point layer, and the upper metal welding point layer can be connected with the front end collecting device and/or the rear end circuit.
In some embodiments, the substrate is a flexible polymer such as, but not limited to, polyimide, polyethylene terephthalate, and the like.
The material of the metal wiring layer may be a noble metal or noble metal alloy, such as 5nm/100nm of chromium/gold, 30nm/150nm of chromium/gold, or the like.
The material of the insulating layer is flexible polymer, such as polyimide, polyethylene terephthalate, photoresist and the like.
It should be understood that the specific materials and thicknesses of the metal wiring layer and the insulating layer are not limited thereto, and may be adjusted accordingly according to actual conditions and requirements.
In one embodiment, the material of the metal transition layer is a noble metal or noble metal alloy, such as 30nm/30nm/150nm of chromium/nickel/gold, etc.
It should be understood that the specific material and thickness of the metal transition layer are not limited thereto, and can be adjusted accordingly according to the actual situation and requirement.
In some embodiments, the material of the lower metal adhesion layer may be metallic nickel, the material of the metal bump layer is metallic copper, and the material of the upper metal pad layer is lead-tin alloy. The thicknesses and materials of the lower metal adhesion layer, the middle metal bump layer and the upper metal pad layer are adjusted according to actual conditions, and the application is not particularly limited to this.
It should be noted that specific details and advantageous effects of the method embodiments may refer to the apparatus embodiments, and are not described herein again.
For the convenience of understanding, the following description will be made by taking the preparation of three metal wiring layers and three insulating layers, taking polyimide as a substrate and an insulating layer material as an example, and combining a specific preparation process diagram. As shown in fig. 7, the method of preparing the signal connection plate for the high-density brain electrode includes:
(a) selecting a single polished silicon wafer 70 with the thickness of 400 mu m, and cleaning;
(b) carrying out thermal oxidation on the silicon wafer to generate silicon dioxide with the thickness of 2 microns as a sacrificial layer 71;
(c) spin-coating a2 μm thick Polyimide (PI) 72;
(d) etching by using aluminum as a mask to form a substrate pattern and performing thermal curing;
(e) spin-coating a positive photoresist with the thickness of 0.5 mu m and carrying out photoetching to form a pattern of a first layer of metal;
(f) obtaining a Cr/Au metal layer with the thickness of 5nm/100nm on the photoresist obtained in the last step through metal evaporation;
(g) removing the photoresist by a lift-off process to obtain a first metal wiring layer 73;
(h) spin-coating PI with the thickness of 1 μm, and etching with aluminum as a mask to form a first insulating layer 74;
(i) spin-coating a positive photoresist with the thickness of 0.5 mu m and carrying out photoetching to form a pattern of a second layer of metal;
(j) obtaining a Cr/Au metal layer with the thickness of 5nm/100nm on the photoresist obtained in the last step through metal evaporation;
(k) removing the photoresist by a lift-off process to obtain a second metal wiring layer 75;
(l) Spin-coating PI with the thickness of 1 micron, and etching by using aluminum as a mask to form a second insulating layer 76;
(m) spin-coating a positive photoresist with the thickness of 0.5 mu m and carrying out photoetching to form a pattern of a third layer of metal;
(n) carrying out metal evaporation on the photoresist obtained in the last step to obtain a Cr/Au metal layer with the thickness of 5nm/100 nm;
(o) removing the photoresist by a lift-off process to obtain a third metal wiring layer 77;
(p) spin-coating PI with the thickness of 1 μm, and etching by using aluminum as a mask to form a third insulating layer 78;
(q) patterning by photolithography to form a pin pattern and evaporating the metal, removing the photoresist to form a 30nm/30nm/150nm metal transition layer 79 of chromium/nickel/gold, the metal transition layer comprising an array of transition pins (Pad);
(r) putting the flexible signal connecting plate into hydrofluoric acid to corrode silicon dioxide, and releasing the prepared flexible signal connecting plate.
In some embodiments, before step (r), after the preparation is completed, the release of silicon dioxide may not be performed temporarily, and a metal layer of nickel/copper/lead-tin alloy may be obtained on the connection board by metal evaporation to prepare a metal bump for subsequent thermocompression bonding with a device. Correspondingly, gold bumps are also prepared on the front-end acquisition device interconnected with the signal connecting plate, and the gold bumps and the front-end acquisition device are aligned and then are subjected to hot-press welding to complete the interconnection of the front-end acquisition device and the signal connecting plate; and generating solder bumps on the rear-end circuit through screen printing, and performing hot-press welding to complete interconnection of the rear-end circuit and the signal connecting plate.
The front-end connecting part in each layer of metal wiring layer in the signal connecting plate of the high-density brain electrode provided by the embodiment of the application is respectively positioned in different first sub-areas corresponding to the first connecting areas in the signal connecting plate, and the rear-end connecting part in each layer of metal wiring layer is respectively positioned in different second sub-areas corresponding to the second connecting areas in the signal connecting plate; an opening for exposing a silicon chip pin in the metal wiring layer of the corresponding layer is formed in the first insulating part in the insulating layer, and the orthographic projection size of the second insulating part in the thickness direction of the signal connecting plate is smaller than or equal to the orthographic projection size of the metal routing part in the adjacent lower metal wiring layer in the thickness direction of the signal connecting plate and larger than or equal to the orthographic projection size of the adjacent upper metal wiring layer in the thickness direction of the signal connecting plate. Therefore, by arranging the multiple layers of metal wiring layers and the multiple layers of insulating layers, and arranging the two adjacent layers of metal wiring layers at two sides of the second insulating part in the insulating layer between the two layers of metal wiring layers in a staggered manner, the number of channels which can be connected by the signal circuit board can be increased, the connection of the EEG signals of a single signal connecting plate, which reach 2160 channels or even more, can be realized, a good and feasible scheme is provided for the high-density brain-computer interface signal connection, and the universality is high.
In addition, the metal wiring layer on the signal connecting plate is prepared by utilizing a photoetching technology and through multiple photoetching and metal evaporation processes, the wiring line width of the circuit connecting plate can be reduced to the micron level, the distance between the electroencephalogram electrode signals is greatly reduced, the connection of the electroencephalogram signals at the micron level is met, the connection of the electroencephalogram signals of thousands of channels can be met, and a new solution is provided for the collection of the electroencephalogram electrode signals with high density and high flux.
The foregoing description has disclosed fully embodiments of the present application. It should be noted that those skilled in the art can make modifications to the embodiments of the present application without departing from the scope of the claims of the present application. Accordingly, the scope of the claims of the present application is not to be limited to the particular embodiments described above.
Claims (10)
1. A signal connecting board of a high-density brain electrode is characterized by comprising a first connecting area, a second connecting area and a transition area positioned between the first connecting area and the second connecting area; the first connecting area comprises a plurality of first sub-areas which are sequentially distributed along the direction from the first connecting area to the second connecting area, and the second connecting area comprises a plurality of second sub-areas which are sequentially distributed along the direction from the second connecting area to the first connecting area; the signal connecting board comprises a substrate, and a plurality of metal wiring layers and a plurality of insulating layers which are arranged on the substrate;
each layer of metal wiring layer comprises a front end connecting part, a metal routing part and a rear end connecting part which are sequentially connected, the front end connecting part comprises a first silicon chip pin, and the rear end connecting part comprises a second silicon chip pin; the front end connecting parts in each layer of metal wiring layer are respectively positioned in the corresponding different first sub-areas in the first connecting area, and the rear end connecting parts in each layer of metal wiring layer are respectively positioned in the corresponding different second sub-areas in the second connecting area;
each insulating layer is arranged on the corresponding metal wiring layer, each insulating layer comprises a first insulating part and a second insulating part, and the first insulating part is provided with an opening for exposing the first silicon chip pin and the second silicon chip pin in the corresponding metal wiring layer;
the orthographic projection dimension of the second insulating part in the thickness direction of the signal connecting plate is smaller than or equal to the orthographic projection dimension of the metal routing part in the adjacent lower metal wiring layer in the thickness direction of the signal connecting plate, and is larger than or equal to the orthographic projection dimension of the adjacent upper metal wiring layer in the thickness direction of the signal connecting plate.
2. The signal connection board according to claim 1, wherein the number of the metal wiring layers and the number of the insulating layers are three layers;
the outline shape of the second insulating part in each insulating layer is matched with the outline shape of the upper metal wiring layer covered on the second insulating part;
the line width of each metal wiring on the metal wiring layer is micrometer.
3. The signal connection board according to claim 1, wherein the first silicon chip pin is connected to a front-end acquisition device, and the second silicon chip pin is connected to a back-end circuit;
the distance between the adjacent first silicon chip pins is less than or equal to 0.5 mm; and/or
And the distance between the adjacent second silicon chip pins is less than or equal to 1 mm.
4. The signal connection board of any one of claims 1-3, further comprising a metal transition layer, the metal transition layer comprising:
one side of each first transition pin in the first transition part is connected with the corresponding first silicon chip pin in each metal wiring layer, and the other side of each first transition pin in the first transition part is used for being connected with a front-end acquisition device;
one side of each second transition pin in the second transition part is connected with the corresponding second silicon chip pin in each layer of metal wiring layer, and the other side of each second transition pin in the second transition part is used for being connected with a back-end circuit;
the size of each first transition pin is larger than that of the corresponding first silicon chip pin, and the size of each second transition pin is larger than that of the corresponding second silicon chip pin.
5. A signal connection board according to any one of claims 1-3, characterized in that the signal connection board further comprises metal bumps;
the metal bump is located the multilayer on the metal wiring layer, it includes metal adhesion layer, well metal bump layer and last metal solder joint layer down, down the metal adhesion layer with front end connecting portion and/or rear end connecting portion connect, well metal bump layer set up in down the metal adhesion layer with go up between the metal solder joint layer, it can be connected with front end acquisition device and/or rear end circuit to go up the metal solder joint layer.
6. Signal connection board according to claim 5,
the material of the substrate is a flexible polymer; and/or
The metal wiring layer is made of chromium/gold; and/or
The insulating layer is made of flexible polymer; and/or
The lower metal adhesion layer is made of metal nickel, the middle metal bump layer is made of metal copper, and the upper metal welding spot layer is made of lead-tin alloy.
7. A method for preparing a signal connecting plate of a high-density brain electrode is characterized by at least comprising the following steps:
providing a substrate, wherein a sacrificial layer is formed on the surface of the substrate;
forming a substrate with a preset shape on the surface of the sacrificial layer;
forming a patterned metal wiring layer on the substrate to obtain a first metal wiring layer; the first metal wiring layer comprises a front end connecting part, a metal routing part and a rear end connecting part which are sequentially connected, the front end connecting part comprises a first silicon chip pin, and the rear end connecting part comprises a second silicon chip pin;
forming an insulating layer on the first metal wiring layer to obtain a first insulating layer; the first insulating layer comprises a first insulating part and a second insulating part; openings for exposing the first silicon chip pins and the second silicon chip pins in the metal wiring layer of the corresponding layer are formed in the first insulating part; the orthographic projection size of the second insulating part in the thickness direction of the signal connecting plate is smaller than or equal to the orthographic projection size of the metal routing part in the first layer of metal wiring layer in the thickness direction of the signal connecting plate;
forming a patterned metal wiring layer on the second insulating part in the first insulating layer to obtain a second metal wiring layer;
forming an insulating layer on the second metal wiring layer to obtain a second insulating layer;
repeating the step of forming the metal wiring layer and the step of forming the insulating layer;
and when the formed metal wiring layer and the formed insulating layer meet the preset number of layers, releasing the sacrificial layer to obtain the signal connecting plate of the high-density brain electrode.
8. The method according to claim 7, wherein the number of layers of the metal wiring layer and the insulating layer is three, respectively, and the method further comprises, after the repeating of the step of forming the metal wiring layer and the step of forming the insulating layer and before the step of releasing the sacrificial layer:
forming a metal transition layer at the position of the opening in each insulating layer in the three-layer metal wiring layer; the center point of each transition pin in the metal transition layer is aligned with the center point of the corresponding silicon chip pin, and the size of each transition pin is larger than that of the corresponding silicon chip pin;
and the line width of each metal wiring on the first metal wiring layer, the second metal wiring layer and the third metal wiring layer is in a micrometer scale.
9. The method of claim 8, further comprising:
forming metal bumps on the multiple metal transition layers; the metal bump comprises a lower metal adhesion layer, an intermediate metal bump layer and an upper metal welding point layer, wherein the lower metal adhesion layer is connected with the front end connecting part and/or the rear end connecting part, the intermediate metal bump layer is arranged between the lower metal adhesion layer and the upper metal welding point layer, and the upper metal welding point layer can be connected with the front end collecting device and/or the rear end circuit.
10. An electronic device, comprising the signal connecting board for the high-density brain electrode according to any one of claims 1 to 6, or the signal connecting board prepared by the method for preparing the signal connecting board for the high-density brain electrode according to any one of claims 7 to 9.
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| CN114406515A (en) * | 2022-01-28 | 2022-04-29 | 中国科学院上海微系统与信息技术研究所 | Welding method of brain electrode device and brain electrode device |
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