CN112018092A - 半导体设备封装和其制造方法 - Google Patents

半导体设备封装和其制造方法 Download PDF

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CN112018092A
CN112018092A CN201910653302.1A CN201910653302A CN112018092A CN 112018092 A CN112018092 A CN 112018092A CN 201910653302 A CN201910653302 A CN 201910653302A CN 112018092 A CN112018092 A CN 112018092A
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substrate
disposed
semiconductor device
device package
dielectric layer
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黄文宏
黄敏龙
苏育贤
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体设备封装包含第一衬底、天线、支撑层、介电层和第二衬底。所述第一衬底具有第一表面和与所述第一表面相对的第二表面。所述天线元件安置于所述第一衬底的所述第二表面上。所述支撑层安置于所述第一衬底的所述第一表面上和所述第一衬底的所述第一表面的外围处。所述支撑层具有背对所述第一衬底的第一表面。所述介电层安置于所述支撑层的所述第一表面上并且与所述第一衬底间隔开。所述介电层以化学方式键合到所述支撑层。所述第二衬底安置于所述介电层的背对所述支撑层的第一表面上。

Description

半导体设备封装和其制造方法
技术领域
本公开涉及一种半导体设备封装和其制造方法，且更具体地说，涉及一种包含天线的半导体设备封装和其制造方法。
背景技术
移动通信的发展已引起对于高数据速率和稳定通信质量的需求，且高频无线传输(例如，28GHz或60GHz)已变成移动通信行业中的一个最重要的课题。为了实现此类高频无线传输，可在波长为约十毫米到约一毫米的(“毫米波”或“mm波”)的频带中传输信号。然而，毫米波传输的问题中的一个是信号衰减。
发明内容
根据本公开的一些实施例，一种半导体设备封装包含第一衬底、天线、支撑层、介电层和第二衬底。所述第一衬底具有第一表面和与所述第一表面相对的第二表面。所述天线元件安置于所述第一衬底的所述第二表面上。所述支撑层安置于所述第一衬底的所述第一表面上和所述第一衬底的所述第一表面的外围处。所述支撑层具有背对所述第一衬底的第一表面。所述介电层安置于所述支撑层的所述第一表面上并且与所述第一衬底间隔开。所述介电层以化学方式键合到所述支撑层。所述第二衬底安置于所述介电层的背对所述支撑层的第一表面上。
根据本公开的一些实施例，一种半导体设备封装包含第一衬底、天线元件、第二衬底和发泡剂。所述第一衬底具有第一表面和与所述第一表面相对的第二表面。所述天线元件安置于所述第一衬底的所述第二表面上。所述第二衬底安置于所述第一衬底上。所述第一衬底和所述第二衬底界定腔。所述发泡剂安置于所述腔内。
根据本公开的一些实施例，一种用于制造半导体设备封装的方法包含(a)预固化第一衬底上的第一光敏元件；(b)预固化第二衬底上的第二光敏元件；(c)将所述第一光敏元件附接到所述第二光敏元件；和(d)完全固化所述第一光敏元件和所述第二光敏元件。
附图说明
图1说明根据本公开的一些实施例的半导体设备封装的横截面图。
图2说明根据本公开的一些实施例的半导体设备封装的横截面图。
图3A、图3B、图3C、图3D、图3E和图3F说明根据本公开的一些实施例的半导体制造方法。
图4A、图4B和图4C说明根据本公开的一些实施例的半导体制造方法。
图5A、图5B和图5C说明根据本公开的一些实施例的半导体制造方法。
在整个图式和详细描述中使用共同参考标号来指示相同或相似组件。根据以下结合附图作出的详细描述将容易理解本公开。
具体实施方式
图1说明根据本公开的一些实施例的半导体设备封装1的横截面图。半导体设备封装1包含衬底10、12、介电层11、天线元件13、电子组件14、电接点15和封装体16。
衬底10可以是例如印刷电路板，例如纸基铜箔层合物、复合铜箔层合物或聚合物浸渍的玻璃纤维基铜箔层合物。在一些实施例中，衬底10可为单层衬底或多层衬底。衬底10具有表面101和与表面101相对的表面102。
天线辐射方向图13安置于衬底10的表面102上。在一些实施例中，天线辐射方向图13穿透衬底10并且从衬底10的表面101暴露。在一些实施例中，天线辐射方向图13包含多个天线元件。举例来说，天线辐射方向图13可包含天线元件阵列。在一些实施例中，天线辐射方向图13可包含M×N天线元件阵列，其中M和N是大于0的整数。在一些实施例中，天线辐射方向图13由金(Au)、银(Ag)、铜(Cu)、铂(Pt)、钯(Pd)、其它金属或合金或其两个或多个的组合形成或包含金(Au)、银(Ag)、铜(Cu)、铂(Pt)、钯(Pd)、其它金属或合金或其两个或多个的组合。
介电层11安置于衬底10的表面101上。介电层11具有表面111、112、113和114。表面111背对衬底10。表面112连接到衬底10的表面101。表面113面对衬底10并且与衬底10间隔开。表面114在表面112与表面113之间延伸。介电层11具有安置于衬底10的表面101上的部分11a(还可称为“支撑元件”)和安置于部分11a上的部分11b。在一些实施例中，介电层11的部分11a以化学方式键合到介电层11的部分11b。部分11a安置于衬底10的表面101的外围处。在一些实施例中，介电层11和衬底10界定腔10c(或室)。举例来说，介电层11的部分11b界定腔10c的上部部分，衬底10界定腔10c的下部部分，且介电层11的部分11a界定腔10c的侧壁。举例来说，介电层11的表面113界定腔10c的上表面，衬底10的表面101界定腔10c的下表面，且介电层11的表面114界定腔10c的侧壁。
介电层11可包含安置于其中的导电层11r。在一些实施例中，导电层11r穿透介电层11的部分11b并且从介电层11的表面111和表面113暴露以用于电连接。导电元件10p(例如，铜柱)安置于腔10c内并且将天线辐射方向图13电连接到导电层11r。导电元件10p是或包含导电材料，例如金属或金属合金。导电材料的实例包含Au、Ag、Cu、Pt、Pd或其合金。在一些实施例中，可省略导电元件10p，且可在天线辐射方向图13与导电层11r之间通过耦合来传输信号。
在一些实施例中，介电层11包含光敏材料。举例来说，介电层11包含膨化聚烯烃(EPO)、防焊剂、聚酰亚胺(PI)、环氧树脂和/或聚苯并恶唑(PBO)。在一些实施例中，介电层11的部分11a和部分11b由相同材料形成。替代地，介电层11的部分11a和部分11b由不同材料形成。
衬底12安置于介电层11的表面111上。衬底12可以是例如印刷电路板，例如纸基铜箔层合物、复合铜箔层合物或聚合物浸渍的玻璃纤维基铜箔层合物。衬底12可包含互连结构12r，例如重布层(RDL)或接地元件。在一些实施例中，互连结构12r的一部分从衬底12暴露以电连接到介电层11的导电层11r。互连结构12r是或包含导电材料，例如金属或金属合金。导电材料的实例包含Au、Ag、Cu、Pt、Pd或其合金。在一些实施例中，衬底12可为单层衬底或包含核心层和导电材料的多层衬底。导电材料和/或结构可包含多个迹线。衬底12可包含接近、邻近或嵌入于衬底12的表面121处中并且在所述表面121处暴露的一或多个导电垫12c。衬底12可包含衬底12的表面121上的防焊剂12m(或焊料掩模)以完全暴露或暴露导电垫12c的至少一部分以用于电连接。举例来说，防焊剂12m可覆盖导电垫12c的一部分。
电子组件14安置于衬底12的表面121上并且电连接到衬底12的导电垫12c。电子组件14可为主动电子组件，例如集成电路(IC)芯片或裸片。在一些实施例中，导电垫12c直接连接到电子组件14的主动表面的导电端子(例如，铜柱)。在其它实施例中，电子组件14可借助于倒装芯片或导线接合技术电连接到衬底12。
电接点15安置于衬底12上(例如，衬底12的导电垫上)以提供半导体设备封装1与任何其它电路板(例如，衬底、PCB、主板等)或电路之间的电连接。在一些实施例中，电接点15是焊料球或导电柱。
封装体16安置于衬底12上并且覆盖或包封电子组件14和电接点15的一部分。电子组件14的背表面从封装体16暴露。在一些实施例中，电子组件14的背表面与封装体16的表面162大体上共平面。电接点15的一部分从封装体16暴露以用于电连接。在一些实施例中，封装体16包含具有填料的环氧树脂、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、具有硅酮分散在其中的材料，或其组合。
如图1中所示出，由于介电层11和衬底10被布置成界定其间的高度、距离、一或多个空腔(例如空气腔)，因此可改进天线辐射方向图13的增益、带宽和辐射效率。在一些实施例中，空腔10c可为真空腔(或真空室)或近真空腔，这可防止归因于在热处理期间空气膨胀引起的衬底10与介电层11或衬底12之间的脱层且继而增加半导体设备封装1的可靠性。
图2说明根据本公开的一些实施例的半导体设备封装2的横截面图。半导体设备封装2类似于图1中的半导体设备封装1，且在下文描述其间的差异。
支撑结构22安置于衬底10的表面101上。支撑结构22安置于衬底10的表面101的外围处。支撑结构22、衬底10和衬底12界定腔20c。在一些实施例中，支撑结构22可为如图1中所示的介电层11。替代地，支撑结构22可以是或包含任何其它合适的材料，例如防焊剂。支撑结构22通过粘附层21(例如，裸片附接膜(DAF)或带)连接到衬底12。在一些实施例中，导电元件10p可穿透粘附层21以电连接所述互连结构12r。在一些实施例中，粘附层21可包含导电材料。举例来说，粘附层21的至少一部分(例如，对应于导电元件10的部分)为导电的以提供衬底12与导电元件10p之间的电连接。
发泡剂23安置于腔20c内。发泡剂23被支撑结构22环绕。在一些实施例中，发泡剂23由具有小于电介质材料的介电常数(Dk)和耗散因子(Df)的Dk和DF的材料形成或包含具有小于电介质材料的介电常数(Dk)和耗散因子(Df)的Dk和DF的材料。举例来说，发泡剂23的Df等于或小于3，且发泡剂23的Df等于或小于0.001。
根据图2中的实施例，由于形成剂23的Dk和Df小于电介质材料的Dk和Df，因此可改进天线辐射方向图13的增益、带宽和辐射效率。另外，发泡剂23安置于腔20c内以覆盖腔20c内的空气，这可防止归因于在热处理期间空气膨胀引起的衬底10与支撑结构22或衬底12之间的脱层且继而增加半导体设备封装2的可靠性。
图3A、图3B、图3C、图3D、图3E和图3F说明根据本公开的一些实施例的半导体制造方法。
参考图3A，提供具有粘附层39h的载体39。衬底10安置于载体39的两个表面上。在一些实施例中，可通过例如层合安置衬底10。形成穿透衬底10的一或多个开口10h以暴露载体39(或粘附层39h)的一部分。在一些实施例中，可通过例如钻孔、蚀刻或任何其它合适的过程形成开口10h。图案化光致抗蚀剂39p(或光掩模)接着安置于衬底10上。
参考图3B，天线辐射方向图13形成于衬底10上和开口10h内。在一些实施例中，由图案化光致抗蚀剂39p界定天线辐射方向图13。举例来说，天线辐射方向图13形成于从图案化光致抗蚀剂39p暴露的位置处。在一些实施例中，通过例如湿式工艺或任何其它合适的工艺形成天线辐射方向图13。接着移除光致抗蚀剂39p。
参考图3C，从衬底10移除载体39和粘附层39h以暴露衬底10的表面101和天线辐射方向图13的一部分。
参考图3D，图案化光致抗蚀剂39p1(或光掩模)安置于衬底10的表面101上。图案化光致抗蚀剂39p1具有一或多个开口39ph以暴露天线辐射方向图13。
参考图3E，导电元件10p通过例如湿式工艺形成于由图案化光致抗蚀剂39p1界定的开口39ph内。移除图案化光致抗蚀剂39p1。接着，介电层11a形成于衬底10的表面101上。介电层11a和衬底10的表面101界定腔10c。在一些实施例中，如图3F中所示，发泡剂23接着填充于腔10c内。
图4A、图4B和图4C说明根据本公开的一些实施例的半导体制造方法。在一些实施例中，图4A、图4B和图4C中说明的方法用以制造图1中的半导体设备封装1。
参考图4A，提供如图3E中所示的结构和其上具有衬底12的介电层11b。将第一温度提供给介电层11a以加热(或软烘烤或预固化)介电层11a(例如，软焙烤工艺或预固化工艺)。将第二温度提供给介电层11b以加热(或软烘烤或预固化)介电层11b(例如，软焙烤工艺或预固化工艺)。在一些实施例中，取决于不同设计要求，所述第一温度可等于、大于或小于所述第二温度。
参考图4B，介电层11b附接到介电层11a。接着，将第三温度提供给介电层11a和11b以加热(硬烘焙或完全固化)介电层11a和11b(例如，硬焙烤工艺或完全固化工艺)，使得介电层11a粘合到介电层11b。根据图4B中的实施例，介电层11a通过化学键连接到介电层11b，这可提供介电层11a与介电层11b之间的更佳粘合强度。
参考图4C，电子组件14安置于衬底12上。电子组件14电连接到衬底12的导电垫12c。在一些实施例中，电接点15可安置于衬底12上，并且接着封装体16可形成于衬底12上以形成如图1中所示的半导体设备封装1。
图5A、图5B和图5C说明根据本公开的一些实施例的半导体制造方法。在一些实施例中，图5A、图5B和图5C中说明的方法用以制造图2中的半导体设备封装2。
参考图5A，提供如图3F中所示的结构和具有粘附层21的衬底12。如图5B中所示，衬底12接着通过粘附层21附接到介电层11a。
参考图5C，电子组件14安置于衬底12上。电子组件14电连接到衬底12的导电垫12c。在一些实施例中，电接点15可安置于衬底12上，并且接着封装体16可形成于衬底12上以形成如图2中所示的半导体设备封装2。
如本文中所使用，术语“基本上”、“基本”、“近似”和“约”用于指示和解释小的变化。举例来说，当结合数值使用时，术语可指代小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。作为另一实例，膜或层的厚度“基本上均匀”可指膜或层的平均厚度的小于或等于±10％的标准偏差，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。术语“基本上共面”可指两个表面在数微米内沿同一平面延伸，例如在40μm内、30μm内、20μm内、10μm内或1μm内沿同一平面延伸。如果两个表面或组件之间的角为例如90°±10°，例如±5°、±4°、±3°、±2°、±1°、±0.5°、±0.1°或±0.05°，那么这两个表面或组件可被认为“基本上垂直”。当结合事件或情况使用时，术语“基本上”、“基本”、“近似地”和“约”可指其中事件或情况精确出现的例子，以及其中事件或情况非常近似出现的例子。
如本文中所使用，除非上下文另外明确规定，否则单数术语“一(a/an)”和“所述”可包含多个指示物。在一些实施例的描述中，提供于另一组件“上”或“上方”的组件可涵盖前一组件直接在后一组件上(例如，与后一组件物理接触)的情况，以及一或多个中间组件位于前一组件与后一组件之间的情况。
如本文所使用，术语“导电”、“导电性”和“导电率”指代输送电流的能力。导电性材料通常指示对电流流动呈现极少或零对抗的那些材料。导电率的一个量度是每米西门子(S/m)。通常，导电性材料是导电率大于约104S/m(例如至少105S/m或至少106S/m)的一种材料。材料的导电率有时可随温度变化。除非另外规定，否则在室温下测量材料的导电率。
另外，有时在本文中按范围格式呈现量、比率和其它数值。应理解，此类范围格式是为了便利和简洁，且应灵活地理解，不仅包含明确地指定为范围极限的数值，而且包含涵盖于所述范围内的所有个别数值或子范围，如同明确地指定每一数值和子范围一般。
尽管已参考本公开的特定实施例描述并说明本公开，但这些描述和说明并不限制本公开。所属领域的技术人员可清楚地理解，可进行各种改变，且可在实施例内替代等效元件而不脱离如由所附权利要求书定义的本公开的真实精神和范围。所述图示可能未必按比例绘制。归因于制造过程中的变量等等，本公开中的技术再现与实际设备之间可能存在区别。可存在并未特定说明的本公开的其它实施例。应将所述说明书和图式视为说明性的，而非限制性的。可做出修改，以使特定情况、材料、物质组成、方法或过程适应于本公开的目标、精神以及范围。所有此类修改意图在所附权利要求书的范围内。虽然已参考按特定次序执行的特定操作描述本文中所公开的方法，但应理解，可在不脱离本公开的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序和分组不受本公开限制。

Claims (20)

1.一种半导体设备封装，其包括：
第一衬底，其具有第一表面和与所述第一表面相对的第二表面；
天线元件，其安置于所述第一衬底的所述第二表面上；
支撑层，其安置于所述第一衬底的所述第一表面上和所述第一衬底的所述第一表面的外围处，所述支撑层具有背对所述第一衬底的第一表面；
介电层，其安置于所述支撑层的所述第一表面上并且与所述第一衬底间隔开，其中所述介电层以化学方式键合到所述支撑层；和
第二衬底，其安置于所述介电层的背对所述支撑层的第一表面上。
2.根据权利要求1所述的半导体设备封装，其中
所述介电层另外包含与所述第一表面相对的第二表面；
所述支撑层包含内表面；且
所述支撑层的所述内表面、所述介电层的所述第二表面和所述第一衬底的所述第一表面界定腔。
3.根据权利要求1所述的半导体设备封装，其中所述介电层和所述支撑层包含光敏材料。
4.根据权利要求3所述的半导体设备封装，其中所述介电层和所述支撑包含膨化聚烯烃EPO、防焊剂、聚酰亚胺PI、环氧树脂和/或聚苯并恶唑PBO。
5.根据权利要求1所述的半导体设备封装，其中所述天线元件穿透所述第一衬底并且通过导电元件电连接到所述第二衬底。
6.根据权利要求5所述的半导体设备封装，其中所述导电元件安置于所述腔内。
7.根据权利要求1所述的半导体设备封装，其另外包括安置于所述第二衬底上的电子组件。
8.一种半导体设备封装，其包括：
第一衬底，其具有第一表面和与所述第一表面相对的第二表面；
天线元件，其安置于所述第一衬底的所述第二表面上；
第二衬底，其安置于所述第一衬底的所述第一表面上，所述第一衬底和所述第二衬底界定腔；和
发泡剂，其安置于所述腔内。
9.根据权利要求8所述的半导体设备封装，其另外包括安置于所述第一衬底与所述第二衬底之间并且环绕所述发泡剂的支撑元件。
10.根据权利要求9所述的半导体设备封装，其另外包括安置于所述支撑元件与所述第二衬底之间的粘附层。
11.根据权利要求8所述的半导体设备封装，其中所述天线元件穿透所述第一衬底并且通过导电元件电连接到所述第二衬底。
12.根据权利要求11所述的半导体设备封装，其中所述导电元件安置于所述腔内。
13.根据权利要求8所述的半导体设备封装，其另外包括安置于所述第二衬底上的电子组件。
14.一种用于制造半导体设备封装的方法，所述方法包括：
(a)预固化第一衬底上的第一光敏元件；
(b)预固化第二衬底上的第二光敏元件；
(c)将所述第一光敏元件附接到所述第二光敏元件；和
(d)完全固化所述第一光敏元件和所述第二光敏元件。
15.根据权利要求14所述的方法，在操作(a)中，其另外包括提供第一温度以软烘烤所述第一光敏元件。
16.根据权利要求14所述的方法，在操作(b)中，其另外包括提供第二温度以软烘烤所述第二光敏元件。
17.根据权利要求14所述的方法，在操作(d)中，其另外包括提供第三温度以硬烘焙所述第一光敏元件和所述第二光敏元件。
18.根据权利要求14所述的方法，其中所述预固化的加热温度小于所述完全固化的加热温度。
19.根据权利要求14所述的方法，在操作(c)中，其另外包括形成由所述第一光敏元件和所述第二光敏元件界定的腔。
20.根据权利要求14所述的方法，其中所述第一光敏元件和所述第二光敏元件包含膨化聚烯烃EPO、防焊剂、聚酰亚胺PI、环氧树脂和/或聚苯并恶唑PBO。
CN201910653302.1A 2019-05-29 2019-07-19 半导体设备封装和其制造方法 Pending CN112018092A (zh)

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US7696930B2 (en) 2008-04-14 2010-04-13 International Business Machines Corporation Radio frequency (RF) integrated circuit (IC) packages with integrated aperture-coupled patch antenna(s) in ring and/or offset cavities
US8706049B2 (en) * 2008-12-31 2014-04-22 Intel Corporation Platform integrated phased array transmit/receive module
US8988299B2 (en) 2011-02-17 2015-03-24 International Business Machines Corporation Integrated antenna for RFIC package applications
WO2013147744A1 (en) 2012-03-26 2013-10-03 Intel Corporation Integration of millimeter wave antennas on microelectronic substrates
US9711465B2 (en) * 2012-05-29 2017-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Antenna cavity structure for integrated patch antenna in integrated fan-out packaging
US9252491B2 (en) * 2012-11-30 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Embedding low-k materials in antennas
KR102003840B1 (ko) * 2018-03-12 2019-07-25 삼성전자주식회사 안테나 모듈
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