CN112017585B - Shift register and driving method thereof, grid driving circuit and display device - Google Patents
Shift register and driving method thereof, grid driving circuit and display device Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The present invention provides a shift register, comprising: the device comprises a transmission circuit, a first gating circuit, an input and compensation circuit, a first output circuit and a noise reduction circuit; the transmission circuit is connected with the input and compensation circuit, the transmission circuit, the noise reduction circuit and the first output circuit are connected with the second node, the first gating circuit, the input and compensation circuit and the noise reduction circuit are connected with the third node, the noise reduction circuit and the input and compensation circuit are connected with the fourth node, and the input and compensation circuit and the first output circuit are connected with the output end of the shift register; the transmission circuit is configured to turn on or off the first node and the second node; the first gating circuit is configured to transmit a second voltage signal provided by the second voltage terminal to the third node; the input and compensation circuit is configured to provide an active level signal to the first node and the fourth node during an output phase of the shift register. The invention also provides a driving method of the shift register, a grid driving circuit and a display device.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, a gate driving circuit, and a display device.
Background
In the existing shift register, the threshold drift problem of the adopted transistor is unavoidable, and when the threshold drift of the transistor is serious, the pull-up node is leaked in the output stage, so that the output of the shift register is affected.
Disclosure of Invention
The invention aims to at least solve one of the technical problems in the prior art, and provides a shift register, a driving method thereof, a grid driving circuit and a display device.
In order to achieve the above object, the present invention provides a shift register, comprising: the device comprises a transmission circuit, a first gating circuit, an input and compensation circuit, a first output circuit and a noise reduction circuit; one end of the transmission circuit is connected with the input and compensation circuit and is connected with a first node, the other end of the transmission circuit, the first end of the noise reduction circuit and the first output circuit are connected with a second node, the first gating circuit, the input and compensation circuit and the second end of the noise reduction circuit are connected with a third node, the third end of the noise reduction circuit and the input and compensation circuit are connected with a fourth node, and the input and compensation circuit and the first output circuit are connected with the output end of the shift register;
the transmission circuit is configured to: switching the first node on or off from the second node in response to control of a potential difference between a first clock signal terminal and the first node;
the first output circuit is configured to: transmitting a clock signal of a second clock signal terminal to an output terminal of the shift register in response to control of the potential of the second node;
the first gating circuit is configured to: transmitting a second voltage signal provided by a second voltage terminal to the third node in response to control of the potential of the first clock signal terminal;
the noise reduction circuit is configured to: switching on or off the fourth node and the second node in response to a potential difference between the third node and the fourth node and control of a potential of the second clock signal terminal;
the input and compensation circuit is configured to: transmitting a signal of an input terminal of the shift register to the first node and transmitting a first voltage signal provided by a first voltage terminal to the fourth node in an input stage and a first noise reduction stage of the shift register in response to potential control of the first clock signal terminal and the third node; in an output stage of the shift register, an active level signal is supplied to the first node and the fourth node.
Optionally, the shift register further includes a second output circuit, and the second output circuit is connected to the third node;
the second output circuit is configured to: and transmitting a first voltage signal provided by the first voltage terminal to an output terminal of the shift register in response to control of the potential of the third node.
Optionally, the shift register further includes: a second gating circuit connected between the second node and the third node;
the second gating circuit is configured to: the second node is turned on or off from the third node in response to control of the potential of the second node.
Optionally, the input and compensation circuit comprises: an input transistor, a first compensation transistor, a second compensation transistor, and a third compensation transistor;
the grid electrode of the input transistor is connected with the first clock signal end, the first electrode of the input transistor is connected with the input end of the shift register, and the second electrode of the input transistor is connected with the first node;
the grid electrode and the second electrode of the first compensation transistor are connected with the output end of the shift register, and the first electrode of the first compensation transistor is connected with the first node;
the grid electrode of the second compensation transistor is connected with the third node, the first electrode of the second compensation transistor is connected with the first voltage end, and the second electrode of the second compensation transistor is connected with the fourth node;
the grid electrode and the second electrode of the third compensation transistor are both connected with the output end of the shift register, and the first electrode of the third compensation transistor is connected with the fourth node.
Optionally, the transmission circuit includes: and the grid electrode of the transmission transistor is connected with the first clock signal end, the first electrode of the transmission transistor is connected with the first node, and the second electrode of the transmission transistor is connected with the second node.
Optionally, the first output circuit includes: a first output transistor and a first capacitor;
the grid electrode of the first output transistor is connected with the second node, the first electrode of the first output transistor is connected with the second clock signal end, and the second electrode of the first output transistor is connected with the output end of the shift register;
one end of the first capacitor is connected with the grid electrode of the first output transistor, and the other end of the first capacitor is linked with the second pole of the first output transistor.
Optionally, the noise reduction circuit includes a first noise reduction transistor and a second noise reduction transistor;
the grid electrode of the first noise reduction transistor is connected with the third node, the first pole of the first noise reduction transistor is connected with the fourth node, and the second pole of the first noise reduction transistor is connected with the first pole of the second noise reduction transistor;
and the grid electrode of the second noise reduction transistor is connected with the second clock signal end, and the second pole of the second noise reduction transistor is connected with the second node.
Optionally, the first gating circuit includes: and the grid electrode of the first gating transistor is connected with the first clock signal end, the first electrode of the first gating transistor is connected with the second voltage end, and the second electrode of the first gating transistor is connected with the third node.
Optionally, the second output circuit includes: a second output transistor and a second capacitor;
the grid electrode of the second output transistor is connected with the third node, the first electrode of the second output transistor is connected with the first voltage end, and the second electrode of the second output transistor is connected with the output end of the shift register;
one end of the second capacitor is connected with the grid electrode of the second output transistor, and the other end of the second capacitor is connected with the first pole of the second output transistor.
Optionally, the second gating circuit includes: and the grid electrode of the second gating transistor is connected with the second node, the first electrode of the second gating transistor is connected with the first clock signal end, and the second electrode of the second gating transistor is connected with the third node.
The invention also provides a driving method applied to the shift register, wherein the driving method comprises the following steps:
in an input stage, providing an effective level signal to the first clock signal end and the input end of the shift register so that the input and compensation circuit transmits the signal of the input end of the shift register to the first node, and the transmission circuit conducts the first node with the second node;
in an output stage, an invalid level signal is provided for the first clock signal end, an effective level signal is provided for the second clock signal end, so that the input and compensation circuit provides the effective level signal for the first node and the fourth node, the transmission circuit disconnects the first node from the second node, and the noise reduction circuit disconnects the fourth node from the second node;
in a first noise reduction stage, an effective level signal is provided for the first clock signal end, an ineffective level signal is provided for the second clock signal end and the input end of the shift register, so that the first gating circuit transmits a second voltage signal provided by a second voltage end to the third node, the input and compensation circuit transmits a signal of the input end of the shift register to the first node, and the transmission circuit conducts the first node and the second node;
in the second noise reduction stage, an invalid level signal is provided for the first clock signal end, an effective level signal is provided for the second clock signal end, so that the input and compensation circuit transmits a first voltage signal provided by the first voltage end to the fourth node, and the noise reduction circuit conducts the fourth node with the second node.
The present invention also provides a gate driving circuit, including: the shift register.
The invention also provides a display device, which comprises the gate driving circuit.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the description serve to explain, without limitation, the invention. In the drawings:
fig. 1 is a schematic diagram of a shift register in a comparative example;
FIG. 2 is a schematic diagram of a shift register according to an embodiment of the present invention;
FIG. 3 is a timing diagram of driving a shift register according to an embodiment of the present invention;
fig. 4a to fig. 4d are schematic diagrams illustrating transistor states of a shift register at different stages according to an embodiment of the present invention.
Detailed Description
The following describes specific embodiments of the present invention in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
Unless defined otherwise, technical or scientific terms used in the embodiments of the present invention should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present invention belongs. The terms "first," "second," and the like, as used herein, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
Fig. 1 is a schematic diagram of a shift register in a comparative example, and as shown in fig. 1, the shift register includes: the first input transistor T1, the first output transistor T2, the second input transistor T3, the second output transistor T4, the first gate transistor T5, the second gate transistor T6, the third gate transistor T7, the first capacitor C1 'and the second capacitor C2'. The first input transistor T1, the first output transistor T2, the first gate transistor T5, and the second gate transistor T6 are connected to the first node N1', and the second input transistor T3, the second output transistor T4, the first gate transistor T5, and the third gate transistor T7 are connected to the second node N2'.
The first input transistor T1 is configured to: the first voltage terminal VL is turned on with the first node N1' in response to the control of the first clock signal terminal CK. The first output transistor T2 is configured to: the second voltage terminal VH is turned on with the output terminal GO in response to control of the potential of the first node N1'. The second input transistor T3 is configured to: in response to the control of the first clock signal terminal CK, the input terminal GI is turned on with the second node N2'. The second output transistor T4 is configured to: the second clock signal terminal CB is turned on with the output terminal GO in response to the control of the potential of the second node N2'. The first gate transistor T5 is configured to: the first clock signal terminal CK is turned on with the first node N1 'in response to control of the potential of the second node N2'. The second gating transistor T6 is configured to: in response to the control of the potential of the first node N1', the second voltage terminal VH is turned on with the third gate transistor T7, and the third gate transistor T7 is configured to: the second gating transistor T6 is turned on with the second node N2' in response to the control of the second clock signal terminal CB.
With the shift register with the above structure, in the input stage, the first clock signal terminal CK and the input terminal GI are provided with the active level signal, the second clock signal terminal CB is provided with the inactive level signal, the second input transistor T3 is turned on, the active level signal of the input terminal GI is transmitted to the second node N2', the first gate transistor T5 is turned on, and the active level signal of the first clock signal terminal CK is transmitted to the first node N1'.
In the output stage, an inactive level signal is provided to the first clock signal terminal CK and the input terminal GI, the second clock signal terminal CB provides an active level signal, the third gate transistor T7 is turned on, and at the same time, the second node N2 'is still an active level signal, the first gate transistor T5 is turned on, and the inactive level signal of the first clock signal terminal CK is transmitted to the first node N1'. At this time, the gate and the source of the second input transistor T3 are both inactive level signals, the gate and the source of the second gate transistor T6 are also inactive level signals, that is, the gate-source voltages vgs=0 of the second input transistor T3 and the second gate transistor T6, but when the threshold voltages of the second input transistor T3 and the second gate transistor T6 drift, the second input transistor T3 and the second gate transistor T6 cannot be completely turned off, the second node N2 'will leak through the second input transistor T3 (i.e., the inactive level signal of the input terminal is transmitted to the second node N2'), and the second node N2 'will leak through the third gate transistor T7 and the second gate transistor T6 (i.e., the inactive level signal of the second voltage terminal VH is transmitted to the second node N2'), which will result in output failure of the shift register when serious.
It should be noted that, the transistors in the shift register may be N-type transistors or P-type transistors, and when the transistors are N-type transistors, the negative drift of the threshold voltage of the transistors will cause the transistors to be unable to be completely turned off; when the transistor is a P-type transistor, the forward shift of the threshold voltage of the transistor will not completely turn off. Specifically, taking the P-type transistors as examples of each transistor in the shift register, when the threshold voltages of the second input transistor T3 and the second gate transistor T6 drift forward, in the output stage, since the gate-source voltages vgs=0 of the second input transistor T3 and the second gate transistor T6, the difference between the gate-source voltages Vgs of the second input transistor T3 and the second gate transistor T6 and the threshold voltage Vth may be less than zero, which may result in that the second input transistor T3 and the second gate transistor T6 cannot be completely turned off.
In view of the foregoing, an embodiment of the present invention provides a shift register, and fig. 2 is a schematic diagram of the shift register provided in the embodiment of the present invention, as shown in fig. 2, the shift register includes: a transmission circuit 1, a first gating circuit 2, an input and compensation circuit 3, a first output circuit 4 and a noise reduction circuit 5. One end of the transmission circuit 1 is connected with the input and compensation circuit 3 at a first node N1, the other end of the transmission circuit 1, the first end of the noise reduction circuit 5 and the first OUTPUT circuit 4 are connected with a second node N2, the second ends of the first gating circuit 2, the input and compensation circuit 3 and the noise reduction circuit 5 are connected with a third node N3, the third end of the noise reduction circuit 5 and the input and compensation circuit 3 are connected with a fourth node N4, and the input and compensation circuit 3 and the first OUTPUT circuit 4 are connected with an OUTPUT end OUTPUT of the shift register.
In an embodiment of the present invention, the operation stages of the shift register include an input stage, an output stage, a first noise reduction stage, and a second noise reduction stage, and the transmission circuit 1 is configured to: in response to the control of the potential difference between the first clock signal terminal CLK and the first node N1, the first node N1 and the second node N2 are turned on in the input phase, and the first node N1 and the second node N2 are turned off in the output phase.
The first output circuit 4 is configured to: in response to the control of the potential of the second node N2, in the OUTPUT stage, the clock signal of the second clock signal terminal CLKB is transmitted to the OUTPUT terminal OUTPUT of the shift register.
The first gating circuit 2 is configured to: in response to the control of the potential of the first clock signal terminal CLK, the second voltage signal provided by the second voltage terminal VGL is transmitted to the third node N3 in the input stage.
The noise reduction circuit 5 is configured to: in the first noise reduction stage, the fourth node N4 is disconnected from the second node N2 in response to a potential difference between the third node N3 and the fourth node N4 and control of a potential of the second clock signal terminal CLKB, and in the second noise reduction stage, the fourth node N4 is disconnected from the second node N2.
The input and compensation circuit 3 is configured to: in response to the potential control of the first clock signal terminal CLK and the third node N3, the signal of the INPUT terminal INPUT of the shift register is transmitted to the first node N1 and the first voltage signal provided by the first voltage terminal VGH is transmitted to the fourth node N4 in the INPUT stage and the first noise reduction stage of the shift register. In the output stage of the shift register, the first node N1 and the fourth node N4 are supplied with active level signals.
In the embodiment of the present invention, in the output stage, an effective level signal may be provided to the first node N1 and the fourth node N4 by the input and compensation circuit 3, when the transmission circuit 1 and the noise reduction circuit 5 each include a switching transistor, the first node N1 may be connected to the source of the switching transistor of the transmission circuit 1, the first clock signal terminal may be connected to the gate of the switching transistor of the transmission circuit 1, the fourth node N4 may be connected to the source of the switching transistor of the noise reduction circuit 5, and the third node N3 may be connected to the gate of the switching transistor of the noise reduction circuit 5, so that the switching transistors in the transmission circuit 1 and the noise reduction circuit 5 may be sufficiently turned off to disconnect the second node N2 from the first node N1, and disconnect the second node N2 from the fourth node N4, thereby preventing the second node N2 from leaking.
The following describes the shift register in detail with reference to fig. 2 to 4d, and it should be noted that the transistors in the embodiment of the present invention may be thin film transistors, field effect transistors, or other switching devices with the same characteristics. Transistors generally comprise three poles: the gate, source and drain, the source and drain in the transistor are symmetrical in structure, and the two are interchangeable as desired. In an embodiment of the present invention, one of the first pole and the second pole is a source and the other is a drain.
Further, the transistors can be classified into N-type transistors and P-type transistors according to transistor characteristics. In the present invention, "active level signal" (or "active level potential") means a voltage signal (or potential) capable of controlling the turn-on of the corresponding transistor, and "inactive level signal" (or "inactive level potential") means a voltage signal (or potential) capable of controlling the turn-off of the corresponding transistor; therefore, when the transistor is an N-type transistor, the active level signal means a high level signal and the inactive level signal means a low level signal; when the transistor is a P-type transistor, the active level signal is a low level signal, and the inactive level signal is a high level signal. The embodiment of the invention is described by taking the example that transistors in the shift register are all P-type transistors.
As shown in fig. 2, in some embodiments, the input and compensation circuit 3 includes: an input transistor M1, a first compensation transistor M2, a second compensation transistor M3, and a third compensation transistor M4. The gate of the INPUT transistor M1 is connected to the first clock signal terminal CLK, the first pole of the INPUT transistor M1 is connected to the INPUT terminal INPUT of the shift register, and the second pole of the INPUT transistor M1 is connected to the first node N1. The gate and the second pole of the first compensation transistor M2 are both connected to the OUTPUT of the shift register, and the first pole of the first compensation transistor M2 is connected to the first node N1. The gate of the second compensation transistor M3 is connected to the third node N3, the first pole of the second compensation transistor M3 is connected to the first voltage terminal VGH, and the second pole of the second compensation transistor M3 is connected to the fourth node N4. The gate and the second pole of the third compensation transistor M4 are both connected to the OUTPUT of the shift register, and the first pole of the third compensation transistor M4 is connected to the fourth node N4.
In some embodiments, the transmission circuit 1 comprises: and a gate of the transmission transistor M5 is connected to the first clock signal terminal CLK, a first pole of the transmission transistor M5 is connected to the first node N1, and a second pole of the transmission transistor M5 is connected to the second node N2.
In some embodiments, the first output circuit 4 comprises: a first output transistor M6 and a first capacitance C1. The gate of the first OUTPUT transistor M6 is connected to the second node N2, the first pole of the first OUTPUT transistor M6 is connected to the second clock signal terminal CLKB, and the second pole of the first OUTPUT transistor M6 is connected to the OUTPUT terminal OUTPUT of the shift register. One end of the first capacitor C1 is connected to the gate of the first output transistor M6, and the other end of the first capacitor C1 is linked to the second pole of the first output transistor M6.
In some embodiments, the noise reduction circuit 5 includes a first noise reduction transistor M7 and a second noise reduction transistor M8. The first noise reduction transistor M7, the gate of the first noise reduction transistor M7 is connected to the third node N3, the first pole of the first noise reduction transistor M7 is connected to the fourth node N4, and the second pole of the first noise reduction transistor M7 is connected to the first pole of the second noise reduction transistor M8. The gate of the second noise reduction transistor M8 is connected to the second clock signal terminal CLKB, and the second pole of the second noise reduction transistor M8 is connected to the second node N2.
In some embodiments, the first gating circuit 2 comprises: the gate of the first gating transistor M9 is connected to the first clock signal terminal CLK, the first pole of the first gating transistor M9 is connected to the second voltage terminal VGL, and the second pole of the first gating transistor M9 is connected to the third node N3.
In some embodiments, the shift register further includes a second output circuit 6, the second output circuit 6 being connected to the third node N3. The second output circuit 6 is configured to: in response to the control of the potential of the third node N3, the first voltage signal provided by the first voltage terminal VGH is transmitted to the OUTPUT terminal OUTPUT of the shift register in the input stage and the noise reduction stage.
In some embodiments, the second output circuit 6 comprises: a second output transistor M10 and a second capacitor C2. The gate of the second OUTPUT transistor M10 is connected to the third node N3, the first pole of the second OUTPUT transistor M10 is connected to the first voltage terminal VGH, and the second pole of the second OUTPUT transistor M10 is connected to the OUTPUT terminal OUTPUT of the shift register. One end of the second capacitor C2 is connected to the gate of the second output transistor M10, and the other end of the second capacitor C2 is connected to the first pole of the second output transistor M10.
In some embodiments, the shift register further comprises: and a second gating circuit 7, the second gating circuit 7 being connected between the second node N2 and the third node N3. The second gating circuit 7 is configured to: in response to control of the potential of the second node N2, the second node N2 is turned on with the third node N3 in the input stage and the first noise reduction stage; in the output stage and the second noise reduction stage, the second node N2 is disconnected from the third node N3.
In some embodiments, the second gating circuit 7 comprises: and a second gating transistor M11, wherein the gate of the second gating transistor M11 is connected to the second node N2, the first pole of the second gating transistor M11 is connected to the first clock signal terminal CLK, and the second pole of the second gating transistor M11 is connected to the third node N3.
Fig. 3 is a driving timing chart of a shift register according to an embodiment of the present invention, fig. 4a to fig. 4d are schematic diagrams of transistor states of the shift register at different stages according to an embodiment of the present invention, and a specific operation process of the shift register according to an embodiment of the present invention is described below with reference to fig. 3 to fig. 4 d.
As shown in fig. 3 and 4a, in the INPUT stage T1, the signal provided to the INPUT terminal INPUT of the shift register is an active level signal, an active level signal is provided to the first clock signal terminal CLK, and an inactive level signal is provided to the second clock signal terminal CLKB. At this time, the INPUT transistor M1, the transmission transistor M5 and the first gate transistor M9 are all turned on, the active level signal provided by the INPUT end INPUT of the shift register is transmitted to the second node N2, the first OUTPUT transistor M6 and the INPUT transistor M11 are turned on, the second voltage signal provided by the second voltage end VGL and the active level signal of the second node are both transmitted to the third node N3, the INPUT transistor M10 is turned on, and the inactive level signal provided by the second clock signal end CLKB and the first voltage signal provided by the first voltage end VGH are both transmitted to the OUTPUT end OUTPUT of the shift register. At the same time, the first compensation transistor M2, the third compensation transistor M4 and the second noise reduction transistor M8 are all turned off, and the second node N2 is disconnected from the first voltage terminal VGH.
As shown in fig. 3 and 4b, in the output stage T2, the signal supplied to the INPUT terminal INPUT of the shift register is an inactive level signal, the inactive level signal is supplied to the first clock signal terminal CLK, and the active level signal is supplied to the second clock signal terminal CLKB. At this time, the input transistor M1, the transmission transistor M5 and the first gating transistor M9 are turned off, the inactive level signal provided by the first clock signal terminal CLK is transmitted to the third node N3 through the input transistor M11, and the second compensation transistor M3, the first noise reduction transistor M7 and the input transistor M10 are turned off. The potential of the second node N2 further decreases under the bootstrap action of the first capacitor C1, the first OUTPUT transistor M6 is fully turned on, and the active level signal provided by the second clock signal terminal CLKB is transmitted to the OUTPUT terminal OUTPUT of the shift register. The first compensation transistor M2 and the third compensation transistor M4 at this time are equivalent to diodes, so that the effective level signal of the OUTPUT terminal OUTPUT of the shift register is written into the first node N1 and the fourth node N4, so that the gate-source voltages Vgs >0 of the transmission transistor M5 and the first noise reduction transistor M7 are made to be sufficiently turned off, thereby preventing the second node N2 from leaking.
As shown in fig. 3 and 4c, in the first noise reduction stage T3, the signal provided to the INPUT terminal INPUT of the shift register is an inactive level signal, the active level signal is provided to the first clock signal terminal CLK, and the inactive level signal is provided to the second clock signal terminal CLKB. At this time, the INPUT transistor M1, the transmission transistor M5 and the first gating transistor M9 are all turned on, and the inactive level signal provided by the INPUT terminal INPUT of the shift register is transmitted to the second node N2 to reduce noise on the second node N2, and the first output transistor M6 and the INPUT transistor M11 are both turned off. The second voltage signal provided by the second voltage terminal VGL is transmitted to the third node N3, the second compensation transistor M3, the first noise reduction transistor M7 and the input transistor M10 are all turned on, and the first voltage signal provided by the first voltage terminal VGH is transmitted to the OUTPUT terminal OUTPUT of the shift register, so as to reduce noise of the OUTPUT terminal OUTPUT of the shift register. At the same time, the first compensation transistor M2, the third compensation transistor M4 and the second noise reduction transistor M8 are all turned off, and the second node N2 is disconnected from the first voltage terminal VGH.
As shown in fig. 3 and 4d, in the second noise reduction stage T4, the signal provided to the INPUT terminal INPUT of the shift register is an inactive level signal, the inactive level signal is provided to the first clock signal terminal CLK, and the active level signal is provided to the second clock signal terminal CLKB. At this time, the input transistor M1, the transmission transistor M5 and the first gating transistor M9 are turned off, the potential of the third node N3 is kept at an active level, the second compensation transistor M3, the first noise reduction transistor M7 and the second noise reduction transistor M8 are turned on, and the first voltage signal provided by the first voltage terminal VGH is transmitted to the second node N2 to reduce noise of the second node N2.
It should be noted that, in the embodiment of the present invention, before the next frame starts, the first noise reduction stage T3 and the second noise reduction stage T4 are alternately performed, so as to reduce noise at the OUTPUT end OUTPUT and the second node N2 of the shift register.
In summary, in the shift register according to the embodiment of the present invention, in the output stage T2, the gate-source voltages Vgs >0 of the transmission transistor M5 and the first noise reduction transistor M7 can be ensured to be sufficiently turned off so as to prevent the second node N2 from leaking, and compared with the scheme in fig. 1, the shift register according to the embodiment of the present invention is further advantageous for improving the forward threshold voltage offset Margin (Vth Margin) of the transistors in the shift register, thereby improving the flexibility of circuit design.
It should be noted that, in other embodiments, the second pole of the first compensation transistor M2 may be further connected to the second node N2, and in this case, during the output phase T2, an active level signal may also be written into the first node N1, so as to ensure that the pass transistor M5 is fully turned off. In this case, the operation state of each transistor is the same as that in the above embodiment in each stage, and a description thereof will be omitted.
The embodiment of the invention also provides a driving method applied to the shift register, wherein the driving method comprises the following steps:
in the input stage, an effective level signal is provided to the first clock signal end and the input end of the shift register, so that the input and compensation circuit transmits the signal of the input end of the shift register to the first node, and the transmission circuit conducts the first node and the second node.
In the output stage, an invalid level signal is provided for the first clock signal end, an effective level signal is provided for the second clock signal end, so that the input and compensation circuit provides the effective level signal for the first node and the fourth node, the transmission circuit disconnects the first node from the second node, and the noise reduction circuit disconnects the fourth node from the second node.
In the first noise reduction stage, an effective level signal is provided for the first clock signal end, an ineffective level signal is provided for the second clock signal end and the input end of the shift register, so that the first gating circuit transmits a second voltage signal provided by the second voltage end to the third node, the input and compensation circuit transmits a signal of the input end of the shift register to the first node, and the transmission circuit conducts the first node and the second node.
In the second noise reduction stage, an invalid level signal is provided for the first clock signal end, an effective level signal is provided for the second clock signal end, so that the input and compensation circuit transmits a first voltage signal provided by the first voltage end to the fourth node, and the noise reduction circuit conducts the fourth node with the second node.
By adopting the driving method of the embodiment of the invention, the second node can be prevented from generating electricity leakage in the output stage, so that the influence of electricity leakage on the output of the shift register is avoided.
The embodiment of the invention also provides a gate driving circuit, which comprises: and the output end of the shift register of the upper stage is connected with the input end of the lower stage in the adjacent two stages. The shift register adopts the shift register.
The embodiment of the invention also provides a display device, which comprises the gate driving circuit.
The display device may be: electronic paper, display panel, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.
Claims (13)
1. A shift register, comprising: the device comprises a transmission circuit, a first gating circuit, an input and compensation circuit, a first output circuit and a noise reduction circuit; one end of the transmission circuit is connected with the input and compensation circuit and is connected with a first node, the other end of the transmission circuit, the first end of the noise reduction circuit and the first output circuit are connected with a second node, the first gating circuit, the input and compensation circuit and the second end of the noise reduction circuit are connected with a third node, the third end of the noise reduction circuit and the input and compensation circuit are connected with a fourth node, and the input and compensation circuit and the first output circuit are connected with the output end of the shift register;
the transmission circuit is configured to: switching the first node on or off from the second node in response to control of a potential difference between a first clock signal terminal and the first node;
the first output circuit is configured to: transmitting a clock signal of a second clock signal terminal to an output terminal of the shift register in response to control of the potential of the second node;
the first gating circuit is configured to: transmitting a second voltage signal provided by a second voltage terminal to the third node in response to control of the potential of the first clock signal terminal;
the noise reduction circuit is configured to: switching on or off the fourth node and the second node in response to a potential difference between the third node and the fourth node and control of a potential of the second clock signal terminal;
the input and compensation circuit is configured to: transmitting a signal of an input terminal of the shift register to the first node and transmitting a first voltage signal provided by a first voltage terminal to the fourth node in an input stage and a first noise reduction stage of the shift register in response to potential control of the first clock signal terminal and the third node; in an output stage of the shift register, an active level signal is supplied to the first node and the fourth node.
2. The shift register of claim 1, further comprising a second output circuit, the second output circuit being connected to the third node;
the second output circuit is configured to: and transmitting a first voltage signal provided by the first voltage terminal to an output terminal of the shift register in response to control of the potential of the third node.
3. The shift register of claim 1, wherein the shift register further comprises: a second gating circuit connected between the second node and the third node;
the second gating circuit is configured to: the second node is turned on or off from the third node in response to control of the potential of the second node.
4. The shift register of claim 1, wherein the input and compensation circuit comprises: an input transistor, a first compensation transistor, a second compensation transistor, and a third compensation transistor;
the grid electrode of the input transistor is connected with the first clock signal end, the first electrode of the input transistor is connected with the input end of the shift register, and the second electrode of the input transistor is connected with the first node;
the grid electrode and the second electrode of the first compensation transistor are connected with the output end of the shift register, and the first electrode of the first compensation transistor is connected with the first node;
the grid electrode of the second compensation transistor is connected with the third node, the first electrode of the second compensation transistor is connected with the first voltage end, and the second electrode of the second compensation transistor is connected with the fourth node;
the grid electrode and the second electrode of the third compensation transistor are both connected with the output end of the shift register, and the first electrode of the third compensation transistor is connected with the fourth node.
5. The shift register according to any one of claims 1 to 4, wherein the transmission circuit includes: and the grid electrode of the transmission transistor is connected with the first clock signal end, the first electrode of the transmission transistor is connected with the first node, and the second electrode of the transmission transistor is connected with the second node.
6. The shift register according to any one of claims 1 to 4, wherein the first output circuit includes: a first output transistor and a first capacitor;
the grid electrode of the first output transistor is connected with the second node, the first electrode of the first output transistor is connected with the second clock signal end, and the second electrode of the first output transistor is connected with the output end of the shift register;
one end of the first capacitor is connected with the grid electrode of the first output transistor, and the other end of the first capacitor is linked with the second pole of the first output transistor.
7. The shift register according to any one of claims 1 to 4, wherein the noise reduction circuit includes a first noise reduction transistor and a second noise reduction transistor;
the grid electrode of the first noise reduction transistor is connected with the third node, the first pole of the first noise reduction transistor is connected with the fourth node, and the second pole of the first noise reduction transistor is connected with the first pole of the second noise reduction transistor;
and the grid electrode of the second noise reduction transistor is connected with the second clock signal end, and the second pole of the second noise reduction transistor is connected with the second node.
8. The shift register according to any one of claims 1 to 4, wherein the first gate circuit includes: and the grid electrode of the first gating transistor is connected with the first clock signal end, the first electrode of the first gating transistor is connected with the second voltage end, and the second electrode of the first gating transistor is connected with the third node.
9. The shift register according to any one of claims 2 to 4, wherein the second output circuit includes: a second output transistor and a second capacitor;
the grid electrode of the second output transistor is connected with the third node, the first electrode of the second output transistor is connected with the first voltage end, and the second electrode of the second output transistor is connected with the output end of the shift register;
one end of the second capacitor is connected with the grid electrode of the second output transistor, and the other end of the second capacitor is connected with the first pole of the second output transistor.
10. The shift register of claim 3 or 4, wherein the second gating circuit comprises: and the grid electrode of the second gating transistor is connected with the second node, the first electrode of the second gating transistor is connected with the first clock signal end, and the second electrode of the second gating transistor is connected with the third node.
11. A driving method applied to the shift register according to any one of claims 1 to 10, characterized in that the driving method comprises:
in an input stage, providing an effective level signal to the first clock signal end and the input end of the shift register so that the input and compensation circuit transmits the signal of the input end of the shift register to the first node, and the transmission circuit conducts the first node with the second node;
in an output stage, an invalid level signal is provided for the first clock signal end, an effective level signal is provided for the second clock signal end, so that the input and compensation circuit provides the effective level signal for the first node and the fourth node, the transmission circuit disconnects the first node from the second node, and the noise reduction circuit disconnects the fourth node from the second node;
in a first noise reduction stage, an effective level signal is provided for the first clock signal end, an ineffective level signal is provided for the second clock signal end and the input end of the shift register, so that the first gating circuit transmits a second voltage signal provided by a second voltage end to the third node, the input and compensation circuit transmits a signal of the input end of the shift register to the first node, and the transmission circuit conducts the first node and the second node;
in the second noise reduction stage, an invalid level signal is provided for the first clock signal end, an effective level signal is provided for the second clock signal end, so that the input and compensation circuit transmits a first voltage signal provided by the first voltage end to the fourth node, and the noise reduction circuit conducts the fourth node with the second node.
12. A gate driving circuit, comprising: the shift register of any one of claims 1 to 10.
13. A display device comprising the gate driver circuit according to claim 12.
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