CN112014707A - Method for measuring and controlling junction temperature of SiC power VDMOS device in power cycle experiment - Google Patents
Method for measuring and controlling junction temperature of SiC power VDMOS device in power cycle experiment Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 49
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
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- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a method for measuring and controlling junction temperature of a SiC power VDMOS device in a power cycle experiment, which accelerates the aging process of the device mainly by applying intermittent power through a power cycle experiment platform so as to achieve the aim of simulating the actual working condition of the SiC power VDMOS device. Calculating and extracting the temperature fluctuation of the chip during the power application period by collecting the conduction voltage drop corresponding to the drain-source current of the device working in the non-saturation region, and controlling the junction temperature of the device to be within a limited range by a feedback circuit; the chip temperature fluctuation during the power turn-off period is calculated and extracted by collecting the conduction voltage drop of the parasitic body diode corresponding to the constant small source-drain current in the turn-off state of the device, and the junction temperature of the device is controlled to be within a limited range by a feedback circuit. The method is simple and easy to implement, the experimental cost is low, the packaging of the SiC power VDMOS device cannot be damaged, complete program control can be realized through a computer, and the junction temperature of the SiC power VDMOS device can be accurately measured and controlled.
Description
Technical Field
The invention relates to measurement and control of junction temperature of a semiconductor device in a power cycle experiment of a SiC power VDMOS device, belonging to the field of power semiconductor device test.
Background
The SiC (Silicon Carbide) material has the advantages of large forbidden band width, high breakdown electric field, high saturation drift velocity and high thermal conductivity, and the excellent properties of the materials make the SiC (Silicon Carbide) material an ideal material for manufacturing high-power, high-frequency, high-temperature-resistant and radiation-resistant devices. Compared with the traditional Si device, the SiC power electronic device has great advantages in blocking performance, switching speed, high temperature characteristics and the like, and particularly, the SiC power VDMOS (Vertical Double-Diffused Metal Oxide Semiconductor Field Effect Transistor) device has attracted attention in recent years due to its advantages of high switching speed, high blocking voltage and the like, and is gradually put into various fields such as spacecraft, electric vehicles and the like.
With the gradual and wide use of the device, the reliability problem also becomes the focus of attention of people, and in order to ensure the reliability of the device in use, the device needs to be sampled and subjected to a reliability assessment test before being put into use so as to assess the service life and the reliability of the device. The power cycle experiment/intermittent life service is one of three reliability assessment tests specified in international standard IEC-60747-9-2007-semiconductor device-discrete device-part 8-field effect transistor, and is also one of tests which must be done before the device leaves the factory. According to the arrhenius model, the lifetime of the device is reduced by about half for every 10 ℃ rise in the device temperature, so temperature control is particularly important in this test.
The existing method for testing junction temperature usually calculates junction temperature by measuring junction voltage corresponding to small current under thermal resistance calculation or off state. The junction temperature measuring method is used for measuring the junction temperature of a device under static state, and the transient junction temperature of the device needs to be measured in the power cycle process, so the method is not suitable for power cycle experiments; the thermal resistance of the device is variable and changes along with the change of working temperature, applied power and the like; therefore, the temperature result obtained by calculating the thermal resistance has errors with the actual junction temperature. The method for measuring junction temperature by using the junction voltage corresponding to the small current in the off state cannot measure the junction temperature of the on-state device and cannot avoid the device burning caused by overhigh on-state temperature.
Because the SiC material is different from the Si material, the gate oxide layer of the SiC power VDMOS device has defects, and the temperature measurement method of the Si power VDMOS cannot be directly used, so that an effective method for measuring and controlling the junction temperature of the SiC power VDMOS device in real time on line when the power cycle experiment is conducted and shut down is urgently needed to be found.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a method for measuring and controlling the junction temperature of a SiC power VDMOS device in a power cycle experiment.
The technical method of the invention is as follows:
in order to simulate two different working conditions of connection and disconnection of a SiC power VDMOS device in actual work, the invention designs a power cycle experimental platform and according to the drain-source voltage V of the device in a non-saturation regionDSRelation with junction temperature, on-voltage V of internal body diode at turn-offFThe relation with the junction temperature measures and controls the junction temperature of the device. In which the device internal body diode conduction voltage V in the off-state is measuredFIn the process, because a gate oxide layer of the device has defects due to a SiC material of the SiC power VDMOS device, and negative gate voltage shielding traps are required to be applied to avoid the influence of the defects on the test, in order to achieve the aim, the invention provides a method for measuring and controlling the junction temperature of the SiC power VDMOS device in a power cycle experiment, which comprises the following steps:
acquiring unsaturated drain-source voltage drop V corresponding to drain-source current in power cycle process of SiC power VDMOS device to be tested during conductionDSAnd the turn-on voltage V of the internal body diode at turn-offF(ii) a The drain-source current is large heating current or constant small current;
conduction voltage drop V corresponding to drain-source current based on junction temperature and drain-source unsaturated regionDSFitting a curved surface to obtain the current junction temperature corresponding to the saturated conduction voltage drop when the power is added and the temperature is raised in the on state of the device;
based on junction temperature and conduction voltage V of internal body diodeFFitting a curve to obtain the current junction temperature of the conduction voltage corresponding to the body diode when the device is in an off state and is not powered and cooled;
when the current junction temperature is smaller than the set lowest junction temperature, the power circulation platform applies power to the device to be tested to raise the temperature; when the current junction temperature is larger than the set maximum temperature, the power of the power circulation platform is removed for cooling; thus, the power cycle experiment is realized.
On the other hand, the invention also provides a power cycle experimental platform of the SiC power VDMOS device, which comprises the following steps:
a power module: the constant drain-source large current is used for providing a device to work in a non-saturation region;
a grid voltage module: the gate voltage is used for providing the device to control the on and off of the device;
a low current module: the test circuit is used for providing a smaller test current of the internal booster diode when the test circuit is switched off;
an acquisition module: for collecting drain-source voltage V when device is turned onDSAnd increasing the diode junction voltage V when switching offFAnd uploading to a computer;
the calculation control module: the device is used for data processing, junction temperature measurement and control, and commands for switching on and off of the device are issued.
The experimental device for realizing the method comprises the following steps: a SiC power VDMOS device and a matched clamp; the power cycle experiment platform comprises a data acquisition card 1 block, an FPGA control panel 1 block, a relay, a capacitor and a plurality of resistors; a computer; providing a pulse current IPThe power device analyzer of (1); providing a constant small current IFThe digital source table of (1); providing a drain-source current IDSThe power supply of (1); providing a stable gate voltage VGSThe linear power supply of (1); an adjustable incubator at 0-150 ℃.
The specific test method comprises the following steps:
the method comprises the following steps: placing the SiC power VDMOS device in an incubator, adjusting the initial temperature of the incubator to a stable state, and when the incubator rises to a set temperature and is kept for 10 minutes, considering that the junction temperature of the SiC power VDMOS device is the same as the internal temperature of the incubator;
step two: connecting the SiC power VDMOS device with a linear power supply and a power device analyzer through a clamp, and applying a gate source voltage V through the linear power supplyGSMaking SiC power VDMOS device be in conduction state, applying short pulse drain-source current I by power device analyzerPMeasuring short pulse drain-source voltage V when SiC power VDMOS device is conductedP；
Step three: applying a negative gate-source voltage V of 6V or moreGSThe SiC power VDMOS device is in a turn-off state and is shielded from the influence of the defects of a gate oxide layer, the SiC power VDMOS device is connected with a digital source meter through a clamp, and the digital source meter applies a conducting current I to a body diode in the SiC power VDMOS deviceFMeasuring the body diode conduction voltage VF；
Step four: holding VGS、IP、IFThe temperature of the incubator is changed and stabilized without change, and the second step and the third step are repeated to measure the V of the SiC power VDMOS device at different temperaturesPAnd VFAccording to VPTemperature and VFThe relation between the voltage and the temperature is fitted by an algorithm to obtain the drain-source voltage V of the unsaturated zoneDSJunction temperature and body diode conduction voltage VFThe relation with the junction temperature and respectively used as a temperature correction curve library when the SiC power VDMOS device is switched on and switched off;
step five: connecting the SiC power VDMOS device to a power cycle experiment platform through a clamp, wherein the SiC power VDMOS device is in an initial state of being turned off, and setting a junction temperature range in which the SiC power VDMOS device normally works through a computer; grid source voltage V is provided for SiC power VDMOS device through linear power supplyGSMaking the SiC power VDMOS device in a conducting state;
step six: connecting the SiC power VDMOS device with a power supply, and applying constant drain-source current I to the device via the power supplyDSCollecting the drain-source current V of the device through a power cycle experiment platformDSUploading the temperature data to a computer, calculating junction temperature according to the temperature correction curve library obtained in the fourth step when the SiC power VDMOS device is conducted, and when the junction temperature is higher than a set maximum value, issuing a turn-off instruction by the computer and applyingApplying negative gate voltage VGSMaking the SiC power VDMOS device in a turn-off state;
step seven: connecting the SiC power VDMOS device with a digital source meter, and applying constant on-state current I to the body diode in the SiC power VDMOS device through the digital source meterF(conduction Current I)FSmaller), the conduction voltage V of the device is acquired through a power cycle experiment platformFUploading the temperature data to a computer, calculating junction temperature according to the temperature correction curve library obtained in the fourth step when the SiC power VDMOS device is turned off, and when the junction temperature is lower than a set minimum value, issuing a turn-on instruction by the computer and turning on a gate voltage VGSMaking the SiC power VDMOS device in a conducting state;
step eight: the variation relation between the power applied to the device and the junction temperature of the SiC power VDMOS device can be obtained through the sixth step and the seventh step; and (3) setting cycle times through a computer, namely repeating the sixth step and the seventh step to perform power cycle experiments on the SiC power VDMOS device for multiple times so as to realize real-time measurement and control of the junction temperature of the SiC power VDMOS device.
Drawings
FIG. 1: a basic schematic diagram of a power cycle experiment;
FIG. 2: a control relation graph among modules of a power cycle experiment;
FIG. 3: a staircase pulse current schematic;
FIG. 4: a schematic diagram of a temperature calibration curve library when a device DUT is conducted;
FIG. 5: schematic diagram of the temperature correction curve library when the device DUT is turned off;
FIG. 6: a graph of applied power versus temperature in a single power cycle experiment;
FIG. 7: a relation graph of applied power and temperature in a plurality of power cycle experiments;
FIG. 8: the invention implements the flow chart.
Detailed Description
The present invention will be described in more detail below with reference to the accompanying drawings and specific embodiments. The power cycle experiment is mainly divided into two parts: 1. using a temperature box and a power analyzer to make a temperature calibration curve for the device; 2. the power cycle experiment is carried out, the basic principle of a power cycle experiment platform is shown in figure 1, the power cycle experiment platform comprises a power module, a small current module, a grid voltage module and an acquisition module, wherein the power module comprises a power supply and a clamp, the small current module comprises a digital source table and a clamp, the grid voltage module comprises a linear power supply and a clamp, the acquisition module comprises an FPGA (field programmable gate array) and a data acquisition card, the power supply and the digital source table are embedded on the power cycle experiment platform, and the control relation among the modules is shown in figure 2.
The specific test method of the invention comprises the following steps:
the method comprises the following steps: connecting a SiC power VDMOS device DUT (device under test) with the model of C2M0080120D with a power analyzer and a digital source meter, placing the device in an incubator, adjusting the initial temperature to 20 ℃, and when the incubator is heated to the set temperature and is kept for 10 minutes, considering that the junction temperature of the device is the same as the internal temperature of the incubator.
Step two: applying a gate-source voltage V by a linear power supplyGSThe device is in a conducting state at 15V, and a short pulse drain-source current I with 100 steps is applied through a power device analyzerP15A (pulse width 100us, duty cycle 1%, step waveform approximately as shown in fig. 3), the short pulse drain-source voltage V at which the device was on was measuredP。
Step three: applying a turn-off gate-source voltage VGSThe DUT is in a turn-off state under-6V, the device is connected with a digital source table through a clamp, and the on-current I is applied to the body diode in the device through the digital source tableF1mA, measuring the body diode conduction voltage VF。
Step four: holding the turn-on gate-source voltage VGS15V, turn-off gate-source voltage VGSStepped short pulse drain-source current I of-6VP15A (pulse width 100us, duty cycle 1%), IFThe temperature of the temperature box is adjusted to be increased by 5 ℃ once when the temperature is not changed to 1mA, and the V of the SiC power VDMOS device is measured at the temperature of 20-150 ℃ according to the second step and the third stepPAnd VFAccording to VPWith temperature and VFThe relation between the voltage and the temperature is fitted by an algorithm to obtain the drain-source voltage V of the unsaturated zoneDSJunction temperature and body diode conduction voltage VFAs a function of junction temperature, andthe temperature calibration curve library of the device DUT when it is turned on and off is shown in FIG. 4 and FIG. 5 respectively.
Step five: the DUT (device under room temperature) is inserted into a test board of a power cycle experiment platform, the initial state of the device is off, and the junction temperature range of normal work of the device is set to be 50-150 ℃ through a computer
Step six: at the moment, the temperature of the device is lower than 50 ℃, so that S1 and S3 are closed, S2 and S4 are opened, and the grid-source voltage V is provided for the device through the grid voltage moduleGSThe device is put in a conducting state at 15V, and the power module applies a constant drain-source current IDS15A, and monitoring the conducted drain-source voltage V in real time through an acquisition moduleDSAnd uploading to the calculation control module.
Step seven: according to V uploaded to computerDSCalculating junction temperature through the temperature correction curve library obtained in the step four when the device is conducted, maintaining the state of the step six if the calculated junction temperature is lower than 150 ℃, giving an instruction to the computer when the junction temperature is higher than 150 ℃, disconnecting S1 and S3, closing S2 and S4, and applying a grid source turn-off voltage V at the momentGS-6V to turn the device off while applying a constant on-current I to the device internal body diode via the low current moduleF1mA, and monitoring the diode conducting voltage V in real time through an acquisition moduleFAnd uploading to the calculation control module.
Step eight: according to V uploaded to computerFCalculating junction temperature through the temperature correction curve library obtained in the fourth step when the device is turned off, maintaining the state in the seventh step if the calculated junction temperature is higher than 50 ℃, issuing instructions by the computer when the junction temperature is lower than 50 ℃, and repeating the sixth step
Step eight: the power cycling can be achieved by continuously repeating steps six, seven and eight, and the power applied to the device DUT during one cycle of the power cycling versus the device junction temperature can be obtained from steps six, seven and eight, as shown in fig. 6. And setting the cycle number to be 3 by a computer, namely repeatedly repeating the sixth step, the seventh step and the eighth step to perform power cycle experiments on the device for 3 times, so as to obtain the relation between the power applied to the device DUT after the power cycle is performed for 3 times and the junction temperature change of the device, as shown in fig. 7, so as to realize the real-time measurement and control of the junction temperature of the SiC power VDMOS device.
The invention has the beneficial effects that: the method is simple and easy to implement, the experiment cost is low, the encapsulation of the SiC power VDMOS device cannot be damaged, complete program control can be realized through a computer, the junction temperature range of the device during the power cycle experiment process can be set automatically, long-time and multi-period power cycle experiments can be carried out, and the junction temperature of the SiC power VDMOS device can be measured and controlled accurately.
Claims (4)
1. A method for measuring and controlling junction temperature of a SiC power VDMOS device in a power cycle experiment is characterized by comprising the following steps:
acquiring unsaturated drain-source voltage drop V corresponding to drain-source current in power cycle process of SiC power VDMOS device to be tested during conductionDSAnd the turn-on voltage V of the internal body diode at turn-offF(ii) a The drain-source current is large heating current or constant small current;
conduction voltage drop V corresponding to drain-source current based on junction temperature and drain-source unsaturated regionDSFitting a curved surface to obtain the current junction temperature corresponding to the saturated conduction voltage drop when the power is added and the temperature is raised in the on state of the device;
based on junction temperature and conduction voltage V of internal body diodeFFitting a curve to obtain the current junction temperature of the conduction voltage corresponding to the body diode when the device is in an off state and is not powered and cooled;
when the current junction temperature is smaller than the set lowest junction temperature, the power circulation platform applies power to the device to be tested to raise the temperature; when the current junction temperature is larger than the set maximum temperature, the power of the power circulation platform is removed for cooling; thus, the power cycle experiment is realized.
2. The method for measuring and controlling junction temperature of the SiC power VDMOS device in the power cycle experiment as claimed in claim 1, wherein the experimental apparatus for implementing the method comprises: a SiC power VDMOS device and a matched clamp; the power cycle experiment platform comprises a data acquisition card 1 block, an FPGA control panel 1 block, a relay, a capacitor and a plurality of resistors; a computer; lifting deviceSupply pulse current IPThe power device analyzer of (1); providing a constant small current IFThe digital source table of (1); providing a drain-source current IDSThe power supply of (1); providing a stable gate voltage VGSThe linear power supply of (1); an adjustable incubator at 0-150 ℃.
3. The method for measuring and controlling junction temperature of the SiC power VDMOS device in the power cycle experiment as claimed in claim 1, wherein the method is based on the non-saturated drain-source conduction voltage drop VDSAnd the turn-on voltage V of the internal body diodeFThe step of obtaining the current junction temperature comprises the steps of:
placing the device in an incubator, adjusting the temperature to a steady state, maintaining for a period of time, considering that the junction temperature of the device is the same as the temperature in the incubator, and applying a gate-source voltage V to the deviceGSTo avoid self-heating caused by long-time operation of the device, short pulse drain-source current I is applied by a power device analyzerPMeasuring the short pulse drain-source voltage V when the device is onP(ii) a Then measuring the on-state voltage V of the internal body diode of the device in the off stateFBecause the SiC material of the SiC power VDMOS device causes the defect of the gate oxide layer of the device, the negative gate voltage which is more than or equal to 6V is required to be applied to avoid the influence of the defect on the test and the influence of the negative gate voltage on shielding the trap, so that the device is in a turn-off state and the influence of the defect of the gate oxide layer is shielded, and a smaller constant on-state current I is appliedFMeasuring the internal body diode turn-on voltage V of the deviceF(ii) a Then the temperature of the incubator is adjusted to be stable, and the grid source voltage V is maintainedGSPulse current IPOn-state current IFConstant, pulsed voltage V at different temperatures at which the measurement device is switched onPConduction voltage V with internal body diodeF(ii) a Fitting the drain-source voltage V of the unsaturated zone in actual work according to an algorithmDSRelation with junction temperature, body diode conduction voltage VFAnd the relation with the junction temperature and are respectively used as a temperature correction curve library when the SiC power VDMOS device is switched on and switched off.
4. The method for measuring and controlling junction temperature of the SiC power VDMOS device in the power cycle experiment as claimed in claim 1, wherein the specific test method comprises the steps of:
the method comprises the following steps: placing the SiC power VDMOS device in an incubator, adjusting the initial temperature of the incubator to a stable state, and when the incubator rises to a set temperature and is kept for 10 minutes, considering that the junction temperature of the SiC power VDMOS device is the same as the internal temperature of the incubator;
step two: connecting the SiC power VDMOS device with a linear power supply and a power device analyzer through a clamp, and applying a gate source voltage V through the linear power supplyGSMaking SiC power VDMOS device be in conduction state, applying short pulse drain-source current I by power device analyzerPMeasuring short pulse drain-source voltage V when SiC power VDMOS device is conductedP；
Step three: applying a negative gate-source voltage V of 6V or moreGSThe SiC power VDMOS device is in a turn-off state and is shielded from the influence of the defects of a gate oxide layer, the SiC power VDMOS device is connected with a digital source meter through a clamp, and the digital source meter applies a conducting current I to a body diode in the SiC power VDMOS deviceFMeasuring the body diode conduction voltage VF；
Step four: holding VGS、IP、IFThe temperature of the incubator is changed and stabilized without change, and the second step and the third step are repeated to measure the V of the SiC power VDMOS device at different temperaturesPAnd VFAccording to VPTemperature and VFThe relation between the voltage and the temperature is fitted by an algorithm to obtain the drain-source voltage V of the unsaturated zoneDSJunction temperature and body diode conduction voltage VFThe relation with the junction temperature and respectively used as a temperature correction curve library when the SiC power VDMOS device is switched on and switched off;
step five: connecting the SiC power VDMOS device to a power cycle experiment platform through a clamp, wherein the SiC power VDMOS device is in an initial state of being turned off, and setting a junction temperature range in which the SiC power VDMOS device normally works through a computer; grid source voltage V is provided for SiC power VDMOS device through linear power supplyGSMaking the SiC power VDMOS device in a conducting state;
step six: connecting the SiC power VDMOS device with a power supply, and applying constant drain-source current I to the device via the power supplyDSCollecting the drain-source current V of the device through a power cycle experiment platformDSUploading the temperature data to a computer, calculating junction temperature according to the temperature correction curve library obtained in the fourth step when the SiC power VDMOS device is conducted, and when the junction temperature is higher than a set maximum value, issuing a turn-off instruction by the computer and applying a negative gate voltage VGSMaking the SiC power VDMOS device in a turn-off state;
step seven: connecting the SiC power VDMOS device with a digital source meter, and applying constant on-state current I to the body diode in the SiC power VDMOS device through the digital source meterF(conduction Current I)FSmaller), the conduction voltage V of the device is acquired through a power cycle experiment platformFUploading the temperature data to a computer, calculating junction temperature according to the temperature correction curve library obtained in the fourth step when the SiC power VDMOS device is turned off, and when the junction temperature is lower than a set minimum value, issuing a turn-on instruction by the computer and turning on a gate voltage VGSMaking the SiC power VDMOS device in a conducting state;
step eight: the variation relation between the power applied to the device and the junction temperature of the SiC power VDMOS device can be obtained through the sixth step and the seventh step; and (4) setting cycle times through a computer, namely repeating the sixth step and the seventh step to perform power cycle experiments on the SiC power VDMOS device for multiple times so as to realize real-time measurement and control of the junction temperature of the SiC power VDMOS device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010671317.3A CN112014707A (en) | 2020-07-13 | 2020-07-13 | Method for measuring and controlling junction temperature of SiC power VDMOS device in power cycle experiment |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113437857A (en) * | 2021-06-23 | 2021-09-24 | 桂林电子科技大学 | SiCMOSFET junction temperature smooth control method and system based on parasitic body diode conduction loss adjustment |
| CN113760033A (en) * | 2021-09-08 | 2021-12-07 | 中国电子科技集团公司第二十四研究所 | Packaging structure of voltage reference chip and output voltage temperature compensation method |
| CN114217198A (en) * | 2021-12-07 | 2022-03-22 | 北京工业大学 | Short-pulse heavy-current-based SiC MOSFET module thermal resistance measurement method |
| CN114325286A (en) * | 2021-12-31 | 2022-04-12 | 浙江大学杭州国际科创中心 | SiC MOSFET power cycle test circuit and control method thereof |
| CN114764116A (en) * | 2020-12-31 | 2022-07-19 | 浙江杭可仪器有限公司 | Test circuit and test method of MOSFET |
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Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3809929A (en) * | 1971-06-21 | 1974-05-07 | Centre Electron Horloger | Temperature sensing device |
| JP2006047039A (en) * | 2004-08-03 | 2006-02-16 | Fuji Electric Device Technology Co Ltd | Temperature detection circuit, and power semiconductor device provided with temperature detection circuit |
| CN101029910A (en) * | 2007-03-22 | 2007-09-05 | 华为技术有限公司 | Current inspecting circuit and device |
| JP2008283498A (en) * | 2007-05-10 | 2008-11-20 | Sharp Corp | Current sensing device |
| US20080319690A1 (en) * | 2007-06-20 | 2008-12-25 | Usa As Represented By The Administrator Of The National Aeronautics & Space Administration | Forward Voltage Short-Pulse Technique for Measuring High Power Laser Diode Array Junction Temperature |
| WO2009095817A1 (en) * | 2008-01-31 | 2009-08-06 | Koninklijke Philips Electronics N.V. | Lighting unit and thermal management system and method therefor |
| CN105158667A (en) * | 2015-08-25 | 2015-12-16 | 同济大学 | Junction-temperature measurement system and junction-temperature measurement method for power diode of converter |
| CN106443400A (en) * | 2016-09-14 | 2017-02-22 | 河北工业大学 | Electric-heat-aging junction temperature calculation model establishing method of IGBT module |
| CN106771951A (en) * | 2016-12-31 | 2017-05-31 | 徐州中矿大传动与自动化有限公司 | Electronic power switch device junction temperature on-Line Monitor Device, detection circuit and method of testing |
| CN106817113A (en) * | 2015-12-01 | 2017-06-09 | 通用电气公司 | For the system and method for the overcurrent protection of field ring shift switch |
| CN106896307A (en) * | 2017-01-18 | 2017-06-27 | 浙江大学 | A kind of modeling method of silicon carbide MOSFET on-resistance characteristics |
| CN107957299A (en) * | 2017-11-27 | 2018-04-24 | 电子科技大学 | A kind of carborundum linear temperature sensor and its temp measuring method and manufacture method |
| US20180172522A1 (en) * | 2016-12-15 | 2018-06-21 | Hyundai Motor Company | System and method for measuring junction temperature of power module |
| US20180372553A1 (en) * | 2016-02-18 | 2018-12-27 | Mitsubishi Electric Corporation | Method and device for determining junction temperature of die of semiconductor power module |
| CN109738773A (en) * | 2018-06-19 | 2019-05-10 | 北京航空航天大学 | IGBT module life-span prediction method under a kind of non-stationary operating condition |
| CN109932629A (en) * | 2019-04-02 | 2019-06-25 | 北京工业大学 | The method of measurement and control power VDMOSFET device junction temperature in a kind of experiment of power cycle |
| CN109994993A (en) * | 2017-12-28 | 2019-07-09 | 瑞萨电子株式会社 | Power conversion device and semiconductor device |
| US20190250046A1 (en) * | 2018-02-14 | 2019-08-15 | Infineon Technologies Ag | Systems and methods for measuring transistor junction temperature while operating |
| US20190377023A1 (en) * | 2017-12-06 | 2019-12-12 | Nanjing Estun Automation Co., Ltd | Real-time online prediction method for dynamic junction temperature of semiconductor power device |
| CN111060798A (en) * | 2019-12-18 | 2020-04-24 | 中国测试技术研究院流量研究所 | Automatic power aging test system and test method for MOS (metal oxide semiconductor) tube |
| WO2020087928A1 (en) * | 2018-10-28 | 2020-05-07 | 北京工业大学 | Power cycle experiment device for automotive-grade igbt multi-junction temperature difference control |
-
2020
- 2020-07-13 CN CN202010671317.3A patent/CN112014707A/en active Pending
Patent Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3809929A (en) * | 1971-06-21 | 1974-05-07 | Centre Electron Horloger | Temperature sensing device |
| JP2006047039A (en) * | 2004-08-03 | 2006-02-16 | Fuji Electric Device Technology Co Ltd | Temperature detection circuit, and power semiconductor device provided with temperature detection circuit |
| CN101029910A (en) * | 2007-03-22 | 2007-09-05 | 华为技术有限公司 | Current inspecting circuit and device |
| JP2008283498A (en) * | 2007-05-10 | 2008-11-20 | Sharp Corp | Current sensing device |
| US20080319690A1 (en) * | 2007-06-20 | 2008-12-25 | Usa As Represented By The Administrator Of The National Aeronautics & Space Administration | Forward Voltage Short-Pulse Technique for Measuring High Power Laser Diode Array Junction Temperature |
| WO2009095817A1 (en) * | 2008-01-31 | 2009-08-06 | Koninklijke Philips Electronics N.V. | Lighting unit and thermal management system and method therefor |
| CN105158667A (en) * | 2015-08-25 | 2015-12-16 | 同济大学 | Junction-temperature measurement system and junction-temperature measurement method for power diode of converter |
| CN106817113A (en) * | 2015-12-01 | 2017-06-09 | 通用电气公司 | For the system and method for the overcurrent protection of field ring shift switch |
| US20180372553A1 (en) * | 2016-02-18 | 2018-12-27 | Mitsubishi Electric Corporation | Method and device for determining junction temperature of die of semiconductor power module |
| CN106443400A (en) * | 2016-09-14 | 2017-02-22 | 河北工业大学 | Electric-heat-aging junction temperature calculation model establishing method of IGBT module |
| US20180172522A1 (en) * | 2016-12-15 | 2018-06-21 | Hyundai Motor Company | System and method for measuring junction temperature of power module |
| CN106771951A (en) * | 2016-12-31 | 2017-05-31 | 徐州中矿大传动与自动化有限公司 | Electronic power switch device junction temperature on-Line Monitor Device, detection circuit and method of testing |
| CN106896307A (en) * | 2017-01-18 | 2017-06-27 | 浙江大学 | A kind of modeling method of silicon carbide MOSFET on-resistance characteristics |
| CN107957299A (en) * | 2017-11-27 | 2018-04-24 | 电子科技大学 | A kind of carborundum linear temperature sensor and its temp measuring method and manufacture method |
| US20190377023A1 (en) * | 2017-12-06 | 2019-12-12 | Nanjing Estun Automation Co., Ltd | Real-time online prediction method for dynamic junction temperature of semiconductor power device |
| CN109994993A (en) * | 2017-12-28 | 2019-07-09 | 瑞萨电子株式会社 | Power conversion device and semiconductor device |
| US20190250046A1 (en) * | 2018-02-14 | 2019-08-15 | Infineon Technologies Ag | Systems and methods for measuring transistor junction temperature while operating |
| CN109738773A (en) * | 2018-06-19 | 2019-05-10 | 北京航空航天大学 | IGBT module life-span prediction method under a kind of non-stationary operating condition |
| WO2020087928A1 (en) * | 2018-10-28 | 2020-05-07 | 北京工业大学 | Power cycle experiment device for automotive-grade igbt multi-junction temperature difference control |
| CN109932629A (en) * | 2019-04-02 | 2019-06-25 | 北京工业大学 | The method of measurement and control power VDMOSFET device junction temperature in a kind of experiment of power cycle |
| CN111060798A (en) * | 2019-12-18 | 2020-04-24 | 中国测试技术研究院流量研究所 | Automatic power aging test system and test method for MOS (metal oxide semiconductor) tube |
Non-Patent Citations (2)
| Title |
|---|
| HARALD KUHN; AXEL MERTENS: "On-line junction temperature measurement of IGBTs based on temperature sensitive electrical parameters", 2009 13TH EUROPEAN CONFERENCE ON POWER ELECTRONICS AND APPLICATIONS, vol. 1, pages 60 - 63 * |
| 卫能;刘斯扬;万维俊;孙伟锋;: "一种测试功率MOSFET热阻的新方法", 微电子学, vol. 44, no. 01, pages 131 - 134 * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114764116A (en) * | 2020-12-31 | 2022-07-19 | 浙江杭可仪器有限公司 | Test circuit and test method of MOSFET |
| CN113437857A (en) * | 2021-06-23 | 2021-09-24 | 桂林电子科技大学 | SiCMOSFET junction temperature smooth control method and system based on parasitic body diode conduction loss adjustment |
| CN113437857B (en) * | 2021-06-23 | 2022-12-20 | 桂林电子科技大学 | SiC MOSFET junction temperature smoothing control method and system based on parasitic body diode conduction loss adjustment |
| CN113760033A (en) * | 2021-09-08 | 2021-12-07 | 中国电子科技集团公司第二十四研究所 | Packaging structure of voltage reference chip and output voltage temperature compensation method |
| CN114217198A (en) * | 2021-12-07 | 2022-03-22 | 北京工业大学 | Short-pulse heavy-current-based SiC MOSFET module thermal resistance measurement method |
| CN114217198B (en) * | 2021-12-07 | 2023-10-10 | 北京工业大学 | Short pulse-based high-current SiC MOSFET module thermal resistance measurement method |
| CN114325286A (en) * | 2021-12-31 | 2022-04-12 | 浙江大学杭州国际科创中心 | SiC MOSFET power cycle test circuit and control method thereof |
| CN117148092A (en) * | 2023-11-01 | 2023-12-01 | 深圳基本半导体有限公司 | Test method and device for accelerating bipolar degradation of SiC MOSFET |
| CN117148092B (en) * | 2023-11-01 | 2024-03-12 | 深圳基本半导体有限公司 | Test method and device for accelerating bipolar degradation of SiC MOSFET |
| CN117761491A (en) * | 2023-12-22 | 2024-03-26 | 合肥安赛思半导体有限公司 | Aging experiment and pulse test system and method for SiC MOSFET device |
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