CN112003616B - Dual-mode prescaler circuit, dual-mode frequency divider, phase-locked loop and chip - Google Patents
Dual-mode prescaler circuit, dual-mode frequency divider, phase-locked loop and chip Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention discloses a dual-mode prescaler circuit, a dual-mode frequency divider, a phase-locked loop and a chip, wherein the dual-mode prescaler circuit comprises a maximum frequency division modulus/2D triggers which are sequentially connected in series, the dual-mode prescaler circuit comprises frequency division switch units with the number of preset selectable modes, input control ends arranged by the frequency division switch units are used for receiving mode gating signals based on the currently selected frequency division modes, one switch end of each frequency division switch unit is connected with a data input end of the matched D trigger, so that after the mode gating signals gate the frequency division switch units, the dual-mode prescaler circuit is multiplexed into the currently selected frequency division modulus/(the currently selected frequency division modulus+1) dual-mode frequency divider; wherein the ratio of the maximum frequency division modulus to 2 is greater than or equal to the number of preset selectable modes.
Description
Technical Field
The invention belongs to the technical field of signal frequency division, and particularly relates to a dual-mode prescaler circuit, a dual-mode frequency divider, a phase-locked loop and a chip.
Background
A Phase Locked Loop (PLL) is a very important functional system, such as providing one or more clocks with frequency requirements in a system on a chip, generating local oscillator signals in a receiver, maintaining synchronization in a communication system, etc.; in general, phase locked loops are classified into integer phase locked loops and fractional phase locked loops. More commonly used fractional phase locked loops include Phase Frequency Detectors (PFD), charge Pumps (CP), low Pass Filters (LPF), voltage Controlled Oscillators (VCO), SDM modulators, frequency dividers, where the frequency dividers require the use of a dual-mode frequency divider ((divide by N (n+1)) divider) or a multi-mode frequency divider (MMD DIVIDER); the decimal phase-locked loop compares feedback of the reference frequency and the output frequency through the frequency-frequency phase detector, outputs a control signal, controls the charge pump to flow in and flow out of the low-pass filter, so as to adjust the output voltage of the low-pass filter, adjusts the voltage-controlled oscillator through the output voltage of the low-pass filter, so as to control and change the output frequency of the voltage-controlled oscillator, divides the output signal of the voltage-controlled oscillator through a double-mode frequency divider (divide by N (n+1)) divider or a multiple-mode frequency divider (MMD DIVIDER), and feeds back to the frequency-frequency phase detector, so that the output control signal of the frequency-frequency phase detector is adjusted, and the frequency-phase detector is circulated until the reference frequency and the output frequency are equal or are in a multiple N relation. It should be noted that, both the multi-mode frequency divider and the dual-mode frequency divider belong to a high-speed programmable frequency divider, and a digital circuit is used to realize the frequency division variable function. The multi-mode frequency divider has simple structure and easy realization, but compared with the dual-mode frequency divider, the multi-mode frequency divider has more stages and larger occupied area when the frequency division number is larger, and the frequency division ratio range which can be realized is smaller; the dual-mode frequency divider has simple structure and small occupied area, but the frequency division ratio range realized by the dual-mode frequency divider is still limited.
In some applications, the dual-mode frequency divider is often selected according to the requirement of the output frequency, if the range of the wide frequency dividing ratio is desired, a smaller frequency dividing module N needs to be set, but under the condition that the upper limit value of the range of the frequency dividing ratio is ensured to be unchanged, the counting bit number of the programmable program counter and the counting bit number of the pulse swallowing counter need to be set larger, at this time, if the counting bit number of the programmable program counter and the counting bit number of the pulse swallowing counter need to be set smaller, a larger frequency dividing module N needs to be set for the dual-mode frequency divider, after the larger frequency dividing module N is set for the dual-mode frequency divider, a wider frequency dividing ratio range is difficult to realize, so that the best performance is often not achieved, and when the simulation verification of different dual-mode frequency dividers is adopted, the manual replacement of different modules is also required to become troublesome, the module call is inconvenient, the efficiency of design and development is reduced, and the occupation area of the control structure used by additional matching is increased.
Disclosure of Invention
The invention aims to solve the defects of the related technology at least to a certain extent, and therefore, the invention mainly aims to provide a dual-mode prescaler circuit, a dual-mode frequency divider, a phase-locked loop and a chip.
The dual-mode prescaler circuit comprises a maximum frequency division modulus/2D triggers which are sequentially connected in series, the dual-mode prescaler circuit comprises frequency division switch units with preset selectable dual modes, input control ends arranged by the frequency division switch units are used for receiving a mode gating signal based on a currently selected frequency division mode, one switch end of each frequency division switch unit is connected with a data input end of the matched D trigger, and after the frequency division switch units are gated by the mode gating signal, the dual-mode prescaler circuit is multiplexed into a currently selected frequency division modulus/(currently selected frequency division modulus+1) dual-mode frequency divider; the maximum frequency division modulus is the maximum value of frequency division modulus in preset selectable double-modulus frequency division modes, the currently selected frequency division modulus is the corresponding frequency division modulus value in the currently selected frequency division mode, and the currently selected frequency division mode is one of the preset selectable double-modulus frequency division modes; the ratio of the maximum frequency division modulus to2 is greater than or equal to a preset selectable dual mode number.
Compared with the prior art, the technical scheme realizes the selection and use of the proper dual-mode frequency divider by multiplexing the dual-mode prescaler circuit structure according to the frequency division work requirement, improves the adaptability of the dual-mode prescaler circuit, multiplexes the structure of the same traditional dual-mode frequency divider into the dual-mode frequency divider in multiple frequency division modes, and reduces the occupied area of an additional circuit.
Further, the structure form that a switch switching end of each frequency division switching unit is connected with the data input end of the matched D flip-flop is as follows: the data input end of the currently selected frequency division modulus/2D triggers which are sequentially connected in series is connected with the fourth switch switching end of the frequency division switching unit corresponding to the currently selected frequency division mode, wherein the currently selected frequency division modulus is any frequency division modulus in the preset selectable double-mode number frequency division modes; the second switch switching end of the frequency division switching unit corresponding to the currently selected frequency division mode is connected with the positive output end of the currently selected frequency division modulus/2+1D triggers which are sequentially connected in series, wherein the currently selected frequency division modulus is not the maximum frequency division modulus; the dual-mode pre-frequency dividing circuit comprises +1D triggers with the preset selectable dual-mode quantity; the maximum frequency division modulus is the maximum value of the frequency division modulus in a preset selectable double-modulus frequency division mode configured in advance, and the currently selected frequency division modulus is the corresponding frequency division modulus value in the currently selected frequency division mode. The frequency division mode can be expanded according to design requirements, and the method is as follows: how many frequency division modes are needed, how many switches are configured, signals of input ends are configured according to the number of frequency division switching switch units of the dual-mode prescaler circuit, and idle ports of a switch structure are reduced.
Further, only one mode gating signal in the input control end of the preset selectable dual-mode frequency division switching unit is effective, so that the frequency division switching unit gated by the effective mode gating signal disconnects the serial connection relation between the D trigger connected with the second switch switching end and the D trigger connected with the fourth switch switching end, and connects the third switch switching end and the fourth switch switching end, but other frequency division switching units connect the D trigger connected with the second switch switching end and the D trigger connected with the fourth switch switching end in series. The second switch switching unit corresponding to the maximum frequency division modulus is arranged at the ground. According to the technical scheme, the frequency division mode can be expanded on the basis of a general dual-mode frequency divider and multiplexing of the dual-mode frequency divider structure is achieved, so that the whole area is slightly increased compared with that of the traditional N and N+1 dual-mode structure.
Further, the dual-mode prescaler circuit specifically comprises N/2D flip-flops which are used for dividing frequency and are sequentially connected in series, one D flip-flop which is used for latching, a first NAND gate and a second NAND gate; n is the maximum divide modulus; the data input end of the D trigger for latching is connected with the output end of the first NAND gate, the second input end of the first NAND gate is used for being connected with a frequency division mode switching control signal generated by the counting of an external counter, the positive output end of the D trigger for latching is connected with the second input end of the second NAND gate, and the clock input ends of the D trigger for latching are connected with a clock signal to be divided; among the N/2D flip-flops which are sequentially connected in series and used for frequency division, the positive output end of the first D flip-flop is connected with the first input end of the second NAND gate, the reverse output end of the first D flip-flop is connected with the first input end of the first NAND gate, and the data input end of the N/2D flip-flop is connected with the fourth switch switching end of the frequency division switching unit corresponding to the maximum frequency division modulus; wherein the clock input ends of the N/2D flip-flops used for frequency division are connected with a clock signal to be frequency-divided. The connection structure of the D trigger supports the dual-mode prescaler circuit to stably select one frequency division mode meeting the requirement of input control signals from preset selectable dual-mode quantity frequency division modes.
Further, the frequency division switching unit further comprises a first switching end, a first inverter, a second inverter, a third inverter, a first transmission gate, a second transmission gate and a third transmission gate; the input control end is connected with the input end of the second inverter, the output end of the second inverter is connected with the inversion control end of the second transmission gate, the output end of the second transmission gate is connected with the fourth switch end, the normal phase control end of the second transmission gate is connected with the input control end, and the third switch end is connected with the input end of the second transmission gate; the input control end is connected with the input end of the first inverter, the output end of the first inverter is connected with the normal phase control end of the first transmission gate, the switching control end is connected with the reverse phase control end of the first transmission gate, the first switch switching end is connected with the output end of the first transmission gate, and the input end of the first transmission gate is connected with the third switch switching end; the input control end is connected with the input end of the third inverter, the output end of the third inverter is connected with the normal phase control end of the third transmission gate, the switching control end is connected with the reverse phase control end of the third transmission gate, the second switch switching end is connected with the input end of the third transmission gate, and the output end of the third transmission gate is connected with the fourth switch switching end. Compared with the prior art, the frequency division switching unit disclosed by the technical scheme realizes a frequency division mode switch control logic unit structure capable of simultaneously switching multiple ports.
Further, the frequency division switching unit further comprises a first switching end (11), a third switching end (13), a second inverter (INV 2), a third inverter (INV 3), a second transmission gate (T2) and a third transmission gate (T3); the input control end is connected with the input end of a second inverter (INV 2), the output end of the second inverter (INV 2) is connected with the reverse phase control end of a second transmission gate (T2), the output end of the second transmission gate (T2) is connected with a fourth switch switching end (14), the normal phase control end of the second transmission gate (T2) is connected with the input control end, and a third switch switching end (13) is connected with the input end of the second transmission gate (T2); the first switch switching end (11) is connected with the third switch switching end (13); the input control end is connected with the input end of a third inverter (INV 3), the output end of the third inverter (INV 3) is connected with the normal phase control end of a third transmission gate (T3), the switching control end is connected with the reverse phase control end of the third transmission gate (T3), the second switch switching end (12) is connected with the input end of the third transmission gate (T3), and the output end of the third transmission gate (T3) is connected with a fourth switch switching end (14). Compared with the technical scheme of the frequency division change-over switch unit, the connection structure of the first inverter and the first transmission gate is omitted, and the occupied area of a circuit is reduced.
A dual-mode frequency divider comprising a programmable program counter and a programmable pulse swallow counter; the frequency division modulus selectable dual-mode frequency divider also comprises a decoder and the dual-mode prescaler circuit; the input end of the decoder is used for inputting a control signal, the modulus selection input end of the dual-mode prescaler circuit is correspondingly connected with the decoding output end of the decoder, and the dual-mode prescaler circuit is used for gating into the currently selected frequency division mode through the modulus selection input end according to the frequency division modulus decoding result of the decoder on the input control signal; the input control end of the frequency division switching unit in the dual-mode prescaler circuit is used as the analog-digital selection input end of the dual-mode prescaler circuit.
According to the dual-mode frequency divider disclosed by the technical scheme, the dual-mode frequency dividing circuit structures of multiple frequency dividing modes are combined in the same dual-mode frequency divider in a structure multiplexing mode, so that the dual-mode frequency divider which is limited in frequency dividing range and has compromised performance is multiplexed into the dual-mode frequency divider of the multiple frequency dividing modes, the increase of the circuit is less, and a larger area is saved; meanwhile, great convenience is provided for design simulation of the phase-locked loop, the modulus of the frequency divider can be adjusted according to the performance effect, and the best-fit dual-mode frequency divider can be selected according to different requirements so as to achieve the best effect. The number of counting bits of the conventional programmable program counter and the number of counting bits of the conventional programmable pulse swallowing counter are saved because the preset selectable modes are enough.
Further, when the decoder is provided with decoding output ends with preset selectable double mode numbers, the double-mode pre-frequency dividing circuit is provided with frequency dividing switch units with preset selectable double mode numbers, and input control ends of the frequency dividing switch units are respectively connected with the decoding output ends with preset selectable double mode numbers in the decoder in a one-to-one correspondence mode, so that the input control ends of the frequency dividing switch units are respectively matched with different frequency dividing modes with the preset selectable double mode numbers in a corresponding mode. Therefore, the optimal dual-mode frequency divider can be decoded and combined according to different simulation design requirements, and the same dual-mode frequency divider structure is multiplexed into the dual-mode frequency divider structure in multiple frequency division modes with the decoding result gating.
Further, the dual-mode frequency divider is configured to gate a frequency-dividing switch unit matching a currently selected frequency-dividing mode according to a decoding result of the input control signal by the decoder, and when the frequency-dividing switch unit matching the currently selected frequency-dividing mode disconnects a series connection relationship between the D flip-flop connected to the second switch terminal and the D flip-flop connected to the fourth switch terminal, and simultaneously control other frequency-dividing switch units to connect the D flip-flop connected to the second switch terminal and the D flip-flop connected to the fourth switch terminal in series according to a decoding result of the input control signal by the decoder, so that a currently selected frequency-dividing modulus/2D flip-flops on one side of the fourth switch terminal of the frequency-dividing switch unit matching the currently selected frequency-dividing mode are sequentially connected in series to be multiplexed into a currently selected frequency-dividing modulus/(currently selected frequency-dividing modulus+1) dual-mode frequency divider. Compared with the prior art, the technical scheme firstly controls the matched multiple frequency division switching switch units according to the decoding result, and then controls the number of the actual serial connection of the D trigger through different frequency division switching switch units, so that the most suitable dual-mode frequency divider can be decoded and combined according to different simulation design requirements, the optimal debugging effect is achieved, the same dual-mode frequency divider structure is multiplexed into the dual-mode frequency divider structure in multiple frequency division modes with the matched decoding result, and meanwhile, the control signals of the programmable program counter and the programmable pulse swallowing counter are multiplexed.
The phase-locked loop comprises a frequency-dividing phase discriminator, a charge pump, an SDM modulator, a filter and a voltage-controlled oscillator which are sequentially connected, the phase-locked loop further comprises a dual-mode frequency divider with selectable frequency dividing modulus, the voltage-controlled oscillator provides a clock signal to be divided for the dual-mode frequency divider, the SDM modulator provides a preset target frequency dividing ratio of the clock signal to be divided for the dual-mode frequency divider, the dual-mode frequency divider carries out frequency dividing processing on the clock signal to be divided according to a frequency dividing mode matched with the preset target frequency dividing ratio, and then a feedback signal is output to the frequency-dividing phase discriminator. The dual-mode prescaler circuit in the dual-mode frequency divider with selectable frequency division modulus comprises frequency division change-over switch units with preset selectable dual-mode quantity, wherein the input control ends of the frequency division change-over switch units are used as modulus selection input ends of the dual-mode prescaler circuit and are respectively connected with decoding output ends matched with the decoder; each frequency division switching unit is connected between two adjacent matched D triggers, so that after the frequency division switching units are gated by frequency division analog-digital decoding results corresponding to input control signals, the dual-mode prescaler circuit enters a currently selected frequency division mode and equivalently forms a currently selected frequency division analog-digital/(currently selected frequency division analog-digital+1) dual-mode frequency divider, switching expansion of the frequency division modes is achieved according to the decoding results, and the dual-mode frequency divider in multiple frequency division modes is multiplexed with the same traditional dual-mode frequency divider.
A chip comprising said phase locked loop. The switching expansion of the frequency division modes is completed according to the decoding result, and the same traditional dual-mode frequency divider is multiplexed into a dual-mode frequency divider in multiple frequency division modes.
Drawings
Fig. 1 is a block diagram of a dual-mode frequency divider with selectable divided modes according to an embodiment of the present invention.
FIG. 2 is a schematic diagram of a modulus selectable dual mode prescaler circuit according to one embodiment of the present invention, wherein the divided modulus is N, N > M, M being greater than or equal to 4.
Fig. 3 is a schematic diagram of the circuit connection of a modulus selectable dual mode prescaler circuit (there are 8 frequency dividing switch cells) with a decoder (thirty-eight decoder) in an embodiment where the frequency dividing mode is 4/5.
Fig. 4 is a schematic diagram of the circuit connection of a modulus selectable dual mode prescaler circuit (there are 8 frequency dividing switch cells) with a decoder (thirty-eight decoder) in an embodiment where the frequency dividing mode is 16/17.
Fig. 5 is a circuit equivalent schematic diagram of the aforementioned frequency division switching unit.
Fig. 6 is a block diagram of a phase locked loop including the dual mode divider described above.
Detailed Description
The following describes the technical solution in the embodiment of the present invention in detail with reference to the drawings in the embodiment of the present invention.
In the design of some frequency dividers, the frequency dividing range is often considered to make a compromise selection on the dual-mode frequency divider, the embodiment of the invention provides a dual-mode prescaler circuit, the adaptability of the dual-mode frequency divider suitable for the dual-mode prescaler circuit is improved through multiplexing of a plurality of structures and selection of control bits, a larger degree of freedom is provided for selecting the frequency dividing modulus, the occupied area of the control structure is smaller, meanwhile, the dual-mode prescaler circuit can be applied to occasions such as phase-locked loops, and the like, a larger convenience is provided for the design simulation of the phase-locked loops, the modulus of the frequency divider can be adjusted according to the performance effect, and the most suitable dual-mode frequency divider is selected according to different requirements so as to achieve the best effect.
As an embodiment, the invention discloses a dual-mode prescaler circuit, the dual-mode prescaler circuit comprises D triggers which are sequentially connected in series with a maximum frequency dividing module/2, the D triggers which are sequentially connected in series with the maximum frequency dividing module/2 are D triggers which are sequentially connected in series with a ratio of the maximum frequency dividing module to 2, the dual-mode prescaler circuit comprises a preset selectable dual-mode number frequency dividing switch unit, an input control end set by the frequency dividing switch unit is used for receiving a mode gating signal based on a currently selected frequency dividing mode, one switch end of each frequency dividing switch unit is connected with a data input end of the matched D trigger, so that after the mode gating signal gates the frequency dividing switch unit, the dual-mode prescaler circuit multiplexes the currently selected frequency dividing module/(the currently selected frequency dividing module+1) dual-mode frequency divider, when the number of the frequency dividing switch unit is equal to the maximum frequency dividing module/2, the input control end set by the frequency dividing switch unit is used for receiving a mode gating signal based on the currently selected frequency dividing mode, namely, the frequency dividing structure is in the preset selectable dual-mode number of the frequency dividing switch unit is preset in the preset mode, and the frequency dividing mode is preset in the preset mode number of the preset frequency dividing mode; the ratio of the maximum frequency division modulus to 2 is greater than or equal to a preset selectable dual mode number.
Specifically, the number of D flip-flops included in the dual-mode prescaler circuit is the maximum frequency division modulus/2+1, the dual-mode prescaler circuit includes frequency division switch units with preset selectable dual-mode numbers, and input control ends of the frequency division switch units serve as modulus selection input ends of the dual-mode prescaler circuit and respectively receive mode gating signals based on a currently selected frequency division mode; when the D trigger connected with the switch switching end of one frequency division switching unit exists, a switching control unit of one stage is formed, and the switching control unit of each stage is the same circuit structure unit; when the ratio of the maximum frequency division modulus to 2 is equal to the preset selectable double-modulus number, the maximum frequency division modulus/2 switch switching control units in the double-modulus prescaler circuit are sequentially connected in series, namely each frequency division switching unit is connected between two adjacent matched D triggers, so that after the frequency division switching units are gated by a mode gating signal of the currently selected frequency division mode, the double-modulus prescaler circuit enters the currently selected frequency division mode and equivalently forms the currently selected frequency division modulus/(the currently selected frequency division modulus+1) double-modulus divider. When the ratio of the maximum frequency division modulus to 2 is greater than the preset number of selectable modes, the input control ends of the frequency division switching units respectively correspond to different frequency division modes matched with the preset number of selectable modes, but the number of the frequency division switching units is smaller than the number of D triggers which are sequentially connected in series in the dual-mode prescaler circuit, and in the embodiment, as long as the mode gating signals received by the input control ends of the frequency division switching units can control the dual-mode prescaler circuit to switch and work in the preset number of selectable modes. Therefore, the ratio of the maximum frequency division modulus to 2 in the preset selectable dual-modulus number of frequency division modes is greater than or equal to the preset selectable dual-modulus number, wherein the maximum number of D flip-flops actually participating in frequency division in the present embodiment is the ratio of the maximum frequency division modulus to 2. Therefore, the number of the frequency division switching units of the dual-mode prescaler circuit can be adjusted according to actual design requirements, and the use amount of the frequency division switching units can be reduced.
Compared with the prior art, the dual-mode frequency divider with the selectable frequency dividing modulus disclosed in the embodiment combines the dual-mode frequency dividing circuit structures of multiple frequency dividing modes into the same dual-mode frequency divider in a structural multiplexing mode, so that a proper preset dual-mode frequency divider is selected to be used according to the requirement of frequency dividing work, the adaptability of the dual-mode frequency divider is improved, the dual-mode frequency divider with the limited frequency dividing range and the compromised performance is multiplexed into the dual-mode frequency divider of multiple frequency dividing modes, the self-adaptive adjustment frequency dividing mode is supported, the increase of the circuit is less, and the larger area is saved; the freedom degree of the conventional design process is greatly improved because of more preset selectable modules.
As an embodiment, the structure that one switch switching end of each frequency division switching switch unit is connected with the data input end of the matched D flip-flop is as follows: the data input end of the currently selected frequency division modulus/2D triggers which are sequentially connected in series is connected with the fourth switch switching end arranged by the frequency division switching unit corresponding to the currently selected frequency division mode, and is regarded as an internal connection structure of the switch switching control unit of the currently selected frequency division modulus/2 level, wherein the currently selected frequency division modulus is any frequency division modulus in preset selectable double-mode number frequency division modes which are configured in advance; The second switch switching end set by the frequency division switching unit corresponding to the currently selected frequency division mode is connected with the positive output end of the currently selected frequency division modulus/2+1D triggers which are sequentially connected in series, wherein the currently selected frequency division modulus is not the maximum frequency division modulus, the connection relation between the switch switching control unit of the currently selected frequency division modulus/2 stage and the currently selected frequency division modulus/2+1D triggers is considered, and if the frequency division switching control unit for receiving and gating the frequency division switching unit which enters the matched frequency division mode is connected with the currently selected frequency division modulus/2+1D triggers, the connection relation between the switch switching control unit of the currently selected frequency division modulus/2 stage and the switch switching control unit of the currently selected frequency division modulus/2+1 stage is considered. the dual-mode prescaler circuit comprises a preset selectable dual-mode number of +1D triggers; the maximum frequency division modulus is the maximum value of the frequency division modulus in a preset selectable double-modulus frequency division mode configured in advance, and the currently selected frequency division modulus is the corresponding frequency division modulus value in the currently selected frequency division mode. As shown in fig. 2, the present embodiment discloses a schematic circuit diagram of a dual-mode prescaler circuit with selectable modulus, wherein the divided modulus is N, N > M, M is greater than or equal to 4, and N and M are both even numbers; in this embodiment, the maximum frequency division modulus set by the actual design requirement is N, and the preset selectable dual-mode number of the selectable frequency division modes is required to be set, and then the preset selectable dual-mode number is N/2; the dual mode prescaler circuit shown in fig. 2 is provided with N/2+1D flip-flops including D flip-flop d_0, D flip-flop d_1, D flip-flops d_2, …, D flip-flops d_m/2, …, D flip-flop d_n/2; the data input ends of the D triggers D_1, D triggers D_2, …, D triggers D_M/2, … and D triggers D_N/2 are respectively connected with a matched frequency division switching unit, wherein the input control end of the frequency division switching unit connected with the D trigger D_1 is used for receiving a Mode gating signal mode_2/3 matched with a 2/3 frequency division Mode; The input control end of the frequency division switching unit connected with the D trigger D_2 is used for receiving a Mode gating signal Mode_4/5 matched with a 4/5 frequency division Mode; the input control end of the frequency division switching unit connected with the D trigger D_N is used for receiving a Mode gating signal mode_N/(N+1) matched with the N/(N+1) frequency division Mode. The frequency division mode can be expanded according to design requirements, and the method achieves the following steps: how many frequency dividing modes are needed, how many switches are configured to realize the effect of selecting the type of control signal (including the control bits of the signal) at the input end according to the number of frequency dividing switch units of the dual-mode prescaler circuit.
It should be noted that the aforementioned currently selected divided modulus/2 stage is the (currently selected divided modulus 2 ratio) stage, the currently selected divided modulus/2 is the (currently selected divided modulus 2 ratio) stage, the currently selected divided modulus/2+1 stage is the (currently selected divided modulus 2 ratio and 1 sum) stage, and the currently selected divided modulus/2+1 (currently selected divided modulus 2 ratio and 1 sum) stage.
As an embodiment, M is a matched frequency division module configured according to design requirements, in fig. 2, a data input end of an M/2 th D flip-flop d_m sequentially connected in series is connected with a second switch end set by a frequency division switch unit corresponding to the matched frequency division Mode (M/(m+1) frequency division Mode), and an input control end of the frequency division switch unit connected with the D flip-flop d_m is used for receiving a Mode strobe signal mode_m/(m+1) frequency division Mode; the positive output end of the M/2+1D trigger which is connected in series in sequence is connected with the fourth switch switching end of the frequency division switching unit corresponding to the matched frequency division mode ((M+2)/(M+3) frequency division mode), but the matched frequency division modulus M+2 is not the maximum frequency division modulus; the matched frequency division modulus is based on the frequency division modulus under the frequency division mode corresponding to the matched input control end of the frequency division change-over switch unit; the ratio of the maximum frequency division modulus to 2 is equal to the preset selectable double-modulus number, the maximum frequency division modulus in fig. 2 is N, the preset selectable double-modulus number is N/2, and the double-mode prescaler circuit comprises N/2+1D flip-flops. Therefore, the method is very convenient to ensure the optimal performance of debugging when performing simulation verification.
Only one mode gating signal in the input control end of the frequency division switching unit is valid, so that the frequency division switching unit gated by the valid mode gating signal breaks the serial connection relation between the D trigger connected with the second switching end and the D trigger connected with the fourth switching end, but other frequency division switching units connect the D trigger connected with the second switching end and the D trigger connected with the fourth switching end in series. As shown in fig. 2, under the control of the Mode gating signal mode_m/(m+1), the frequency-dividing switch unit matching the M/(m+1) frequency-dividing Mode disconnects the series connection relationship between the D flip-flop d_m/2+1 connected to the second switch terminal and the D flip-flop d_m/2 connected to the fourth switch terminal, but other frequency-dividing switch units connect the D flip-flop connected to the second switch terminal and the D flip-flop connected to the fourth switch terminal in series, so that M/2D flip-flops are sequentially connected in series on one side of the fourth switch terminal of the frequency-dividing switch unit matching the M/(m+1) frequency-dividing Mode to form the M/(m+1) frequency divider; wherein the currently selected frequency division modulus M is the corresponding frequency division modulus in the currently selected (M/(m+1)) frequency division mode. The embodiment can expand the frequency division mode on the basis of a general dual-mode frequency divider and realize multiplexing control of the structure by utilizing the frequency division change-over switch unit.
As shown in fig. 2, the dual-mode prescaler circuit specifically includes N/2D flip-flops for frequency division, one D flip-flop d_0 for latching, a first nand gate NA1, and a second nand gate NA2, which are sequentially connected in series; n is the maximum divide modulus; the data input end of the D trigger D_0 used for latching is connected with the output end of the first NAND gate NA1, and the second input end of the first NAND gate NA1 is used for accessing a frequency division mode switching control signal generated by the counting of an external counter, such as a full-count output signal of a programmable pulse-swallowing counter in a conventional dual-mode frequency divider or other counters playing the role of the same frequency division mode switching; the positive output end of the D trigger D_0 used for latching is connected with the second input end of the second NAND gate NA2, and the clock input ends of the D trigger D_0 used for latching are connected with the clock signal Fosc to be divided; among the N/2D flip-flops connected in series in turn for frequency division, the positive output terminal of the first D flip-flop d_1 is connected with the first input terminal of the second nand gate NA2, the inverted output terminal of the first D flip-flop d_1 is connected with the first input terminal of the first nand gate NA1, and the data input terminal of the N/2D flip-flop d_n/2 is connected with the fourth switch switching terminal of the frequency division switching unit corresponding to the maximum frequency division modulus; the clock input ends of the N/2D flip-flops D_N/2 used for frequency division are connected with the clock signal Fosc to be frequency-divided. The connection structure of the D flip-flop in this embodiment supports the dual-mode prescaler circuit to stably select a frequency division mode satisfying the input control signal requirement from preset selectable dual-mode number frequency division modes.
As an embodiment, as shown in fig. 5, the frequency division switching unit further includes a first switch switching terminal 11, a second switch switching terminal 12, a third switch switching terminal 13, a fourth switch switching terminal 14, a first inverter INV1, a second inverter INV2, a third inverter INV3, a first transmission gate T1, a second transmission gate T2, and a third transmission gate T3; the input control end is used for inputting a Mode gating signal Mode; the input control end is connected with the input end of a second inverter INV2, the output end of the second inverter INV2 is connected with the inversion control end of a second transmission gate T2, the output end of the second transmission gate T2 is connected with a fourth switch switching end 14, the normal phase control end of the second transmission gate T2 is connected with the input control end, and a third switch switching end 13 is connected with the input end of the second transmission gate T2; The input control end is connected with the input end of the first inverter INV1, the first switch switching end 11 is connected with the inversion control end of the first transmission gate T1), the first switch switching end 11 is connected with the output end of the first transmission gate T1, the input end of the first transmission gate T1 is connected with the third switch switching end 13, the first switch switching end 11 is connected with the input end of the first inverter INV1, and the output end of the first inverter INV1 is connected with the non-inverting control end of the first transmission gate T1; the input control end is connected with the input end of the third inverter INV3, the output end of the third inverter INV3 is connected with the normal phase control end of the third transmission gate T3, the switching control end is connected with the reverse phase control end of the third transmission gate T3, the second switch switching end 12 is connected with the input end of the third transmission gate T3, and the output end of the third transmission gate T3 is connected with the fourth switch switching end 14. Compared with the prior art, the frequency division switching unit disclosed by the technical scheme realizes a frequency division mode switch control logic unit structure capable of simultaneously switching multiple ports. As can be seen from fig. 5, when the input control terminal of the frequency dividing and switching unit inputs the first control signal, i.e. the input control terminal inputs the low level (mode=0), the first transmission gate T1 communicates the first switch switching terminal 11 and the third switch switching terminal 13; the second transmission gate T2 blocks a path between the first switch terminal 11 and the fourth switch terminal 14; the third transmission gate T3 is connected to the second switch end 12 and the fourth switch end 14, which means that the D flip-flop whose positive output end is connected to the second switch end 12 and the D flip-flop whose data input end is connected to the fourth switch end 14 are connected in series, and the frequency division switching unit is not currently selected by the mode gating signal of the input control end to enter the matched frequency division mode. When the input control terminal of the frequency division switching unit inputs a second control signal, that is, the input control terminal inputs a high level (mode=1), the first transmission gate T1 blocks the path between the first switching terminal 11 and the third switching terminal 13; the second transmission gate T2 is communicated with the third switch switching end 13 and the fourth switch switching end 14; The third transmission gate T3 blocks the path between the second switch terminal 12 and the fourth switch terminal 14, which means that the D flip-flop whose positive output terminal is connected to the second switch terminal 12 and the D flip-flop whose data input terminal is connected to the fourth switch terminal 14 are not connected, so that the current input mode gating signal of the frequency dividing switch unit is selected to enter the matched frequency dividing mode, and the D flip-flops connected to the second switch terminal 12 and connected in series in equivalent are stopped, and the D flip-flops connected to the D flip-flop connected to the fourth switch terminal 14 and connected in equivalent in series in equivalent are operated in the matched frequency dividing mode. the embodiment completes the switching control of the frequency division mode of the dual-mode prescaler circuit by changing the level of the input control end of different frequency division switching units.
As another embodiment, the dual mode prescaler circuit may further use another frequency division switching unit including a first switching terminal 11, a second switching terminal 12, a third switching terminal 13, a fourth switching terminal 14, a second inverter INV2, a third inverter INV3, a second transmission gate T2 and a third transmission gate T3, but not including a first inverter INV1 and a first transmission gate T1, because the presence or absence of the first inverter INV1 and the first transmission gate T1 does not affect the function of the frequency division switching unit for switching the frequency division mode, the internal circuit configuration of the frequency dividing switching unit in the present embodiment is not the circuit configuration shown in fig. 5. The input control end is used for inputting a Mode gating signal Mode; the input control end is connected with the input end of a second inverter INV2, the output end of the second inverter INV2 is connected with the inversion control end of a second transmission gate T2, the output end of the second transmission gate T2 is connected with a fourth switch switching end 14, the normal phase control end of the second transmission gate T2 is connected with the input control end, and a third switch switching end 13 is connected with the input end of the second transmission gate T2; the input control end is connected with the input end of the third inverter INV3, the output end of the third inverter INV3 is connected with the normal phase control end of the third transmission gate T3, the switching control end is connected with the reverse phase control end of the third transmission gate T3, the second switch switching end 12 is connected with the input end of the third transmission gate T3, and the output end of the third transmission gate T3 is connected with the fourth switch switching end 14. Compared with the prior art, the frequency division switching unit disclosed by the technical scheme realizes a frequency division mode switch control logic unit structure capable of simultaneously switching multiple ports. When the input control terminal of the frequency division switching unit inputs a first control signal, that is, the input control terminal inputs a low level (mode=0), the first switching terminal 11 and the third switching terminal 13 are already directly connected; the second transmission gate T2 blocks a path between the first switch terminal 11 and the fourth switch terminal 14; the third transmission gate T3 is connected to the second switch terminal 12 and the fourth switch terminal 14, which means that the D flip-flop whose positive output terminal is connected to the second switch terminal 12 and the D flip-flop whose data input terminal is connected to the fourth switch terminal 14 are connected in series, and the frequency division switching unit is not currently selected by the mode gating signal of the input control terminal to enter the matched frequency division mode. When the input control terminal of the frequency division switching unit inputs a second control signal, that is, the input control terminal inputs a high level (mode=1), the first switch switching terminal 11 and the third switch switching terminal 13 are still connected; the second transmission gate T2 is communicated with the third switch switching end 13 and the fourth switch switching end 14; The third transmission gate T3 blocks the path between the second switch terminal 12 and the fourth switch terminal 14, which means that the D flip-flop with the positive output terminal Q connected to the second switch terminal 12 and the D flip-flop with the data input terminal connected to the fourth switch terminal 14 are not connected, so that the current input mode gating signal of the frequency division switching unit is selected to enter the matched frequency division mode, and the D flip-flops with the equivalent serial connection connected to the second switch terminal 12 are stopped, and the D flip-flop with the equivalent serial connection connected to the D flip-flop with the fourth switch terminal 14 is operated in the matched frequency division mode. Compared with the frequency division switching unit in the previous embodiment, the frequency division switching unit reduces the switch control circuit branch circuit consisting of one inverter and one transmission gate, and on the premise that the function of switching the frequency division mode of the frequency division switching unit is not affected, the maximum frequency division module devices are saved from the aspect of the whole dual-mode prescaler circuit, so that the occupied area of the circuit is reduced.
As shown in fig. 1, an embodiment of the present invention discloses a dual-mode frequency divider with selectable frequency dividing modes, which comprises a programmable program counter and a programmable pulse swallowing counter; the dual-mode frequency divider with optional frequency dividing modulus further comprises the dual-mode prescaler circuit and the decoder in the previous embodiment; the module selection input end of the module selectable dual-module prescaler circuit is correspondingly connected with the decoding output end of the decoder; the modulus-selectable dual-mode prescaler circuit is used for gating the input control signal into the currently selected frequency division mode through a modulus selection input end according to the frequency division modulus decoding result of the decoder on the premise that the counting bit number of the programmable program counter and the counting bit number of the programmable pulse swallowing counter are unchanged, and the frequency division modulus decoding result corresponds to the mode gating signal of fig. 1; in this embodiment, the preset frequency division modes with the selectable dual mode numbers are preconfigured, and the decoder is at least provided with decoding output ends with the selectable dual mode numbers, so that redundant ports exist at the decoding output ends, so that the subsequent dual mode pre-frequency division circuit can conveniently expand the frequency division modes, but the number of the input ends is selected according to the preset modulus corresponding to the number of the preconfigured frequency division modes, and the number of the D triggers which are used for frequency division and are sequentially connected in series and are set by the dual mode pre-frequency division circuit can be smaller than the number of the switching control units which can be formed by the D triggers of the previous embodiment and the corresponding matched frequency division switching units. The frequency division modulus decoding result is a frequency division mode which is selected from preset selectable double-modulus frequency division modes and meets the requirement of an input control signal; the counting bit number of the programmable program counter and the counting bit number of the programmable pulse swallowing counter are determined by the corresponding maximum frequency division modulus in the preset frequency division modes with the selectable double mode numbers, and when the maximum frequency division modulus is larger, the counting bit number is larger. Compared with the prior art, the method and the device have the advantages that the proper preset dual-mode frequency divider is selected and used according to the requirement of frequency division work, the adaptability of the dual-mode frequency divider is improved, the dual-mode frequency divider which is limited in frequency division range and has compromised performance is multiplexed into the dual-mode frequency divider with multiple frequency division modes, the occupied area of an additional control circuit is reduced, a larger area is saved, and the self-adaptive adjustment of the frequency division mode is supported; the number of the counting bits of the conventional programmable program counter and the number of the counting bits of the conventional programmable pulse swallowing counter are saved because the preset selectable modulus is more. And great convenience is provided for the design simulation of the phase-locked loop, the modulus of the frequency divider can be adaptively adjusted according to the performance effect, and the most suitable dual-mode frequency divider can be selected according to different requirements so as to achieve the best effect.
Preferably, the input control end of the frequency division switching unit needs to be connected with the decoding output end matched with the decoder, but the number of the input control ends of the frequency division switching unit is not necessarily larger than the number of all decoding output ends in the decoder, and the input control ends of the frequency division switching unit are not necessarily connected with all decoding output ends in the upper decoder. The input control end of the frequency division change-over switch unit needs to be connected with a decoding output end matched with the decoder, so that the multi-channel frequency division mode signal is converted into a few-bit signal to be controlled, and great convenience is provided for the design simulation of the phase-locked loop.
It should be noted that, in the embodiment of the present invention, the count value P of the programmable program counter is greater than a-2, the count value P of the programmable program counter is greater than or equal to the count value S of the programmable pulse-swallowing counter, and the count value S of the programmable pulse-swallowing counter is less than a; the minimum value of the count value P of the programmable program counter is a-1, and the minimum value of the count value S of the programmable pulse swallowing counter is 0. The count value P of the programmable program counter and the count value S of the programmable pulse-swallowing counter are thus both set for the maximum target frequency dividing modulus and the alternative maximum frequency dividing modulus of the clock signal to be divided of the dual-mode frequency divider to which the frequency dividing modulus is selectable. Because the control signals of the programmable program counter and the programmable pulse swallowing counter are multiplexed by the dual-mode prescaler circuit in the embodiment, the count bit number P of the programmable program counter and the count bit number S of the programmable pulse swallowing counter do not need to be changed, and compared with the prior art, the occupied area of the control structure used by additional matching is reduced.
In order to ensure that the frequency dividing modulus-selectable dual-mode frequency divider realizes a normal frequency dividing function and realizes a programmable continuous frequency dividing function of the dual-mode frequency divider. The programmable program counter and the programmable pulse swallowing counter are all common counter structures of the dual-mode frequency divider.
The phase-locked loop which can be used before the application day needs to be matched with a dual-mode frequency divider or a multi-mode frequency divider (MMD DIVIDER) to realize the change of the frequency dividing ratio and achieve the purpose of fractional frequency division, however, the frequency dividing range of the multi-mode frequency divider is smaller, the number of stages is more when the frequency dividing ratio is larger, and the consumption area is larger; the dual-mode frequency divider has certain advantages in area, and the frequency division range is expanded to a certain extent, but the limitation is still met, for example, the divide-by-a (a+1) dual-mode frequency divider has a minimum frequency division ratio of a (a-1) and a maximum frequency division ratio of Pmax a+ (a-1) as known by those skilled in the art.
When the count bit number P of the programmable program counter and the count bit number S of the programmable pulse-swallowing counter are both 4 bits, selecting which dual-mode frequency divider generally considers the frequency division range where the preset target frequency division ratio is located, for example, when the frequency division ratio range is required to be relatively large, the dual-mode frequency divider with relatively large frequency division modulus like dividing by 30 and 31 is not selected, because the minimum frequency division ratio achieved by dividing by 30 and 31 is a (a-1) =870, the maximum frequency division ratio is pmax+a (a-1) =479, and the minimum frequency division ratio achieved by dividing by 30 and 31 is extremely large; instead, a=8 is selected, that is, the minimum frequency division ratio of the divide-by-8 and divide-by-9 dual-mode frequency divider is 56, or a=5 is selected, that is, the minimum frequency division ratio of the divide-by-5 and divide-by-6 dual-mode frequency divider is 20, and the maximum frequency division ratio is determined by the count bit number P of the programmable program counter and the count bit number S of the pulse swallowing counter, when the values of P, S and a are set larger, the larger the frequency division ratio can be realized, the larger the minimum value of the frequency division ratio is, so that the problem that the maximum frequency division ratio is not large enough can be solved, but the power consumption and the area can be increased. In another example, if the frequency division ratio of the divide-by-a (a+1) dual-mode frequency divider is reduced to be smaller than the minimum frequency division ratio, the frequency division ratio is discontinuous. On the basis of keeping the maximum frequency division ratio unchanged, if the lower limit of the frequency division ratio is to be enlarged (the minimum frequency division ratio is to be reduced), the value of a needs to be reduced, and meanwhile, the count bit number P of the programmable program counter used with the dual-mode frequency divider and the count bit number S of the pulse swallowing counter need to be simultaneously lifted, so that the power consumption and the area are increased.
In fig. 1, the frequency-dividing modulus selectable dual-mode frequency divider is configured to trigger the programmable program counter and the programmable pulse-swallowing counter to count simultaneously when the frequency-dividing mode of the dual-mode frequency divider is a frequency-dividing mode of dividing a by a (a+1), and the dual-mode preset frequency-dividing circuit is set in a frequency-dividing state of (a+1), when the dual-mode preset frequency-dividing circuit receives a full-counted output signal of the programmable pulse-swallowing counter, that is, when the count value reaches a counting modulus S, the programmable pulse-swallowing counter transmits a control signal K to the dual-mode preset frequency-dividing circuit, the frequency-dividing modulus of the dual-mode preset frequency-dividing circuit is configured to be a, and the programmable pulse-swallowing counter stops counting when full, and the programmable program counter continues counting, wherein the control signal K is used as a control signal of the dual-mode preset frequency-dividing circuit to determine that the dual-mode frequency-dividing circuit performs a frequency division or (a+1) frequency division on an input clock signal to be divided by a; when the full output signal of the programmable program counter, namely the count value reaches the count module value P, a Reset signal Reset is output to the programmable pulse swallowing counter, the frequency dividing module of the dual-mode pre-frequency dividing circuit is reconfigured to be a+1, and the programmable program counter and the programmable pulse swallowing counter synchronously Reset and restart to count to start the next working period. In the current working period, the frequency division ratio of the input clock signal Fosc to be divided through the dual-mode prescaler circuit can be expressed as follows: ndiv= (a+1) s+a (P-S) =ap+s, so that, for each input of the two-mode prescaler ap+s clock signals, a frequency division signal Fdiv is output by the programmable program counter.
As an embodiment, when the decoder is provided with decoding output ends with preset selectable double-mode numbers, decoding results output by the decoding output ends respectively correspond to different frequency division modes with preset selectable double-mode numbers, the double-mode pre-frequency dividing circuit is provided with frequency dividing switch units with preset selectable double-mode numbers, and input control ends of the frequency dividing switch units are respectively connected with the decoding output ends with preset selectable double-mode numbers in the decoder in a one-to-one correspondence manner, so that the input control ends of the frequency dividing switch units respectively correspond to the different frequency dividing modes with preset selectable double-mode numbers; the dual-mode prescaler circuit comprises the preset selectable dual-mode number +1D flip-flops. The specific dual-mode frequency divider structure comprises the following steps: fig. 3 is a schematic circuit connection diagram of a dual mode prescaler circuit with selectable modulus (there are 8 frequency dividing switch units) and a decoder (three eight decoders) in an embodiment with a frequency dividing mode of 4/5, and fig. 4 is a schematic circuit connection diagram of a dual mode prescaler circuit with selectable modulus (there are 8 frequency dividing switch units) and a decoder (three eight decoders) in an embodiment with a frequency dividing mode of 16/17, the three eight decoders being provided with three input terminals A0, A1 and A2, the three input control terminals receiving a 3bit input control signal and then outputting an eight bit mode strobe signal, specifically including: the decoding output end Y0 of the three-eight decoder is used for outputting a Mode gating signal Mode_2/3 matched with a 2/3 frequency division Mode, the decoding output end Y1 of the three-eight decoder is used for outputting a Mode gating signal Mode_4/5 matched with a 4/5 frequency division Mode, the decoding output end Y2 of the three-eight decoder is used for outputting a Mode gating signal Mode_6/7 matched with a 6/7 frequency division Mode, the decoding output end Y3 of the three-eight decoder is used for outputting a Mode gating signal Mode_8/9 matched with a 8/9 frequency division Mode, the decoding output end Y4 of the three-eight decoder is used for outputting a Mode gating signal Mode_10/11 matched with a 10/11 frequency division Mode, the decoding output end Y5 of the three-eight decoder is used for outputting a Mode gating signal Mode_12/13 matched with a 12/13 frequency division Mode, the decoding output end Y6 of the three-eight decoder is used for outputting a Mode gating signal Mode_14/15 matched with a 14/15 frequency division Mode, the decoding output end Y7 of the three-eight decoder is used for outputting a Mode gating signal Mode_16/17 matched with a frequency division Mode, the three-eight decoder is used for outputting a Mode gating signal Mode_16/17, the three-eight decoder is used for outputting a three-eight decoder is not used for outputting a high level decoding signal corresponding to the three-level decoding signal 1, and the three-level decoding output signal 3 is used for outputting a three-level decoding gating signal 3, namely, and the three-eight decoder is used for outputting a high level decoding signal is not outputting a high level signal, and the three-level signal is used for outputting a high level signal, and the three-level decoding signal is used for outputting a high level signal, and the three-level signal is used for the decoding signal. The clock input ends of the 8D flip-flops used for frequency division are connected with the clock signal to be frequency-divided.
Referring to fig. 3 and 6, the selectable modulus dual-mode prescaler circuit includes 16/2D flip-flops for frequency division, one D flip-flop d_0 for latching, a first nand gate NA1 and a second nand gate NA2;16 is the maximum frequency dividing module, 4 is the currently selected frequency dividing module of the decoder, the data input end of the D trigger D_0 used for latching is connected with the output end of the first NAND gate NA1, the second input end of the first NAND gate NA1 is connected with the full count signal K output by the programmable pulse swallowing counter, the positive output end of the D trigger D_0 used for latching is connected with the second input end of the second NAND gate NA2, the clock input end of the D trigger D_0 used for latching is connected with the clock signal Fosc to be divided, and the D trigger D_0 is used for latching the current frequency dividing module before the frequency dividing module changes. When the decoder gates a frequency-dividing switching unit matching a 4/5 frequency-dividing Mode on the frequency-dividing analog-to-digital 4 decoding result of the input control signal, that is, when the Mode gating signal mode_4/5 is a high level "1", 2D flip-flops for frequency division are selected to be connected in series in sequence between the fourth switching terminal 14 of the frequency-dividing switching unit matching the 4/5 frequency-dividing Mode (for receiving the gating control effect of the Mode gating signal mode_4/5) and the first input terminal of the second nand gate NA2, the 2D flip-flops for frequency division are connected in series in sequence through the data input terminal, the positive output terminal and the frequency-dividing switching unit thereof, wherein the positive output terminal of the first D flip-flop d_1 is connected with the first input terminal of the second nand gate NA2, the inverting output terminal of the first D flip-flop d_1 is connected to the first input terminal of the first nand gate NA1, the data input terminal of the 2 nd D flip-flop d_2 is connected to the fourth switch switching terminal 14 of the frequency dividing switching unit matching the currently selected frequency dividing Mode of 4/5, the frequency dividing switching units connected between the 2D flip-flops for frequency division are turned on, so that the positive output terminals and the data input terminals of the adjacent two D flip-flops (such as the flip-flop d_1 and the flip-flop d_2 which are adjacently arranged) are communicated, and the third switch switching terminal 13 of the frequency dividing switching unit matching the currently selected frequency dividing Mode (frequency dividing Mode of 4/5) is connected to the output terminal of the second nand gate NA2, thereby allowing the modulus selectable dual mode prescaler circuit to operate in the currently selected frequency division mode (4/5 frequency division mode).
As shown in fig. 3, there are (16-4)/2D flip-flops connected in series in sequence between the second switch switching terminal 12 and the ground terminal of the frequency dividing switching unit matching the currently selected 4/5 frequency dividing Mode, the 6D flip-flops for frequency division are connected in series in sequence by their data input terminal, positive output terminal and the frequency dividing switching unit, but when the Mode gating signal mode_4/5 is at a high level "1", the 6D flip-flops (including D flip-flop d_3, D flip-flop d_4, D flip-flop d_5, D flip-flop d_6, D flip-flop d_7, D flip-flop d_8 of fig. 3) are in a deactivated state, The positive output end of the D trigger D_3 is connected with the second switch switching end 12 of the frequency division switching unit matched with the currently selected 4/5 frequency division mode, and the data input end of the D trigger D_8 is connected with the ground end; The (16-4)/2 frequency division switching units connected between the D triggers for frequency division are conducted, so that the positive output ends and the data input ends of the two adjacent D triggers are communicated, the first switch switching end of the frequency division switching unit matched with the currently selected 4/5 frequency division Mode is equivalently communicated with the first switch switching end of the frequency division switching unit for receiving the Mode gating signal mode_16/17, but the (16-4)/2D triggers for frequency division are in a stop working state, and power consumption is saved. Referring to fig. 4 and 6, the selectable modulus dual-mode prescaler circuit includes 16/2D flip-flops for frequency division, one D flip-flop d_0 for latching, a first nand gate NA1 and a second nand gate NA2; 16 is the maximum frequency dividing module, 16 is the currently selected frequency dividing module of the decoder, the data input end of the D trigger D_0 used for latching is connected with the output end of the first NAND gate NA1, the second input end of the first NAND gate NA1 is connected with the full count signal K output by the programmable pulse swallowing counter, the positive output end of the D trigger D_0 used for latching is connected with the second input end of the second NAND gate NA2, the clock input end of the D trigger D_0 used for latching is connected with the clock signal Fosc to be divided, and the D trigger D_0 is used for keeping the working state of the current frequency dividing mode stable before the frequency dividing module changes. When the decoder gates a frequency-dividing switching unit matching a 16/17 frequency-dividing Mode on the frequency-dividing modulus 16 decoding result of the input control signal, that is, when the Mode gating signal mode_16/17 is high level "1", 8D flip-flops for frequency division are selected to be connected in series in sequence between the fourth switching terminal 14 of the frequency-dividing switching unit matching the 16/17 frequency-dividing Mode (for receiving the gating control action of the Mode gating signal mode_16/17) and the first input terminal of the second nand gate NA2, the 8D flip-flops for frequency division are connected in series in sequence through the data input terminal, the positive output terminal and the frequency-dividing switching unit thereof, Wherein the positive output end of the first D trigger D_1 is connected with the first input end of the second NAND gate NA2, the inverse output end of the first D trigger D_1 is connected with the first input end of the first NAND gate NA1, the data input end of the 8 th D trigger D_8 is connected with the fourth switch end 14 of the frequency division switch unit matched with the currently selected 16/17 frequency division mode, the frequency division switch units connected between the 8D triggers for frequency division are conducted, so that the positive output ends and the data input ends of two adjacent D triggers (such as the adjacently arranged trigger D_2 and the trigger D_3) are communicated, the third switch end 13 arranged by the frequency division switch unit matched with the currently selected frequency division mode (16/17 frequency division mode) is connected with the output end of the second NAND gate NA2, Thereby letting all the D flip-flops enter the currently selected divide mode (divide by 16/17 mode) to operate.
According to the embodiment, the matched multiple frequency division switching units are controlled according to the decoding result, and then the number of the actual serial connection of the D trigger is controlled through different frequency division switching units, so that the most suitable dual-mode frequency divider can be decoded and combined according to different simulation design requirements, the optimal debugging effect is achieved, the same dual-mode frequency division structure is multiplexed into the dual-mode frequency divider structure in multiple frequency division modes with the matched decoding result, and meanwhile, the control signals of the programmable program counter and the programmable pulse swallowing counter are multiplexed.
The phase-locked loop disclosed in an embodiment of the present invention, as shown in fig. 6, includes a phase frequency detector PFD, a charge pump CP, a low pass filter LPF, a voltage controlled oscillator VCO, and an SDM modulator connected in sequence, and further includes the dual-mode frequency divider with selectable frequency dividing modulus, the voltage controlled oscillator provides a clock signal Fosc to be divided for the dual-mode frequency divider, the SDM modulator provides a preset target frequency dividing ratio of the clock signal to be divided for the dual-mode frequency divider, the dual-mode frequency divider performs frequency dividing processing on the clock signal to be divided according to a frequency dividing mode matched with the preset target frequency dividing ratio, and then outputs a feedback signal Fdiv to the phase frequency detector, and then converts the feedback signal Fdiv to a control voltage of the voltage controlled oscillator VCO through the charge pump and the low pass filter, and controls the voltage controlled oscillator VCO to provide the clock signal to be divided to form a loop of the phase-locked loop. Specifically, the dual-mode prescaler circuit in the dual-mode frequency divider with selectable frequency division modulus at least comprises frequency division change-over switch units with preset selectable dual-mode quantity, and the input control ends of the frequency division change-over switch units are used as modulus selection input ends of the dual-mode prescaler circuit and are respectively connected with decoding output ends matched with the decoder; each frequency division switching unit is connected between two adjacent matched D triggers, so that after the frequency division switching units are gated by frequency division analog-digital decoding results corresponding to input control signals, the dual-mode prescaler circuit enters a currently selected frequency division mode and equivalently forms a currently selected frequency division analog-digital/(currently selected frequency division analog-digital+1) dual-mode frequency divider, switching expansion of the frequency division modes is achieved according to the decoding results, the same traditional dual-mode frequency divider is multiplexed to form a dual-mode frequency divider in multiple frequency division modes, and self-adaptive adjustment of the frequency division modes is supported.
A chip comprising said phase locked loop. The method realizes the switching expansion of frequency division modes according to the decoding result, multiplexes the same traditional dual-mode frequency divider with the structure of multiple frequency division modes, multiplexes the dual-mode frequency divider with limited frequency division range and compromised performance into the pre-configured dual-mode frequency divider with multiple frequency division modes, and meets the frequency division requirement of products.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same; while the invention has been described in detail with reference to the preferred embodiments, those skilled in the art will appreciate that: modifications may be made to the specific embodiments of the present invention or equivalents may be substituted for part of the technical features thereof; without departing from the spirit of the invention, it is intended to cover the scope of the invention as claimed.
Claims (11)
1. The dual-mode prescaler circuit is characterized by comprising a maximum frequency division module/2D triggers which are sequentially connected in series, wherein the dual-mode prescaler circuit comprises frequency division switch units with preset selectable dual-mode numbers, and input control ends arranged by the frequency division switch units are used for receiving mode gating signals based on a currently selected frequency division mode; one switch switching end of each frequency division switching unit is connected with the data input end of the matched D trigger, so that after the mode gating signal gates the frequency division switching units, the dual-mode prescaler circuit is multiplexed into a currently selected frequency division modulus/(the currently selected frequency division modulus+1) dual-mode frequency divider;
each frequency division switching unit and the D trigger matched with the frequency division switching unit form a switch switching control unit, and when the number of the frequency division switching units is equal to the maximum frequency division modulus/2, a structure of sequentially connecting the maximum frequency division modulus/2 switch switching control units in series is formed;
The ratio of the maximum frequency division modulus to 2 is greater than or equal to the preset selectable double-modulus number, the maximum frequency division modulus is the maximum value of the frequency division modulus in the preset frequency division modes of the preset selectable double-modulus number, and the currently selected frequency division modulus is the corresponding frequency division modulus value in the currently selected frequency division mode.
2. The dual-mode prescaler circuit of claim 1, wherein a switching terminal of each of said frequency dividing and switching units is connected to the data input terminal of the matched D flip-flop in a configuration of:
The data input end of the currently selected frequency division modulus/2D triggers which are sequentially connected in series is connected with the fourth switch switching end of the frequency division switching unit corresponding to the currently selected frequency division mode, wherein the currently selected frequency division modulus is any frequency division modulus in the preset selectable double-mode number frequency division modes;
The second switch switching end of the frequency division switching unit corresponding to the currently selected frequency division mode is connected with the positive output end of the currently selected frequency division modulus/2+1D triggers which are sequentially connected in series, wherein the currently selected frequency division modulus is not the maximum frequency division modulus.
3. The dual mode prescaler circuit of claim 2, wherein only one mode strobe signal is valid in the input control terminals of the preset selectable dual mode number of frequency dividing switch units, such that the frequency dividing switch unit gated by the valid mode strobe signal disconnects the series connection relationship between the D flip-flop connected to the second switch terminal and the D flip-flop connected to the fourth switch terminal, but the other frequency dividing switch units connect the D flip-flop connected to the second switch terminal and the D flip-flop connected to the fourth switch terminal in series;
The second switch switching unit corresponding to the maximum frequency division modulus is arranged at the ground.
4. A dual mode prescaler circuit according to claim 3, further comprising a D flip-flop for latching, a first nand gate (NA 1) and a second nand gate (NA 2);
The data input end of the D trigger for latching is connected with the output end of the first NAND gate (NA 1), the second input end of the first NAND gate (NA 1) is used for being connected with a frequency division mode switching control signal generated by the counting of an external counter, the positive output end of the D trigger for latching is connected with the second input end of the second NAND gate (NA 2), and the clock input end of the D trigger for latching is connected with a clock signal to be divided;
In the maximum frequency division modulus/2D flip-flops which are connected in series in turn and used for frequency division, the positive output end of the first D flip-flop is connected with the first input end of the second NAND gate (NA 2), the negative output end of the first D flip-flop is connected with the first input end of the first NAND gate (NA 1), and the data input end of the maximum frequency division modulus/2D flip-flops is connected with the fourth switch switching end of the frequency division switching unit corresponding to the maximum frequency division modulus;
wherein the clock input of the maximum frequency dividing modulus/2D flip-flops for frequency dividing is connected with the clock signal to be frequency divided.
5. The dual-mode prescaler circuit of claim 4, wherein the frequency dividing switching unit further comprises a first switching terminal (11), a third switching terminal (13), a first inverter (INV 1), a second inverter (INV 2), a third inverter (INV 3), a first transmission gate (T1), a second transmission gate (T2), and a third transmission gate (T3);
The input control end is connected with the input end of a second inverter (INV 2), the output end of the second inverter (INV 2) is connected with the reverse phase control end of a second transmission gate (T2), the output end of the second transmission gate (T2) is connected with a fourth switch switching end (14), the normal phase control end of the second transmission gate (T2) is connected with the input control end, and a third switch switching end (13) is connected with the input end of the second transmission gate (T2);
The input control end is connected with the input end of the first inverter (INV 1), the first switch switching end (11) is connected with the inversion control end of the first transmission gate (T1), the first switch switching end (11) is connected with the output end of the first transmission gate (T1), the input end of the first transmission gate (T1) is connected with the third switch switching end (13), the first switch switching end (11) is connected with the input end of the first inverter (INV 1), and the output end of the first inverter (INV 1) is connected with the normal phase control end of the first transmission gate (T1);
The input control end is connected with the input end of a third inverter (INV 3), the output end of the third inverter (INV 3) is connected with the normal phase control end of a third transmission gate (T3), the switching control end is connected with the reverse phase control end of the third transmission gate (T3), the second switch switching end (12) is connected with the input end of the third transmission gate (T3), and the output end of the third transmission gate (T3) is connected with a fourth switch switching end (14).
6. The dual-mode prescaler circuit of claim 4, wherein the frequency dividing switching unit further comprises a first switching terminal (11), a third switching terminal (13), a second inverter (INV 2), a third inverter (INV 3), a second transmission gate (T2), and a third transmission gate (T3);
The input control end is connected with the input end of a second inverter (INV 2), the output end of the second inverter (INV 2) is connected with the reverse phase control end of a second transmission gate (T2), the output end of the second transmission gate (T2) is connected with a fourth switch switching end (14), the normal phase control end of the second transmission gate (T2) is connected with the input control end, and a third switch switching end (13) is connected with the input end of the second transmission gate (T2);
The first switch switching end (11) is connected with the third switch switching end (13);
The input control end is connected with the input end of a third inverter (INV 3), the output end of the third inverter (INV 3) is connected with the normal phase control end of a third transmission gate (T3), the switching control end is connected with the reverse phase control end of the third transmission gate (T3), the second switch switching end (12) is connected with the input end of the third transmission gate (T3), and the output end of the third transmission gate (T3) is connected with a fourth switch switching end (14).
7. A dual-mode frequency divider comprising a programmable program counter and a programmable pulse swallow counter; wherein the divided modulus selectable dual modulus divider further comprises a decoder and the dual modulus prescaler circuit of any of claims 1 to 6;
the input end of the decoder is used for inputting a control signal, the modulus selection input end of the dual-mode prescaler circuit is correspondingly connected with the decoding output end of the decoder, and the dual-mode prescaler circuit is used for gating the input control signal into the currently selected frequency division mode through the modulus selection input end on the premise that the counting bit number of the programmable program counter and the counting bit number of the programmable pulse swallowing counter are unchanged; the input control end of the frequency division switching unit in the dual-mode prescaler circuit is used as the analog-digital selection input end of the dual-mode prescaler circuit.
8. The dual-mode frequency divider according to claim 7, wherein when the decoder is provided with decoding output ends of a preset selectable dual-mode number, the dual-mode pre-frequency dividing circuit is provided with frequency dividing switch units of the preset selectable dual-mode number, and input control ends of the frequency dividing switch units are respectively connected with the decoding output ends of the preset selectable dual-mode number in the decoder in a one-to-one correspondence manner, so that the input control ends of the frequency dividing switch units respectively correspond to different frequency dividing modes of the preset selectable dual-mode number.
9. The dual-mode frequency divider according to claim 8, wherein the dual-mode frequency divider is configured to, when a frequency-dividing switch unit matching a currently selected frequency-dividing mode is selected according to a decoding result of the decoder on the frequency-dividing modulus of the input control signal, disconnect a series connection relationship between the D flip-flop connected to the second switch terminal and the D flip-flop connected to the fourth switch terminal, the frequency-dividing switch unit matching the currently selected frequency-dividing mode is connected to the third switch terminal and the fourth switch terminal, and simultaneously control other frequency-dividing switch units according to a decoding result of the decoder on the frequency-dividing modulus of the input control signal to connect the D flip-flop connected to the second switch terminal and the D flip-flop connected to the fourth switch terminal in series, so that a currently selected frequency-dividing modulus/2D flip-flops are sequentially connected in series on a side of the fourth switch terminal matching the currently selected frequency-dividing mode to multiplex the currently selected frequency-dividing modulus/(currently selected frequency-dividing modulus+1) dual-mode frequency divider.
10. The phase-locked loop comprises a phase frequency detector, a charge pump, an SDM modulator, a filter and a voltage-controlled oscillator which are sequentially connected, and is characterized by further comprising the dual-mode frequency divider as claimed in any one of claims 7 to 9, wherein the voltage-controlled oscillator provides a clock signal to be divided for the dual-mode frequency divider, the SDM modulator provides a preset target frequency division ratio of the clock signal to be divided for the dual-mode frequency divider, the dual-mode frequency divider carries out frequency division processing on the clock signal to be divided according to a frequency division mode matched with the preset target frequency division ratio, and then outputs a feedback signal to the phase frequency detector.
11. A chip comprising the phase locked loop of claim 10.
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