WO2014169681A1 - Multimode programmable frequency divider - Google Patents

Multimode programmable frequency divider Download PDF

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Publication number
WO2014169681A1
WO2014169681A1 PCT/CN2013/090479 CN2013090479W WO2014169681A1 WO 2014169681 A1 WO2014169681 A1 WO 2014169681A1 CN 2013090479 W CN2013090479 W CN 2013090479W WO 2014169681 A1 WO2014169681 A1 WO 2014169681A1
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Prior art keywords
terminal
frequency
frequency dividing
frequency division
power
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PCT/CN2013/090479
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French (fr)
Chinese (zh)
Inventor
易律凡
彭关超
刘永才
谢豪律
周栋梁
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中兴通讯股份有限公司
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Publication of WO2014169681A1 publication Critical patent/WO2014169681A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17784—Structural details for adapting physical parameters for supply voltage

Definitions

  • the present invention relates to the field of frequency divider design, and more particularly to a multimode programmable frequency divider. Background technique
  • the frequency synthesizer provides the carrier signal for the transceiver
  • the programmable frequency divider is the core device in the frequency synthesizer. It directly controls the channel selection and is the key to the overall tunable chip design. Therefore, high operating frequencies, wide division ratio ranges, low power consumption, etc. are usually the general requirements of the system for the divider.
  • the multimode programmable frequency divider is a programmable frequency divider designed based on the cascade of 2/3 frequency division units.
  • the range of the frequency division ratio is easy to expand, and the module circuits in this structure are basically the same. Strong use.
  • a wide-range multi-mode programmable frequency divider in the prior art is shown in FIG. 1, and the total number n of the 2/3 frequency dividing unit is determined according to the maximum value of the required frequency dividing ratio, and then according to the minimum frequency dividing ratio.
  • the value determines that there is no need to add the number of 2/3 frequency division units Ne, and each 2/3 frequency division unit is connected in series, wherein the front Ne level is a standard 2/3 frequency division cascade, and the subsequent levels are bands
  • the 2/3 division of the extension bits is cascaded. This circuit can effectively extend the division ratio of the multimode programmable divider.
  • the structure of the conventional 2/3 frequency dividing unit is as shown in FIG. 2, and the conventional 2/3 frequency dividing unit has a trigger signal input terminal f in , a mode control signal input terminal modi, a set terminal P, and a trigger signal. Output f. And a mode control signal output terminal mod. ; Trigger signal output terminal f.
  • the trigger signal input terminal f in is connected to the second-stage 2/3 frequency dividing unit of the second stage, and the digitizing terminal P is configured to receive the divisor signal to select the frequency dividing unit to perform the divide by 2 or divide the 3 working mode, the first level 2/3
  • the trigger signal input terminal of the frequency dividing unit is connected to the source pulse.
  • the 2/3 divider with extension bits is a traditional 2/3 division
  • the element is improved, and its structure is shown in Figure 3.
  • the 2/3 of the part is disabled by the multi-mode programmable frequency divider that achieves the highest division ratio.
  • the frequency unit implements a downward expansion of the frequency division range.
  • the traditional multi-mode programmable frequency divider is a circuit with a current mode logic (CML) structure, which consumes a lot of power and is complicated.
  • a multimode programmable frequency divider based on a True Single Phase Clock (TSPC) architecture circuit can effectively reduce the power consumption of the circuit compared to a multimode programmable frequency divider using a CML architecture circuit.
  • TSPC True Single Phase Clock
  • the existing multimode programmable frequency dividers are in a different frequency division ratio, and each 2/3 frequency division unit is in the working mode, which will inevitably result in waste of power consumption of the multimode programmable frequency divider. Summary of the invention
  • embodiments of the present invention provide a multi-mode programmable frequency divider.
  • the embodiment of the invention provides a multi-mode programmable frequency divider, comprising: a main frequency dividing stage composed of cascaded 2/3 frequency dividing units, wherein the cascaded 2/3 frequency dividing unit does not have a frequency dividing unit
  • the number of 2/3 division units of the extension bit is Ne
  • the number of 2/3 division units with the division ratio extension bit is n-Ne
  • Ne is the effective number of bits of the multimode programmable frequency divider
  • the multimode programmable frequency divider further includes: a real-time power consumption control circuit and a power switch control transistor.
  • the real-time power consumption control circuit is composed of two-input AND gates of n-Ne-1 level, and the reverse signal Pinv[n] of the frequency division ratio control bit P[n] of the n-th stage 2/3 frequency division unit is connected to the nth
  • the aspect is connected to the Power_Ctrl terminal of the n-1th 2/3 frequency dividing unit, and on the other hand, the inverse of the frequency dividing ratio control bit P[n-2] of the n-2th 2/3 frequency dividing unit.
  • the signal Pinv[n-2] is connected to the n-1th level and the gate Two inputs; and so on, until the n-Ne stage 2/3 frequency dividing unit and the n-Ne-1 level AND gate; the power switch control transistor has a drain connected to the corresponding band division ratio extension bit
  • the power supply terminal of the 2/3 frequency dividing unit, the source is connected to the power supply, and the gate is connected to the Power_Ctrl terminal of the 2/3 frequency dividing unit with the frequency dividing ratio extension bit.
  • the total number n of the cascaded 2/3 frequency division units is determined according to a required maximum frequency division ratio, the maximum frequency division ratio is 2 n+1 ⁇ l , and the minimum of the multimode programmable frequency divider is The division ratio is determined according to the effective number of bits Ne of the multimode programmable frequency divider, and the minimum division ratio is 2 Ne+1 .
  • the 2/3 frequency division unit with the frequency division ratio extension bit, the reverse signal output P2inv of the extension bit is a real-time control signal
  • power_Ctrl is the controlled end
  • the three triggers DFF1, DFF2, DFF3 are Trigger with dual input D1, D2, DFF4 is a single input trigger, the clock of all the triggers is derived from the trigger signal input terminal fin;
  • the QB terminal of DFF4 contacts the signal output terminal fo;
  • the D2 terminal of DFF3 is connected to the mode control signal input Terminal modi, Dl terminates the Q end of DFF4;
  • DFF2 D2 terminal is connected to the terminal PI, D1 is terminated to the Q terminal of DFF3;
  • DFF1 D2 is connected to the QB end of DFF2, D1 is terminated to the QB end of DFF4, that is, fo;
  • the D terminal of DFF4 is connected to the Q terminal of DFF1;
  • the terminal P2 is connected to the input terminal of inverter I
  • the output terminal of AND1 is connected to the mode control signal output terminal modo; PI and P2 are also connected to the input terminal of AND gate AND2, and the output terminal of AND2 is connected to P0 12 ; the source terminal Vt of all DFF is connected to the power switch control transistor. Drain, the gate of the power switch control transistor is connected to power-Ctrl, the power switch controls the transistor To the power source.
  • the 2/3 frequency division unit with the frequency division ratio extension bit adopts a true single phase clock D flip-flop TSPC DFF.
  • the 2/3 frequency division unit with the frequency division ratio extension bit adopts a TSPC DFF with a built-in AND gate.
  • the power switch control transistor is a P-channel field effect transistor PMOS.
  • a multi-mode programmable frequency divider provided by an embodiment of the present invention can control a multi-mode frequency divider in different frequency divisions by adding a real-time power consumption control circuit and a power switch control transistor. Compared with the working condition of the 2/3 frequency dividing unit, the power consumption of the multi-mode programmable frequency divider is effectively avoided.
  • FIG. 1 is a schematic structural view of a wide-range multi-mode programmable frequency divider in the prior art
  • FIG. 2 is a schematic structural view of a conventional 2/3 frequency dividing unit in the prior art
  • FIG. 3 is a schematic structural diagram of a 2/3 frequency division unit with an extension bit in the prior art
  • FIG. 4 is a schematic structural diagram of a multimode programmable frequency divider according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of a 2/3 frequency division unit according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of a circuit of a TSPC DFF according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a circuit structure of a TSPC DFF with a built-in AND gate according to an embodiment of the present invention. detailed description
  • a multi-mode programmable frequency divider provided by an embodiment of the present invention includes: a primary frequency division level composed of cascaded 2/3 frequency division units, and 2/3 points of the cascade
  • the number of 2/3 frequency division units without frequency division extension bits in the frequency unit is Ne
  • the number of 2/3 frequency division units with frequency division ratio extension bits is n-Ne
  • Ne is the multimode programmable
  • the effective number of bits of the frequency divider; the total number n of the cascaded 2/3 frequency dividing units is determined according to a required maximum frequency dividing ratio, and the maximum frequency dividing ratio is 2 n+1 -l
  • the multimode can be
  • the minimum division ratio of the programming frequency divider is determined according to the effective number of bits Ne of the multimode programmable frequency divider, and the minimum division ratio is 2 Ne+1 ; in the structure diagram shown in FIG. 4, the front Ne
  • the level is a standard 2/3 frequency division unit (
  • the multi-mode programmable frequency divider further includes: a real-time power consumption control circuit and a power switch control transistor, wherein
  • the real-time power consumption control circuit is composed of two-input and gates of n-Ne-1 level, and the inverse signal Pinv[n] of the frequency division ratio control bit P[n] of the n-th stage 2/3 frequency division unit is connected to the nth stage 2 /3 frequency division unit power control Positioning power— Ctrl; the ratio of the inverse signal Pinv[n] of the division ratio control bit P[n] of the nth stage 2/3 division unit and the division ratio of the n-1th stage 2/3 division unit
  • the inverted signal Pinv[n-1] of the control bit P[n-1] is connected to the two input terminals of the nth AND gate, and the output of the nth AND gate is connected to the n-1th level 2 on the one hand.
  • the Power_ Ctrl terminal of the /3 frequency division unit is connected to the reverse signal Pinv[n-2] of the division ratio control bit P[n-2] of the n-2th 2/3 division unit.
  • the power_ Ctrl terminal of the /3 frequency division unit is connected to the reverse signal Pinv[n-2] of the division ratio control bit P[n-2] of the n-2th 2/3 division unit.
  • ⁇ denotes the trigger signal input
  • f Indicates the trigger signal output
  • modi represents the mode control signal input
  • mod. Indicates the mode control signal output
  • power—Ctrl indicates the power control bit.
  • the drain of the power switch control transistor is connected to the power supply terminal of the 2/3 frequency dividing unit with the frequency division ratio extension bit, and the source is connected to the power supply.
  • the power switch control transistor may be a P-channel field effect transistor (PMOS transistor).
  • the multi-mode programmable frequency divider has a 2/3 frequency division unit with a frequency division ratio extension bit, and the structure thereof is as shown in FIG. 5, and the frequency division ratio extension bit of the embodiment of the present invention is 2
  • the /3 frequency division unit is implemented based on the improvement of the 2/3 frequency division unit with the frequency division ratio extension bit in the prior art; the 2/3 frequency division unit with the frequency division ratio extension bit in the embodiment of the present invention,
  • the reverse signal output P2inv of the extension bit P[n] is the real-time control signal
  • power_Ctrl is the controlled terminal
  • three flip-flops DFF1, DFF2, DFF3 are triggers with dual inputs D1, D2, and DFF4 is single-input trigger
  • the trigger of all the triggers is derived from the trigger signal input terminal fin; the QB terminal of DFF4 is connected to the output fo (ie, the trigger signal output terminal); the D2 terminal of the DFF3 is connected to the mode control signal input terminal modi, and the D1 terminal is
  • the output of AND1 is connected to the mode control signal output terminal modo; PI and P2 are also connected to the input terminal of AND2 (AND gate), and the output terminal of AND2 is connected to P0 12 ;
  • the source Vt of all DFFs is connected
  • the power switch controls the drain of the transistor (such as PMOS transistor PM1), the gate of the power switch control transistor (such as PM1) is connected to ower ctrl, and the source of the power switch control transistor (such as PM1) is connected to the power supply.
  • the drain of the power switch control transistor PM1 is connected to the source terminal Vt of the 2/3 frequency dividing unit, and the source is connected to the power supply. Then, the power switch control transistor controls the corresponding 2/3 frequency dividing unit according to the signal received by the power Ctrl.
  • the power supply is connected or disconnected for real-time control of the power consumption of the multimode programmable divider.
  • the 2/3 frequency division unit with the frequency division ratio extension bit in the embodiment of the present invention can adopt the circuit structure of the TSPC DFF as shown in FIG. 6, which adopts a technique for optimizing the glitch and charge sharing effect, thereby Can improve the working speed of multi-mode programmable frequency divider;
  • the 2/3 frequency division unit with the frequency division ratio extension bit in the embodiment of the present invention can also adopt the circuit structure of the TSPC DFF with built-in AND gate shown in FIG. 7, and usually, the AND gate and the D flip-flop It is two different parts, and the structure shown in Figure 7 is an improvement on the structure shown in Figure 6. It will be combined with the gate and the D flip-flop, that is, only the PMOS tube PM1 and the NMOS tube NM1 connected to the D2 terminal are added. The function of the AND gate and Figure 6 is realized, thereby shortening the length of the critical path, reducing the number of transistors, increasing the operating frequency, and reducing power consumption.
  • the multi-mode programmable frequency divider of the embodiment of the present invention can control the multi-mode frequency divider in different frequency division ratios by 2/3 in real time by adding a real-time power consumption control circuit and a power switch control transistor.
  • the working condition of the frequency dividing unit effectively avoids waste of power consumption of the multimode programmable frequency divider; in addition, the circuit structure of the embodiment of the invention is simple, and only a series of AND gates are added on the basis of the original multimode programmable frequency divider.
  • the PMOS transistor, and the added gate operates at the output signal frequency, without adding additional power.

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  • Mathematical Physics (AREA)
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  • Computer Hardware Design (AREA)
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Abstract

Disclosed is a multimode programmable frequency divider, comprising: cascaded 2/3 frequency dividing units, a real-time power consumption control circuit, and a power switch control transistor, wherein the number of the frequency dividing units without a frequency dividing ratio extension bit and the number of the frequency dividing units with the extension digit are Ne and n-Ne, respectively; the real-time power consumption control circuit is composed of n-Ne-1 levels of two-input AND gates; the reverse signal of the frequency dividing ratio control bit of the n-th level of the frequency dividing unit is connected to the power control bit of the n-th level of the frequency dividing unit; the reverse signal, and the reverse signal of the frequency dividing ratio control bit of the (n-1)-th level of the frequency dividing unit are connected to the input end of the n-th level of the AND gate; the output end of the n-th level of the AND gate is connected to the power control bit of the (n-1)-th level of the frequency dividing unit, and the reverse signal of the frequency dividing ratio control bit of the (n-2)-th level of the frequency dividing unit is correspondingly connected to the input end of the (n-1)-th level of the AND gate; the subsequent connections are completed in a similar way until the reverse signal of the frequency dividing ratio control bit of the (n-Ne)-th level of the frequency dividing unit is connected to the input end of the (n-Ne-1)-th level of the AND gate; the drain of the power switch control transistor is connected to the power ends of the frequency dividing units with the extension bit, the source of the power switch control transistor is connected to a power supply, and the grid of the power switch control transistor is connected to the power control bits of the frequency dividing units with the extension bit.

Description

一种多模可编程分频器 技术领域  Multi-mode programmable frequency divider
本发明涉及分频器设计领域， 尤其涉及一种多模可编程分频器。 背景技术  The present invention relates to the field of frequency divider design, and more particularly to a multimode programmable frequency divider. Background technique
为提高系统的频谱利用率， 移动通信系统大都采用频分复用技术， 收 发机进行通信时的信道将会根据信道占用情况、 信道质量等进行实时切换。 频率合成器为收发机提供载波信号， 而可编程分频器则是频率合成器中的 核心器件， 它直接控制着信道的选择， 是整个可调谐芯片设计的关键。 因 此， 高的工作频率、 宽的分频比范围、 低功耗等通常是系统对分频器的一 般要求。  In order to improve the spectrum utilization of the system, mobile communication systems mostly adopt frequency division multiplexing technology, and the channel when the transceiver performs communication will be switched in real time according to channel occupancy and channel quality. The frequency synthesizer provides the carrier signal for the transceiver, and the programmable frequency divider is the core device in the frequency synthesizer. It directly controls the channel selection and is the key to the overall tunable chip design. Therefore, high operating frequencies, wide division ratio ranges, low power consumption, etc. are usually the general requirements of the system for the divider.
多模可编程分频器是一种基于 2/3 分频单元级联来设计的可编程分频 器， 其分频比的范围容易扩展， 并且这种结构中的模块电路基本一致， 可 复用性强。 现有技术中一种宽范围的多模可编程分频器如图 1 所示， 根据 所需分频比的最大值确定 2/3分频单元的总个数 n, 再根据最小分频比的值 确定无需加置数端的 2/3分频单元的数量 Ne,各 2/3分频单元串接，其中， 前 Ne级为标准的 2/3分频级联， 后面的各级为带扩展位的 2/3分频级联。 这种电路可以有效地扩展多模可编程分频器的分频比。  The multimode programmable frequency divider is a programmable frequency divider designed based on the cascade of 2/3 frequency division units. The range of the frequency division ratio is easy to expand, and the module circuits in this structure are basically the same. Strong use. A wide-range multi-mode programmable frequency divider in the prior art is shown in FIG. 1, and the total number n of the 2/3 frequency dividing unit is determined according to the maximum value of the required frequency dividing ratio, and then according to the minimum frequency dividing ratio. The value determines that there is no need to add the number of 2/3 frequency division units Ne, and each 2/3 frequency division unit is connected in series, wherein the front Ne level is a standard 2/3 frequency division cascade, and the subsequent levels are bands The 2/3 division of the extension bits is cascaded. This circuit can effectively extend the division ratio of the multimode programmable divider.
其中， 传统 2/3分频单元的结构如图 2所示， 传统 2/3分频单元具有一 触发信号输入端 fin、 一模式控制信号输入端 modi、 一置数端 P、 一触发信 号输出端 f。、 以及一模式控制信号输出端 mod。； 触发信号输出端 f。连接于 后一级 2/3分频单元的触发信号输入端 fin, 置数端 P用以接收除数信号， 以选择该分频单元进行除 2或除 3工作模式，第一级 2/3分频单元的触发信 号输入端 ^连接来源脉沖。带扩展位的 2/3分频单元是由传统的 2/3分频单 元改进而来， 其结构如图 3 所示， 通过增加两个或门和一个反向器， 在实 现最高分频比的多模可编程分频器的基础上通过禁用部分的 2/3 分频单元 实现分频范围的向下扩展。 The structure of the conventional 2/3 frequency dividing unit is as shown in FIG. 2, and the conventional 2/3 frequency dividing unit has a trigger signal input terminal f in , a mode control signal input terminal modi, a set terminal P, and a trigger signal. Output f. And a mode control signal output terminal mod. ; Trigger signal output terminal f. The trigger signal input terminal f in is connected to the second-stage 2/3 frequency dividing unit of the second stage, and the digitizing terminal P is configured to receive the divisor signal to select the frequency dividing unit to perform the divide by 2 or divide the 3 working mode, the first level 2/3 The trigger signal input terminal of the frequency dividing unit is connected to the source pulse. The 2/3 divider with extension bits is a traditional 2/3 division The element is improved, and its structure is shown in Figure 3. By adding two OR gates and an inverter, the 2/3 of the part is disabled by the multi-mode programmable frequency divider that achieves the highest division ratio. The frequency unit implements a downward expansion of the frequency division range.
传统的多模可编程分频器是采用电流型逻辑（ CML, Current Mode Logic ) 结构的电路， 其功耗非常大， 且电路较复杂。基于真单相时钟（TSPC, True Single Phase Clock )结构电路的多模可编程分频器， 相比采用 CML结构电 路的多模可编程分频器， 可以有效地降低电路的功耗。 但是现有的多模可 编程分频器在不同分频比下， 由于每个 2/3分频单元都处于工作模式下， 势 必造成多模可编程分频器功耗的浪费。 发明内容  The traditional multi-mode programmable frequency divider is a circuit with a current mode logic (CML) structure, which consumes a lot of power and is complicated. A multimode programmable frequency divider based on a True Single Phase Clock (TSPC) architecture circuit can effectively reduce the power consumption of the circuit compared to a multimode programmable frequency divider using a CML architecture circuit. However, the existing multimode programmable frequency dividers are in a different frequency division ratio, and each 2/3 frequency division unit is in the working mode, which will inevitably result in waste of power consumption of the multimode programmable frequency divider. Summary of the invention
为解决现有存在的技术问题， 本发明实施例提供一种多模可编程分频 器。  To solve the existing technical problems, embodiments of the present invention provide a multi-mode programmable frequency divider.
本发明实施例提供一种多模可编程分频器， 包括： 由级联的 2/3分频单 元构成的主分频级， 所述级联的 2/3分频单元中不带分频比扩展位的 2/3分 频单元的数量为 Ne, 带分频比扩展位的 2/3 分频单元的数量为 n-Ne, Ne 为所述多模可编程分频器的有效位数，  The embodiment of the invention provides a multi-mode programmable frequency divider, comprising: a main frequency dividing stage composed of cascaded 2/3 frequency dividing units, wherein the cascaded 2/3 frequency dividing unit does not have a frequency dividing unit The number of 2/3 division units of the extension bit is Ne, and the number of 2/3 division units with the division ratio extension bit is n-Ne, Ne is the effective number of bits of the multimode programmable frequency divider ,
所述多模可编程分频器还包括： 实时功耗控制电路和电源开关控制晶 体管，  The multimode programmable frequency divider further includes: a real-time power consumption control circuit and a power switch control transistor.
所述实时功耗控制电路由 n-Ne-1级两输入与门组成， 第 n级 2/3分频 单元的分频比控制位 P[n]的反向信号 Pinv[n]连接第 n级 2/3分频单元的电 源控制位 power— Ctrl; 第 n级 2/3分频单元的分频比控制位 P[n]的反向信号 Pinv[n]、 以及第 n-1 级 2/3 分频单元的分频比控制位 P[n-1]的反向信号 Pinv[n- 1 ] ,对应连接到第 n级与门的两输入端，第 n级与门的输出端一方面 连接到第 n-1级 2/3分频单元的 Power— Ctrl端， 另一方面与第 n-2级 2/3分 频单元的分频比控制位 P[n-2]的反向信号 Pinv[n-2]对应连接到第 n-1级与门 的两输入端； 依此类推， 直至第 n-Ne级 2/3分频单元和第 n-Ne-1级与门； 所述电源开关控制晶体管的漏极连接相应带分频比扩展位的 2/3 分频 单元的电源端， 源极连接供电电源， 栅极连接相应带分频比扩展位的 2/3 分频单元的 Power— Ctrl端。 The real-time power consumption control circuit is composed of two-input AND gates of n-Ne-1 level, and the reverse signal Pinv[n] of the frequency division ratio control bit P[n] of the n-th stage 2/3 frequency division unit is connected to the nth The power control bit of the level 2/3 frequency division unit power_Ctrl; the frequency division ratio of the nth stage 2/3 frequency division unit P[n], the reverse signal Pinv[n], and the n-1th level 2 /3 The division ratio of the frequency division ratio control bit P[n-1], Pinv[n-1], corresponding to the two input terminals of the nth AND gate, the output of the nth AND gate The aspect is connected to the Power_Ctrl terminal of the n-1th 2/3 frequency dividing unit, and on the other hand, the inverse of the frequency dividing ratio control bit P[n-2] of the n-2th 2/3 frequency dividing unit. The signal Pinv[n-2] is connected to the n-1th level and the gate Two inputs; and so on, until the n-Ne stage 2/3 frequency dividing unit and the n-Ne-1 level AND gate; the power switch control transistor has a drain connected to the corresponding band division ratio extension bit The power supply terminal of the 2/3 frequency dividing unit, the source is connected to the power supply, and the gate is connected to the Power_Ctrl terminal of the 2/3 frequency dividing unit with the frequency dividing ratio extension bit.
其中， 所述级联的 2/3分频单元的总数 n根据所需最大分频比确定， 所 述最大分频比为 2n+1-l , 所述多模可编程分频器的最小分频比根据所述多模 可编程分频器的有效位数 Ne确定， 所述最小分频比为 2Ne+1。 The total number n of the cascaded 2/3 frequency division units is determined according to a required maximum frequency division ratio, the maximum frequency division ratio is 2 n+1 −l , and the minimum of the multimode programmable frequency divider is The division ratio is determined according to the effective number of bits Ne of the multimode programmable frequency divider, and the minimum division ratio is 2 Ne+1 .
其中， 所述带分频比扩展位的 2/3分频单元， 其扩展位的反向信号输出 P2inv为实时控制信号， power— Ctrl为被控端， 3个触发器 DFF1、 DFF2、 DFF3是含双输入 Dl、 D2的触发器， DFF4是单输入触发器， 所有触发器 的时钟来源于触发信号输入端 fin; DFF4的 QB端接触发信号输出端 fo; DFF3的 D2端接模式控制信号输入端 modi, Dl端接 DFF4的 Q端； DFF2 的 D2端接置数端 PI , D1端接 DFF3的 Q端； DFF1的 D2端接 DFF2的 QB端， D1端接 DFF4的 QB端、 即 fo; DFF4的 D端接 DFF1的 Q端； 置 数端 P2接反向器 INV1的输入端， INV1的输出端接 P2inv和与门 AND1 的输入端， DFF3的输出 Q端同时接到 AND1的另一个输入端， AND1的输 出端接到模式控制信号输出端 modo; PI和 P2也接到与门 AND2的输入端， AND2的输出端接到 P012; 所有 DFF的源端 Vt接到电源开关控制晶体管 的漏极， 电源开关控制晶体管的栅极接到 power— Ctrl, 电源开关控制晶体管 的源端接到电源。 Wherein, the 2/3 frequency division unit with the frequency division ratio extension bit, the reverse signal output P2inv of the extension bit is a real-time control signal, power_Ctrl is the controlled end, and the three triggers DFF1, DFF2, DFF3 are Trigger with dual input D1, D2, DFF4 is a single input trigger, the clock of all the triggers is derived from the trigger signal input terminal fin; the QB terminal of DFF4 contacts the signal output terminal fo; the D2 terminal of DFF3 is connected to the mode control signal input Terminal modi, Dl terminates the Q end of DFF4; DFF2 D2 terminal is connected to the terminal PI, D1 is terminated to the Q terminal of DFF3; DFF1 D2 is connected to the QB end of DFF2, D1 is terminated to the QB end of DFF4, that is, fo; The D terminal of DFF4 is connected to the Q terminal of DFF1; the terminal P2 is connected to the input terminal of inverter INV1, the output terminal of INV1 is connected to the input terminal of P2inv and AND gate AND1, and the output Q terminal of DFF3 is connected to another input of AND1. The output terminal of AND1 is connected to the mode control signal output terminal modo; PI and P2 are also connected to the input terminal of AND gate AND2, and the output terminal of AND2 is connected to P0 12 ; the source terminal Vt of all DFF is connected to the power switch control transistor. Drain, the gate of the power switch control transistor is connected to power-Ctrl, the power switch controls the transistor To the power source.
其中， 所述带分频比扩展位的 2/3分频单元采用真单相时钟 D触发器 TSPC DFF。  Wherein, the 2/3 frequency division unit with the frequency division ratio extension bit adopts a true single phase clock D flip-flop TSPC DFF.
其中，所述带分频比扩展位的 2/3分频单元采用内置与门的 TSPC DFF。 其中， 所述电源开关控制晶体管为 P沟道场效应晶体管 PMOS。  Wherein, the 2/3 frequency division unit with the frequency division ratio extension bit adopts a TSPC DFF with a built-in AND gate. The power switch control transistor is a P-channel field effect transistor PMOS.
本发明实施例所提供的一种多模可编程分频器， 通过增设的实时功耗 控制电路和电源开关控制晶体管， 能够实时地控制多模分频器在不同分频 比下 2/3分频单元的工作状况， 有效地避免多模可编程分频器功耗的浪费。 附图说明 A multi-mode programmable frequency divider provided by an embodiment of the present invention can control a multi-mode frequency divider in different frequency divisions by adding a real-time power consumption control circuit and a power switch control transistor. Compared with the working condition of the 2/3 frequency dividing unit, the power consumption of the multi-mode programmable frequency divider is effectively avoided. DRAWINGS
图 1为现有技术中一种宽范围的多模可编程分频器的结构示意图； 图 2为现有技术中传统 2/3分频单元的结构示意图；  1 is a schematic structural view of a wide-range multi-mode programmable frequency divider in the prior art; FIG. 2 is a schematic structural view of a conventional 2/3 frequency dividing unit in the prior art;
图 3为现有技术中带扩展位的 2/3分频单元的结构示意图；  3 is a schematic structural diagram of a 2/3 frequency division unit with an extension bit in the prior art;
图 4为本发明实施例的一种多模可编程分频器的结构示意图； 图 5为本发明实施例的一种 2/3分频单元的结构示意图；  4 is a schematic structural diagram of a multimode programmable frequency divider according to an embodiment of the present invention; FIG. 5 is a schematic structural diagram of a 2/3 frequency division unit according to an embodiment of the present invention;
图 6为本发明实施例的一种 TSPC DFF的电路结构示意图；  6 is a schematic structural diagram of a circuit of a TSPC DFF according to an embodiment of the present invention;
图 Ί为本发明实施例的一种内置与门的 TSPC DFF的电路结构示意图。 具体实施方式  FIG. 3 is a schematic diagram of a circuit structure of a TSPC DFF with a built-in AND gate according to an embodiment of the present invention. detailed description
下面结合附图和具体实施例对本发明的技术方案进一步详细阐述。 本发明实施例提供的一种多模可编程分频器， 如图 4所示， 包括： 由 级联的 2/3分频单元构成的主分频级， 所述级联的 2/3分频单元中不带分频 比扩展位的 2/3分频单元的数量为 Ne, 带分频比扩展位的 2/3分频单元的 数量为 n-Ne, Ne为所述多模可编程分频器的有效位数； 所述级联的 2/3分 频单元的总数 n根据所需最大分频比确定， 所述最大分频比为 2n+1-l , 所述 多模可编程分频器的最小分频比根据所述多模可编程分频器的有效位数 Ne 确定， 所述最小分频比为 2Ne+1; 在图 4所示的结构图中， 前 Ne级为标准的 2/3 分频单元（即不带分频比扩展位的 2/3 分频单元）级联， 后续的 n-Ne 级为带分频比扩展位的 2/3分频单元级联； The technical solutions of the present invention are further elaborated below in conjunction with the accompanying drawings and specific embodiments. A multi-mode programmable frequency divider provided by an embodiment of the present invention, as shown in FIG. 4, includes: a primary frequency division level composed of cascaded 2/3 frequency division units, and 2/3 points of the cascade The number of 2/3 frequency division units without frequency division extension bits in the frequency unit is Ne, and the number of 2/3 frequency division units with frequency division ratio extension bits is n-Ne, Ne is the multimode programmable The effective number of bits of the frequency divider; the total number n of the cascaded 2/3 frequency dividing units is determined according to a required maximum frequency dividing ratio, and the maximum frequency dividing ratio is 2 n+1 -l , and the multimode can be The minimum division ratio of the programming frequency divider is determined according to the effective number of bits Ne of the multimode programmable frequency divider, and the minimum division ratio is 2 Ne+1 ; in the structure diagram shown in FIG. 4, the front Ne The level is a standard 2/3 frequency division unit (ie, a 2/3 frequency division unit without a division ratio extension bit), and the subsequent n-Ne stage is a 2/3 frequency division unit with a frequency division ratio extension bit. cascade;
该多模可编程分频器还包括： 实时功耗控制电路和电源开关控制晶体 管， 其中，  The multi-mode programmable frequency divider further includes: a real-time power consumption control circuit and a power switch control transistor, wherein
实时功耗控制电路由 n-Ne-1级两输入与门组成， 第 n级 2/3分频单元 的分频比控制位 P[n]的反向信号 Pinv[n]连接第 n级 2/3分频单元的电源控 制位 power— Ctrl;第 n级 2/3分频单元的分频比控制位 P[n]的反向信号 Pinv[n]、 以及第 n-1级 2/3分频单元的分频比控制位 P[n-1]的反向信号 Pinv[n-1], 对 应连接到第 n级与门的两输入端， 第 n级与门的输出端一方面连接到第 n-1 级 2/3分频单元的 Power— Ctrl端， 另一方面与第 n-2级 2/3分频单元的分频 比控制位 P[n-2]的反向信号 Pinv[n-2]对应连接到第 n-1级与门的两输入端； 依此类推， 直至第 n-Ne级 2/3分频单元和第 n-Ne-1级与门。 The real-time power consumption control circuit is composed of two-input and gates of n-Ne-1 level, and the inverse signal Pinv[n] of the frequency division ratio control bit P[n] of the n-th stage 2/3 frequency division unit is connected to the nth stage 2 /3 frequency division unit power control Positioning power— Ctrl; the ratio of the inverse signal Pinv[n] of the division ratio control bit P[n] of the nth stage 2/3 division unit and the division ratio of the n-1th stage 2/3 division unit The inverted signal Pinv[n-1] of the control bit P[n-1] is connected to the two input terminals of the nth AND gate, and the output of the nth AND gate is connected to the n-1th level 2 on the one hand. The Power_ Ctrl terminal of the /3 frequency division unit, on the other hand, is connected to the reverse signal Pinv[n-2] of the division ratio control bit P[n-2] of the n-2th 2/3 division unit. To the two inputs of the n-1th AND gate; and so on, up to the n-Ne level 2/3 division unit and the n-Ne-1 level AND gate.
在图 4所示的结构图中， ^表示触发信号输入端， f。表示触发信号输出 端， modi表示模式控制信号输入端， mod。表示模式控制信号输出端， power— Ctrl表示电源控制位。  In the block diagram shown in Figure 4, ^ denotes the trigger signal input, f. Indicates the trigger signal output, modi represents the mode control signal input, mod. Indicates the mode control signal output, power—Ctrl indicates the power control bit.
电源开关控制晶体管的漏极连接所述带分频比扩展位的 2/3 分频单元 的电源端， 源极连接供电电源。 较佳的， 所述电源开关控制晶体管可以是 P 沟道场效应晶体管 （ PMOS管）。  The drain of the power switch control transistor is connected to the power supply terminal of the 2/3 frequency dividing unit with the frequency division ratio extension bit, and the source is connected to the power supply. Preferably, the power switch control transistor may be a P-channel field effect transistor (PMOS transistor).
其中，本发明实施例中多模可编程分频器内带分频比扩展位的 2/3分频 单元，其结构如图 5所示，本发明实施例的带分频比扩展位的 2/3分频单元， 是基于现有技术中带分频比扩展位的 2/3分频单元改进来实现的；本发明实 施例的带分频比扩展位的 2/3分频单元，其扩展位 P[n]的反向信号输出 P2inv 为实时控制信号， power— Ctrl 为被控端， 3 个触发器 DFF1、 DFF2、 DFF3 是含双输入 Dl、 D2的触发器， DFF4是单输入触发器， 所有触发器的时钟 来源于触发信号输入端 fin; DFF4的 QB端接输出 fo(即触发信号输出端）； DFF3的 D2端接模式控制信号输入端 modi, D1端接 DFF4的 Q端； DFF2 的 D2端接 P1端 (置数端）， D1端接 DFF3的 Q端； DFF1的 D2端接 DFF2 的 QB端， D1端接 DFF4的 QB端、 即 fo; DFF4的 D端接 DFF1的 Q端； P2端 （置数端）接 INV1 (反向器） 的输入端， INV1的输出端接 P2inv和 AND1 (与门）的输入端， DFF3的输出 Q端同时接到 AND1的另一个输入 端， AND1的输出端接到模式控制信号输出端 modo; PI和 P2也接到 AND2 (与门） 的输入端， AND2的输出端接到 P012; 所有 DFF的源端 Vt接到 电源开关控制晶体管（如 PMOS管 PM1 )的漏极， 电源开关控制晶体管（如 PM1 )的栅极接到 ower ctrl, 电源开关控制晶体管（如 PM1 )的源端接到 电源。 电源开关控制晶体管 PM1的漏极连接 2/3分频单元的源端 Vt, 源极 连接供电电源，那么电源开关控制晶体管根据 power— Ctrl接收到的信号来控 制给对应 2/3分频单元的电源连接或断开，进而实现对多模可编程分频器功 耗的实时控制。 In the embodiment of the present invention, the multi-mode programmable frequency divider has a 2/3 frequency division unit with a frequency division ratio extension bit, and the structure thereof is as shown in FIG. 5, and the frequency division ratio extension bit of the embodiment of the present invention is 2 The /3 frequency division unit is implemented based on the improvement of the 2/3 frequency division unit with the frequency division ratio extension bit in the prior art; the 2/3 frequency division unit with the frequency division ratio extension bit in the embodiment of the present invention, The reverse signal output P2inv of the extension bit P[n] is the real-time control signal, power_Ctrl is the controlled terminal, three flip-flops DFF1, DFF2, DFF3 are triggers with dual inputs D1, D2, and DFF4 is single-input trigger The trigger of all the triggers is derived from the trigger signal input terminal fin; the QB terminal of DFF4 is connected to the output fo (ie, the trigger signal output terminal); the D2 terminal of the DFF3 is connected to the mode control signal input terminal modi, and the D1 terminal is connected to the Q terminal of the DFF4; D2 of DFF2 is connected to P1 end (numbering end), D1 is connected to Q end of DFF3; D2 of DFF1 is connected to QB end of DFF2, D1 is connected to QB end of DFF4, that is, fo; D terminal of DFF4 is connected to Q of DFF1 The P2 terminal (the number of terminals) is connected to the input of INV1 (inverter), the output of INV1 is connected to the input of P2inv and AND1 (AND gate), and the input of DFF3 The Q terminal is connected to the other input of AND1 at the same time. The output of AND1 is connected to the mode control signal output terminal modo; PI and P2 are also connected to the input terminal of AND2 (AND gate), and the output terminal of AND2 is connected to P0 12 ; The source Vt of all DFFs is connected The power switch controls the drain of the transistor (such as PMOS transistor PM1), the gate of the power switch control transistor (such as PM1) is connected to ower ctrl, and the source of the power switch control transistor (such as PM1) is connected to the power supply. The drain of the power switch control transistor PM1 is connected to the source terminal Vt of the 2/3 frequency dividing unit, and the source is connected to the power supply. Then, the power switch control transistor controls the corresponding 2/3 frequency dividing unit according to the signal received by the power Ctrl. The power supply is connected or disconnected for real-time control of the power consumption of the multimode programmable divider.
较佳的，本发明实施例中带分频比扩展位的 2/3分频单元可以采用如图 6所示的 TSPC DFF的电路结构，该电路采用了优化毛刺和电荷共享效应的 技术， 从而能够提高多模可编程分频器的工作速度；  Preferably, the 2/3 frequency division unit with the frequency division ratio extension bit in the embodiment of the present invention can adopt the circuit structure of the TSPC DFF as shown in FIG. 6, which adopts a technique for optimizing the glitch and charge sharing effect, thereby Can improve the working speed of multi-mode programmable frequency divider;
较佳的，本发明实施例中带分频比扩展位的 2/3分频单元还可以采用图 7所示的内置与门的 TSPC DFF的电路结构， 通常情况下， 与门和 D触发 器是两个不同部分， 而图 7所示结构是在图 6所示结构基础上的改进， 它 将与门和 D触发器结合在一起， 即仅增加 D2端连接的 PMOS管 PM1和 NMOS管 NM1 , 实现了与门和图 6的功能， 从而缩短关键路径的长度， 减 少晶体管的个数， 提高工作频率， 降低功耗。  Preferably, the 2/3 frequency division unit with the frequency division ratio extension bit in the embodiment of the present invention can also adopt the circuit structure of the TSPC DFF with built-in AND gate shown in FIG. 7, and usually, the AND gate and the D flip-flop It is two different parts, and the structure shown in Figure 7 is an improvement on the structure shown in Figure 6. It will be combined with the gate and the D flip-flop, that is, only the PMOS tube PM1 and the NMOS tube NM1 connected to the D2 terminal are added. The function of the AND gate and Figure 6 is realized, thereby shortening the length of the critical path, reducing the number of transistors, increasing the operating frequency, and reducing power consumption.
综上所述， 本发明实施例的多模可编程分频器， 通过增设的实时功耗 控制电路和电源开关控制晶体管， 能够实时地控制多模分频器在不同分频 比下 2/3分频单元的工作状况， 有效地避免多模可编程分频器功耗的浪费； 另外， 本发明实施例的电路结构简单， 只在原多模可编程分频器基础上增 加一系列与门和 PMOS管， 而且所增加的门电路工作在输出信号频率， 不 增加额外功耗。  In summary, the multi-mode programmable frequency divider of the embodiment of the present invention can control the multi-mode frequency divider in different frequency division ratios by 2/3 in real time by adding a real-time power consumption control circuit and a power switch control transistor. The working condition of the frequency dividing unit effectively avoids waste of power consumption of the multimode programmable frequency divider; in addition, the circuit structure of the embodiment of the invention is simple, and only a series of AND gates are added on the basis of the original multimode programmable frequency divider. The PMOS transistor, and the added gate operates at the output signal frequency, without adding additional power.
以上所述， 仅为本发明的较佳实施例而已， 并非用于限定本发明的保 护范围。  The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Claims

权利要求书 claims
1、 一种多模可编程分频器， 包括： 由级联的 2/3分频单元构成的主 分频级， 所述级联的 2/3分频单元中不带分频比扩展位的 2/3分频单元的 数量为 Ne, 带分频比扩展位的 2/3分频单元的数量为 n-Ne, Ne为所述多 模可编程分频器的有效位数， 1. A multi-mode programmable frequency divider, including: a main frequency dividing stage composed of cascaded 2/3 frequency dividing units, and the cascaded 2/3 frequency dividing units do not have a frequency division ratio extension bit. The number of 2/3 frequency dividing units is Ne, the number of 2/3 frequency dividing units with frequency division ratio extension bits is n-Ne, Ne is the effective number of bits of the multi-mode programmable frequency divider,
所述多模可编程分频器还包括： 实时功耗控制电路和电源开关控制 晶体管， The multi-mode programmable frequency divider also includes: a real-time power consumption control circuit and a power switch control transistor,
所述实时功耗控制电路由 n-Ne-1级两输入与门组成， 第 n级 2/3分 频单元的分频比控制位 P[n]的反向信号 Pinv[n]连接第 n级 2/3分频单元 的电源控制位 power— Ctrl; 第 n级 2/3分频单元的分频比控制位 P[n]的反 向信号 Pinv[n]、以及第 n-1级 2/3分频单元的分频比控制位 P[n-1]的反向 信号 Pinv[n-1] , 对应连接到第 n级与门的两输入端， 第 n级与门的输出 端一方面连接到第 n-1级 2/3分频单元的 Power— Ctrl端，另一方面与第 n-2 级 2/3分频单元的分频比控制位 P[n-2]的反向信号 Pinv[n-2]对应连接到第 n-1级与门的两输入端；依此类推，直至第 n-Ne级 2/3分频单元和第 n-Ne-1 级与门； The real-time power consumption control circuit is composed of n-Ne-1-stage two-input AND gates. The reverse signal Pinv[n] of the frequency division ratio control bit P[n] of the n-th stage 2/3 frequency division unit is connected to the n-th The power control bit power—Ctrl of the stage 2/3 frequency dividing unit; the reverse signal Pinv[n] of the frequency division ratio control bit P[n] of the nth stage 2/3 frequency dividing unit, and the n-1th stage 2 The inverse signal Pinv[n-1] of the frequency division ratio control bit P[n-1] of the /3 frequency dividing unit is connected to the two input terminals of the n-th level AND gate and the output terminal of the n-th level AND gate. On the one hand, it is connected to the Power-Ctrl terminal of the n-1st stage 2/3 frequency division unit, and on the other hand, it is connected to the reverse direction of the frequency division ratio control bit P[n-2] of the n-2th stage 2/3 frequency division unit. The signal Pinv[n-2] is correspondingly connected to the two input terminals of the n-1th level AND gate; and so on, until the n-Neth level 2/3 frequency dividing unit and the n-Ne-1th level AND gate;
所述电源开关控制晶体管的漏极连接相应带分频比扩展位的 2/3 分 频单元的电源端， 源极连接供电电源， 栅极连接相应带分频比扩展位的 2/3分频单元的 Power— Ctrl端。 The drain of the power switch control transistor is connected to the power end of the corresponding 2/3 frequency division unit with the frequency division ratio extension bit, the source is connected to the power supply, and the gate is connected to the corresponding 2/3 frequency division unit with the frequency division ratio extension bit. Power—Ctrl side of the unit.
2、 根据权利要求 1 所述多模可编程分频器， 其中， 所述级联的 2/3 分频单元的总数 n根据所需最大分频比确定， 所述最大分频比为 2n+1-l , 所述多模可编程分频器的最小分频比根据所述多模可编程分频器的有效 位数 Ne确定， 所述最小分频比为 2Ne+1。 2. The multi-mode programmable frequency divider according to claim 1, wherein the total number n of the cascaded 2/3 frequency dividing units is determined according to the required maximum frequency dividing ratio, and the maximum frequency dividing ratio is 2 n +1 -1, the minimum frequency division ratio of the multi-mode programmable frequency divider is determined according to the effective number of digits Ne of the multi-mode programmable frequency divider, and the minimum frequency division ratio is 2 Ne+1 .
3、 根据权利要求 1或 2所述多模可编程分频器， 其中， 所述带分频 比扩展位的 2/3分频单元， 其扩展位的反向信号输出 P2inv为实时控制信 号， power— Ctrl为被控端， 3个触发器 DFF1、 DFF2、 DFF3是含双输入 Dl、 D2的触发器， DFF4是单输入触发器， 所有触发器的时钟来源于触 发信号输入端 fin; DFF4的 QB端接触发信号输出端 fo; DFF3的 D2端 接模式控制信号输入端 modi, D1端接 DFF4的 Q端； DFF2的 D2端接 置数端 PI , D1端接 DFF3的 Q端； DFF1的 D2端接 DFF2的 QB端， D1端接 DFF4的 QB端、 即 fo; DFF4的 D端接 DFF1的 Q端； 置数端 P2接反向器 INV1的输入端， INV1的输出端接 P2inv和与门 AND1的输 入端， DFF3的输出 Q端同时接到 AND1的另一个输入端， AND1的输出 端接到模式控制信号输出端 modo; PI和 P2也接到与门 AND2的输入端， AND2的输出端接到 P012; 所有 DFF的源端 Vt接到电源开关控制晶体 管的漏极， 电源开关控制晶体管的栅极接到 power— Ctrl, 电源开关控制晶 体管的源端接到电源。 3. The multi-mode programmable frequency divider according to claim 1 or 2, wherein the 2/3 frequency dividing unit with a frequency division ratio extension bit, the reverse signal output P2inv of the extension bit is a real-time control signal No., power—Ctrl is the controlled terminal, the three flip-flops DFF1, DFF2, and DFF3 are flip-flops with dual inputs Dl and D2, DFF4 is a single-input flip-flop, and the clocks of all flip-flops come from the trigger signal input terminal fin; The QB terminal of DFF4 is connected to the signal output terminal fo; the D2 terminal of DFF3 is connected to the mode control signal input terminal modi, and the D1 terminal is connected to the Q terminal of DFF4; the D2 terminal of DFF2 is connected to the digital terminal PI, and the D1 terminal is connected to the Q terminal of DFF3; DFF1 The D2 terminal is connected to the QB terminal of DFF2, and the D1 terminal is connected to the QB terminal of DFF4, that is, fo; the D terminal of DFF4 is connected to the Q terminal of DFF1; the setting terminal P2 is connected to the input terminal of the inverter INV1, and the output terminal of INV1 is connected to P2inv and The input terminal of AND gate AND1 and the output Q terminal of DFF3 are simultaneously connected to the other input terminal of AND1, and the output terminal of AND1 is connected to the mode control signal output terminal modo; PI and P2 are also connected to the input terminal of AND gate AND2, and the output terminal of AND2 The output terminal is connected to P0 12 ; the source terminal Vt of all DFFs is connected to the drain of the power switch control transistor, the gate of the power switch control transistor is connected to power-Ctrl, and the source terminal of the power switch control transistor is connected to the power supply.
4、 根据权利要求 1或 2所述多模可编程分频器， 其中， 所述带分频 比扩展位的 2/3分频单元采用真单相时钟 D触发器 TSPC DFF。 4. The multi-mode programmable frequency divider according to claim 1 or 2, wherein the 2/3 frequency dividing unit with frequency division ratio extension bit adopts a true single-phase clock D flip-flop TSPC DFF.
5、 根据权利要求 4所述多模可编程分频器， 其中， 所述带分频比扩 展位的 2/3分频单元采用内置与门的 TSPC DFF。 5. The multi-mode programmable frequency divider according to claim 4, wherein the 2/3 frequency dividing unit with a frequency division ratio expansion bit adopts a TSPC DFF with a built-in AND gate.
6、 根据权利要求 1或 2所述多模可编程分频器， 其中， 所述电源开 关控制晶体管为 P沟道场效应晶体管 PMOS。 6. The multi-mode programmable frequency divider according to claim 1 or 2, wherein the power switch control transistor is a P-channel field effect transistor PMOS.
PCT/CN2013/090479 2013-04-19 2013-12-25 Multimode programmable frequency divider WO2014169681A1 (en)

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