CN111987142B - Trench array transistor structure and preparation method thereof - Google Patents

Trench array transistor structure and preparation method thereof Download PDF

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Publication number
CN111987142B
CN111987142B CN201910438272.2A CN201910438272A CN111987142B CN 111987142 B CN111987142 B CN 111987142B CN 201910438272 A CN201910438272 A CN 201910438272A CN 111987142 B CN111987142 B CN 111987142B
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oxide layer
trench
transistor structure
array transistor
insulating layer
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CN111987142A (en
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杨正杰
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

The disclosure provides a trench array transistor structure and a preparation method thereof, and relates to the technical field of integrated circuit manufacturing. The preparation method of the trench array transistor structure comprises the steps of forming a trench in a substrate base plate with a source region by etching; forming an oxide layer on the bottom and the side wall of the groove through first oxidation; filling an insulating layer in the trench by deposition; removing the insulating layer by etching part to expose the oxide layer on the upper part of the side wall of the groove; an oxide extension is formed by the extension of the oxide exposed at the upper portion of the second oxidized sidewall. The technical scheme provided by the disclosure can effectively improve the problem that the trench array transistor is easy to generate leakage current.

Description

Trench array transistor structure and preparation method thereof
Technical Field
The present disclosure relates to the field of integrated circuit manufacturing technology, and in particular, to a trench array transistor structure and a method for manufacturing the same.
Background
Transistors are now widely used in memory, registers, and integrated circuits, and as device fabrication technologies develop, the size becomes smaller and smaller, causing transistor short channel effects to occur. Trench channel array transistors (RCAT, RECESS CHANNEL ARRAY transistors) have a smaller channel length, which reduces short channel effects, and have been widely used in recent years.
However, as the size of the trench channel array transistor continues to shrink, gate-induced drain leakage (GIDL) currents (gate-induced DRAIN LEAKAGE) in the gate-drain overlap region tend to occur, and among these leakage currents, the GIDL currents dominate the leakage currents when the device in the integrated circuit is in an off state or in a standby state, and have a large impact on the reliability of the trench channel array transistor. The oxide layer of the conventional trench array transistor structure is uniformly covered on the inner wall of the trench, so that the GIDL leakage current is poorly controlled and is easy to generate. Therefore, the problem that the trench channel array transistor is easy to generate leakage current is an urgent need in the technical field of integrated circuit manufacturing.
It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure provides a trench array transistor structure and a method for manufacturing the same, which can effectively improve the problem of easily generating leakage current.
Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.
According to another aspect of the present disclosure, there is provided a method for manufacturing a trench array transistor structure, including: forming a trench in a substrate base plate having an active region by etching; forming an oxide layer on the bottom and the side wall of the groove through first oxidation; filling an insulating layer in the trench by deposition; removing the insulating layer by etching part to expose the oxide layer on the upper part of the side wall of the groove; and forming an oxide layer extension part by oxidizing the oxide layer extension exposed at the upper part of the side wall for the second time.
In one embodiment, the method for manufacturing the trench array transistor structure further includes: removing the insulating layer in the groove and on the substrate; forming a conductive layer by deposition on the oxide layer, the conductive layer being located within the trench; forming a filled insulating layer over the conductive layer within the trench; and forming a source electrode and a drain electrode on two sides of the groove in the active region.
In one embodiment, the method for manufacturing the trench array transistor structure further includes: the first oxidation and the second oxidation respectively adopt one of a dry oxygen oxidation process and a wet oxygen oxidation process.
In one embodiment, the method for manufacturing the trench array transistor structure further includes: and removing the insulating layer by etching the part, wherein the removing depth of the insulating layer in the groove is 20-50 nanometers.
In one embodiment, the thickness of the lower portion of the oxide layer ranges from 1 nm to 4 nm.
In one embodiment, the oxide layer extends in a direction toward the drain or source for a length of 2 nm to 10 nm.
In one embodiment, the shape of the groove is U-shaped, rectangular, and inverted trapezoid.
According to one aspect of the present disclosure, there is provided a trench array transistor structure comprising: the semiconductor device comprises a substrate, a groove and an oxide layer. The substrate base plate is provided with an active area, wherein a source electrode and a drain electrode are arranged in the active area. A trench is located within the substrate base through the active region, including a bottom and sidewalls. An oxide layer covers the bottom and the side walls of the trench, and a first oxide layer extension part is arranged on the upper part of the first side of the oxide layer in the direction close to the source electrode or the drain electrode.
In one embodiment, the oxide layer further includes the first oxide layer extension proximate the drain direction and a second oxide layer extension proximate the source direction.
In one embodiment, the trench array transistor structure further comprises a conductive layer and a filled insulating layer. A conductive layer is located within the trench. A fill insulating layer is located over the conductive layer within the trench.
In one embodiment, the thickness of the first oxide layer extension and the second oxide layer extension is 2 nm to 10 nm.
In one embodiment, the first oxide layer extension and the second oxide layer extension have a depth of 20 nanometers to 50 nanometers.
In one embodiment, the thickness of the lower portion of the first oxide layer ranges from 1 nm to 4 nm.
In one embodiment, the shape of the groove is U-shaped, rectangular, and inverted trapezoid.
The technical scheme provided by the embodiment of the disclosure can comprise the following beneficial effects:
The present disclosure provides a trench array transistor structure and a method of fabricating the same, the trench of the trench array transistor structure comprising: the oxide layer of the trench array transistor is provided with an oxide layer extension part, so that the thickness of the oxide layer between the source electrode and the drain electrode which are positioned at two sides of the trench is increased, and the problem of easy leakage current generation can be effectively solved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
Fig. 1 is a flowchart of a method for manufacturing a trench array transistor structure according to an embodiment of the present disclosure;
FIG. 2 is a flow chart of a method of preparing a partially removed insulating layer provided in an embodiment of the present disclosure;
Fig. 3 to 11 are schematic partial cross-sectional structures of the trench array transistor structure provided in one embodiment of the present disclosure at various steps in the fabrication process;
Fig. 12-13 are schematic views of a partial interface structure of an oxide layer extension of a trench array transistor structure according to an embodiment of the present disclosure at various steps in the fabrication process;
fig. 14 is a schematic partial cross-sectional structure of a trench array transistor structure in one embodiment of the disclosure;
fig. 15 is a schematic partial cross-sectional structure of a trench array transistor structure in another embodiment of the disclosure;
fig. 16 is a schematic partial cross-sectional structure of a trench array transistor structure in another embodiment of the disclosure;
fig. 17 is a schematic view of a partial cross-sectional structure of a trench array transistor structure in another embodiment of the disclosure;
fig. 18 is a schematic partial cross-sectional structure of a trench array transistor structure in another embodiment of the disclosure;
Fig. 19 is a schematic partial cross-sectional structure of a trench array transistor structure in another embodiment of the disclosure.
Reference numerals illustrate:
300: substrate base
1111: Source electrode
1112: Drain electrode
320: Groove(s)
321: Bottom part
322: Side wall
430: Oxide layer
431: First side
432: Second side
433: First oxide layer extension
434: Second oxide layer extension
910: Conductive layer
1010: Filling an insulating layer
310: Mask layer
330: Active region
510: Insulating layer
T1: thickness of oxide layer extension
T2: depth of oxide extension
T3: thickness of oxide layer
D1: width of opening of trench
D2: depth of groove
D3: depth of removal of insulating layer in trench
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature.
The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the disclosed aspects may be practiced without one or more of the specific details, or with other methods, steps, etc. In other instances, well-known methods, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.
Fig. 1 is a flowchart of a method for manufacturing a trench array transistor structure according to an embodiment of the disclosure. The preparation method of the trench array transistor structure comprises the following steps.
In step S101, a trench is formed in a substrate base plate having a source region by etching.
In step S102, an oxide layer is formed on the bottom and the sidewall of the trench by the first oxidation.
Step S103, filling the trench with an insulating layer by deposition.
In step S104, the oxide layer located at the upper portion of the sidewall of the trench is exposed by partially removing the insulating layer by etching.
Step S105, forming an oxide layer extension portion by oxidizing the oxide layer extension exposed at the upper portion of the sidewall for the second time.
Referring to fig. 3 to 11, schematic partial cross-sectional structures of the trench array transistor structure provided in the embodiments of the present disclosure at various steps in the fabrication process are shown. A detailed process for preparing the trench array transistor structure will be given below.
In step S101, referring to fig. 3, a trench 320 is etched on a substrate 300 using a mask layer 310, the trench 320 passes through an active region 330, and the trench 320 includes a bottom 321 and a sidewall 322. Specifically, the substrate 300 may be etched using at least one of a dry etching process or a wet etching process. The shape of the trench 320 is, for example but not limited to, U-shape, the opening width d1 of the trench 320 ranges from 20 nm to 80nm, and the depth d2 of the trench 320 ranges from 100 nm to 200 nm.
In some embodiments of the present disclosure, the material of mask layer 310 is, for example, but not limited to, nitride. The material of the substrate 300 may be a monocrystalline or polycrystalline semiconductor material, for example, the substrate 300 is a monocrystalline silicon substrate or a polycrystalline silicon substrate, or a lightly doped silicon substrate. The material of the substrate 300 is not limited to this as long as it meets the requirement of device performance.
In some embodiments of the present disclosure, the number of trenches 320 may be set according to the actual requirements of the device. The cross-sectional shape of the trench 320 may also be rectangular, inverted trapezoidal, etc. in various shapes consistent with device performance.
In step S102, referring to fig. 4, a first oxide layer 430 is formed on the bottom 321 and the second sidewall 322 of the trench 320 by first oxidation. Specifically, the trench 320 may be oxidized by one of a dry oxygen oxidation process and a wet oxygen oxidation process to form an oxide layer 430 covering the bottom 321 and the sidewalls 322 of the trench 320. In the dry oxygen oxidation process, a hot oxygen flow is injected into the trench 320, and the temperature of the oxygen ranges from 800 ℃ to 3000 ℃, so that the oxide layer 430 with uniform thickness and fewer defects can be prepared. In the preparation process of the wet oxygen oxidation process, a water vapor process is adopted for preparation, and a large amount of gas-phase active free radicals are generated in the preparation process and participate in the oxidation of silicon, so that an oxide layer with uniform thickness and fewer defects is obtained. The main component of the oxide layer 430 is silicon oxide, and the thickness of the oxide layer 430 ranges from 1 nm to 4 nm.
In step S103, an insulating layer 510 is filled in the trench 320 by deposition with reference to fig. 5; specifically, chemical vapor deposition may be used to fill the trench 320 with the insulating layer 510. The material of the insulating layer 510 may be any suitable insulating material, such as an insulating oxide, nitride, oxynitride, etc. However, if the material of the insulating layer 510 is the same as that of the mask layer 310, for example, nitride, the mask layer 310 on the substrate 300 in step S102 does not need to be processed, and step S103 may be directly performed. If the material of the insulating layer 510 is different from that of the mask layer 310, the mask layer 310 in step S102 may be etched by a dry etching process or a wet etching process, and then step S103 is performed. The trench 320 will be completely filled with the insulating layer 510.
In step S104, a part of the insulating layer 510 formed in step S103 is etched away with reference to fig. 6. A dry etching process or a wet etching process may be employed. The center line of the removed region of the insulating layer 510 is not coincident with the center line of the trench 320, i.e., the insulating layer 510 is asymmetrically etched to expose an upper portion of the first side 431 of the oxide layer 430 located on the upper portion of the sidewall 322 of the trench 320 near the drain side. While the other side upper portion of the trench 320 corresponding to the first side 431 of the exposed oxide layer 430 is still covered by the insulating layer 510. The removal depth d3 of the insulating layer 510 in the trench 320 ranges from 20nm to 50 nm.
Fig. 2 is a flowchart of a method for preparing a partially removed insulating layer provided in an embodiment of the present disclosure.
Referring to fig. 2, the detailed procedure of etching a portion of the insulating layer 510 is as follows.
In step S201, a photoresist layer is formed on the surface of the insulating layer 510.
In step S202, exposure is performed through the corresponding mask, and the pattern of the mask is transferred to the photoresist layer.
In step S203, the photoresist layer is exposed to the region to be removed by development.
In step S204, a removal region is formed in the insulating layer by etching. Specifically, the insulating layer 510 may be etched by a dry etching process, and in the preparation process, the etching gas used is, for example, sulfur hexafluoride gas, and the etching depth of the insulating layer 510 is controlled by adjusting the flow rate and the etching time of the etching gas.
In step S205, the photoresist layer is removed, forming the structure shown in fig. 6.
The etching method for the insulating layer provided in the above embodiment can control the etching depth of the insulating layer 510.
In step S105, referring to fig. 7, a second oxidation process is performed, and one of a dry oxidation process and a wet oxidation process may be used to oxidize the wall surface of the trench 320, or an ion implantation process is performed before oxidation, so as to form a first oxide layer extension 433 extending in a direction approaching the drain on the upper portion of the first side 431 of the oxide layer 430. The thickness t1 of the first oxide layer extension 433 ranges from 2nm to 10 nm.
Referring to fig. 8, the insulating layer 510 within the trench 320 and on the substrate 300 is etched to expose the entire oxide layer 430 on the walls of the trench 320. The insulating layer 510 on the substrate 300 may be removed by a dry etching process or a wet etching process, or by chemical-mechanical planarization (CMP).
In some embodiments of the present disclosure, the first oxidation and the second oxidation may be performed by one of a dry oxidation process and a wet oxidation process, and the processes used in the two oxidation processes may be the same or different, in other words, the two oxidation processes have no effect on each other.
In the above embodiments of the present disclosure, the design of the oxide layer 430 of the trench 320 with the first oxide layer extension 433 increases the thickness of the upper oxide layer on both sides of the trench 320, so that the problem that the trench array transistor is prone to generate leakage current can be effectively improved.
As shown in fig. 9, a conductive layer 910 is formed by deposition within the trench. Specifically, the material of the conductive layer 910 is selected from a metal-containing conductive material, such as titanium nitride, gold tungsten, and may be prepared by electroplating, chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
As shown in fig. 10, a filled insulating layer 1010 is formed over conductive layer 910 within trench 320. Specifically, the material of the insulating layer 1010 may be selected from suitable insulating materials, such as insulating oxides, nitrides, oxynitrides, and the like. The fill insulating layer 1010 may be formed using a suitable fabrication process such as chemical deposition. The top surface of the formed filled insulating layer remains flush with the top of the substrate base 300.
As shown in fig. 11, a trench array transistor structure is formed. Specifically, a source 1111 and a drain 1112 are formed on two sides of the trench 320 in the substrate 300, wherein the drain 1112 is located on one side of the trench 320 close to the first oxide extension 433, and the source 1111 is located on the other side of the trench 320 far from the drain 1112. Specifically, an ion implantation process is used to dope the active region, for example, N-type conductivity impurities, to obtain a source 1111 and a drain 1112. The P-type conductive impurities may be doped here, which is not limited in this disclosure.
In some embodiments of the present disclosure, another method for fabricating a trench array transistor structure is different from the above method for fabricating the trench array transistor structure in that: in step S104 shown in fig. 6, a portion of the insulating layer 510 is etched away on a side near the source 1111 to expose the oxide layer 430 on a side near the source 1111 on the second side 432 of the trench 320. Then, a second oxide extension 434 is formed to be located at a side near the source electrode 1111. And will not be described in detail herein.
In some embodiments of the present disclosure, another fabrication method of a trench array transistor structure is different from the above-described fabrication method in that the process of forming the first oxide layer extension 433 in steps 104 and 105 is different. The same steps will not be described in detail. Fig. 12 to 13 are schematic views of a partial interface structure of an oxide layer extension of a trench array transistor structure according to an embodiment of the present disclosure at various steps in the fabrication process.
Fig. 12 is different from fig. 6 in that: the insulating layer 510 is symmetrically etched to expose the oxide layer 430 at the upper portions of both sidewalls of the trench 320. The removal depth d3 of the insulating layer 510 in the trench 320 is also in the range of 20 nm to 50 nm.
Referring to fig. 13, the second oxidation process is performed, and the wall surface of the trench 320 may be oxidized by one of a dry oxidation process and a wet oxidation process, so as to form a first oxide layer extension 433 and a second oxide layer extension 434 on the upper portions of the two sides of the oxide layer 430, which extend in a direction close to the drain and the source, respectively. Wherein the first oxide extension 433 is located at a side near the drain 1112 and the second oxide extension 434 is located at a side near the source 1111.
In some embodiments of the present disclosure, another method for fabricating a trench array transistor structure is different from the previous method in that: the oxidation process conditions for forming the oxide layer extensions are different and the shape of the resulting extensions is slightly different. And will not be described in detail herein.
In addition, other methods may be employed by those skilled in the art to form the trench array transistor structures provided by the disclosed embodiments, but remain within the scope of the disclosure.
In summary, in the method for manufacturing a trench array transistor according to the above embodiment of the present disclosure, the oxide layer has the design of the oxide layer extension portion, so that the thickness of the oxide layer covered on both sides of the upper portion of the trench 320 is increased, that is, the thickness of the oxide layer between the source 1111 and the drain 1112 is increased, which can effectively improve the problem that the trench array transistor is prone to generate leakage current.
Fig. 14 is a schematic partial cross-sectional structure of a trench array transistor structure in one embodiment of the disclosure.
As shown in fig. 14, the trench array transistor structure includes a substrate base 300, an active region 330, a trench 320, an oxide layer 439, a conductive layer 910, and a fill insulation layer 1010. The material of the substrate 300 may be a monocrystalline or polycrystalline semiconductor material, for example, the substrate 300 is a monocrystalline silicon substrate or a polycrystalline silicon substrate, or a lightly doped silicon substrate, which is not limited in this disclosure. The substrate 300 has a source region 330, and the source 1111 and the drain 1112 are obtained by doping the source region 330 with an ion implantation process, for example, doping with N-type conductive impurities. The P-type conductive impurities may be doped here, which is not limited in this disclosure. The source 1111 and the drain 1112 are disposed on opposite sides of the trench 320.
With continued reference to fig. 14, a trench 320 is disposed in the substrate 300 through the active region 330, and includes a bottom 321 and a sidewall 322, and the cross-sectional shape of the trench 320 is, for example, U-shaped as shown in fig. 1. Oxide layer 131 covers the bottom and sidewalls 322 of trench 320. The material of the oxide layer 430 is, for example and without limitation, silicon oxide, which may include silicon monoxide and silicon dioxide. In this embodiment, the oxide layer 430 may be formed by one of a dry oxygen oxidation process or a wet oxygen oxidation process. The upper portion of the first side 431 of the oxide layer has a first oxide layer extension 433 in a direction close to the drain. The material of the first oxide layer extension 433 is, for example, but not limited to, silicon oxide, which may include silicon monoxide and silicon dioxide. Conductive layer 910 is located within trench 320. The material of the conductive layer 910 is selected from a metal-containing conductive material, such as titanium nitride or Jin Wu, and the conductive layer 910 may be formed by electroplating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like. A fill insulating layer 1010 is located over conductive layer 910 within trench 320. The material filling the insulating layer 1010 may be selected from suitable insulating materials, such as insulating oxides, nitrides, oxynitrides, and the like. The filling insulating layer 1010 may be formed by a suitable preparation process such as chemical deposition, which is not limited in this disclosure. The top surface of the fill insulation layer 1010 is flush with the top surface of the substrate base 300.
In some embodiments of the present disclosure, the cross-sectional shape of trench 320 may also be rectangular, inverted trapezoidal, etc. in various shapes consistent with device performance.
As shown in fig. 1, the thickness t1 of the first oxide layer extension 433 ranges from 2 nm to 10 nm. The depth t2 of the first oxide layer extension 433 ranges from 20 nanometers to 50 nanometers. The thickness t3 of the lower portion of the oxide layer 433 ranges from 1 nm to 4 nm.
The trench array transistor structure provided by the above embodiments of the present disclosure has the design that the oxide layer 430 has the first oxide layer extension 433 increases the thickness of the oxide layer between the source 1111 and the drain 1112, and can effectively improve the leakage current problem.
Fig. 15 to 19 are schematic partial cross-sectional structures of trench array transistor structures in further embodiments of the present disclosure.
The trench array transistor structure in fig. 15 is different from that of fig. 14 in that: the bottom of the first oxide layer extension 433 is an inclined surface, and oxidation conditions used in the process of preparing the first oxide layer extension 433 are different and the shape is slightly changed. The trench array transistor structure of fig. 15 can also achieve an increase in the thickness of the oxide layer between the source 1111 and the drain 1112, and can effectively improve the problem of leakage current.
The trench array transistor structure in fig. 16 is different from that in fig. 14 in that: the upper source 1111 of the second side 432 of the oxide layer has a second oxide layer extension 434 in the direction of the upper source 1111. The trench array transistor structure of fig. 16 can also achieve an increase in the thickness of the oxide layer between the source 1111 and the drain 1112, and can effectively improve the problem of leakage current.
The trench array transistor structure in fig. 17 differs from that of fig. 16 in that: the bottom of the second oxide extension 434 is a slope, and the oxidation conditions used in the process of preparing the second oxide extension 434 are different and the shape is slightly changed. The trench array transistor structure of fig. 17 can also achieve an increase in the thickness of the oxide layer between the source 1111 and the drain 1112, and can effectively improve the problem of leakage current.
The trench array transistor structure in fig. 18 is different from that of fig. 14 to 17 in that: the oxide layer has a first oxide extension 433 and a second oxide extension 434, which are located on a side near the source 1111 and a side near the drain 1112, respectively. The trench array transistor structure in fig. 18 can also achieve an increase in the thickness of the oxide layer between the source 1111 and the drain 1112, and can effectively improve the problem of leakage current.
The trench array transistor structure in fig. 19 differs from that of fig. 18 in that: the bottom portions 434 of the first oxide layer extension 433 and the second oxide layer extension 434 are inclined planes, and the oxidation conditions used in the process of the first oxide layer extension 433 and the second oxide layer extension 434 are different, and the shapes are slightly changed. The trench array transistor structure in fig. 19 can also achieve an increase in the thickness of the oxide layer between the source 1111 and the drain 1112, and can effectively improve the problem of leakage current easily generated.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. The present disclosure is not limited to the precise construction that has been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (13)

1. A method for manufacturing a trench array transistor structure is characterized in that,
Comprising the following steps:
forming a trench in a substrate base plate having an active region by etching;
forming an oxide layer on the bottom and the side wall of the groove through first oxidation;
Filling an insulating layer in the trench by deposition;
Removing the insulating layer by etching part to expose the oxide layer on the upper part of the side wall of the groove;
and forming an oxide layer extension part by oxidizing the oxide layer extension exposed at the upper part of the side wall for the second time.
2. The method according to claim 1, wherein,
Further comprises:
removing the insulating layer in the groove and on the substrate;
Forming a conductive layer by deposition on the oxide layer, the conductive layer being located within the trench;
Forming a filled insulating layer over the conductive layer within the trench;
And forming a source electrode and a drain electrode on two sides of the groove in the active region.
3. The method according to claim 1, wherein,
Further comprises:
The first oxidation and the second oxidation respectively adopt one of a dry oxygen oxidation process and a wet oxygen oxidation process.
4. The method according to claim 1, wherein,
Further comprises:
and removing the insulating layer by etching the part, wherein the removing depth of the insulating layer in the groove is 20-50 nanometers.
5. The method according to claim 1, wherein,
The thickness of the lower part of the oxide layer ranges from 1 nanometer to 4 nanometers.
6. The method according to claim 1, wherein,
The length of the oxide layer extending towards the direction close to the drain electrode or the source electrode is 2-10 nanometers.
7. The method according to claim 1, wherein,
The grooves are U-shaped, rectangular and inverted trapezoidal.
8. A trench array transistor structure is disclosed, wherein,
Comprising the following steps:
The substrate base plate is provided with an active area, wherein a source electrode and a drain electrode are arranged in the active area;
a trench in the substrate base passing through the active region, including a bottom and a sidewall;
An oxide layer covering the bottom and the side wall of the trench, wherein a first oxide layer extending part is arranged on the upper part of the first side of the oxide layer in the direction close to the source electrode or the drain electrode, and the bottom of the first oxide layer extending part is an inclined plane;
A conductive layer located within the trench;
and the filling insulating layer is positioned above the conductive layer in the groove, and the top surface of the filling insulating layer is kept flush with the top of the substrate base plate.
9. The trench array transistor structure of claim 8 wherein,
The oxide layer also includes the first oxide layer extension adjacent to the drain direction and a second oxide layer extension adjacent to the source direction.
10. The trench array transistor structure of claim 9 wherein,
The thickness of the first oxide layer extension part and the second oxide layer extension part is 2 nanometers to 10 nanometers.
11. The trench array transistor structure of claim 9 wherein,
The depth of the first oxide layer extension part and the second oxide layer extension part is 20 nanometers to 50 nanometers.
12. The trench array transistor structure of claim 8 or 9, wherein,
The thickness of the lower part of the first oxide layer ranges from 1 nanometer to 4 nanometers.
13. The trench array transistor structure of claim 8 or 9, wherein,
The grooves are U-shaped, rectangular and inverted trapezoidal.
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