CN209822649U - Trench array transistor structure - Google Patents

Abstract

The disclosure provides a trench array transistor structure, and relates to the technical field of integrated circuit manufacturing. The trench array transistor structure includes a substrate, a trench and a gate oxide layer. The substrate base plate is provided with an active area, wherein a source electrode and a drain electrode are arranged in the active area. The trench is located in the substrate and penetrates through the active region, and comprises a bottom, a side wall, a first extension portion and a second extension portion, wherein the first extension portion is located on one side, close to the source, of the upper portion of the side wall, and the second extension portion is located on one side, close to the drain, of the upper portion of the side wall. The gate oxide layer covers the bottom, the sidewall, the first extension portion and the second extension portion of the trench. The technical scheme provided by the disclosure can effectively improve the problem that the trench array transistor is easy to generate leakage current.

Description

Trench array transistor structure

Technical Field

The present disclosure relates to the field of integrated circuit manufacturing technologies, and in particular, to a trench array transistor structure.

Background

At present, transistors are widely used in memories, registers and integrated circuits, and as the manufacturing technology of each device is developed, the size of the transistors becomes smaller and smaller, which causes the occurrence of short channel effect of the transistors. A trench channel array transistor (RCAT) has a small channel length, and can reduce short channel effect, and is widely used in recent years.

However, when the size of the trench-channel array transistor is continuously reduced, the distance between the source and the drain at both sides of the trench is continuously reduced, and gate-induced drain leakage current (GIDL) of the gate-drain overlap region is easily generated. Therefore, the small size of the trench-channel array transistor is a problem to be solved in the field of integrated circuit manufacturing technology.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

SUMMERY OF THE UTILITY MODEL

The present disclosure is directed to solving the above-mentioned problems of the prior art, and provides a trench array transistor structure capable of effectively improving the problem of leakage current.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.

According to an aspect of the present disclosure, there is provided a trench array transistor structure, including: substrate base plate, slot and grid oxide layer. The substrate base plate is provided with an active area, wherein a source electrode and a drain electrode are arranged in the active area. The trench is located in the substrate and penetrates through the active region, and comprises a bottom, a side wall, a first extension portion and a second extension portion, wherein the first extension portion is located on one side, close to the source, of the upper portion of the side wall, and the second extension portion is located on one side, close to the drain, of the upper portion of the side wall. The gate oxide layer covers the bottom, the sidewall, the first extension portion and the second extension portion of the trench.

In one embodiment, the trench array transistor structure further comprises a conductive layer and a filling insulating layer. The conducting layer is located in the groove, and the top surface of the conducting layer is flush with the bottom end of the grid oxide layer in the extension portion. The filling insulating layer is positioned above the conducting layer in the groove.

In one embodiment, the length of the first extension portion extending from the sidewall of the trench to the source direction is 2 nm to 10 nm; the length of the second extension part extending from the side wall of the groove to the drain electrode direction is 2-10 nanometers.

In one embodiment, the first and second extensions have a depth of 20 nm to 50 nm.

In one embodiment, the gate oxide layer has a thickness of 1 nm to 4 nm.

In one embodiment, the grooves are U-shaped, rectangular, inverted trapezoidal in shape.

In one embodiment, the first extension and the second extension are asymmetrically disposed at two sides of the trench.

In one embodiment, the depth of the trench is 100 nanometers to 200 nanometers.

In one embodiment, the bottom surfaces of the first extension part and the second extension part are horizontal surfaces.

In one embodiment, the bottom surfaces of the first extension part and the second extension part are inclined surfaces.

According to another aspect of the present disclosure, there is provided a method for manufacturing a trench array transistor structure, including: forming a groove in the substrate base plate with the source region by etching; forming a first sacrificial oxide layer at the bottom and the side wall of the groove by first oxidation; filling an insulating layer in the groove through deposition; partially removing the insulating layer by etching to expose the first sacrificial oxide layer on the upper part of the side wall of the groove; forming a second sacrificial oxide layer by second oxidizing the first sacrificial oxide layer extension exposed from the upper portion of the sidewall; removing the insulating layer in the groove by etching; removing the first sacrificial oxide layer and the second sacrificial oxide layer in the trench to form a first extension portion and a second extension portion on the upper portion of the sidewall, wherein the first extension portion is located on one side of the upper portion of the sidewall close to the source, and the second extension portion is located on one side of the upper portion of the sidewall close to the drain; forming a gate oxide layer on the bottom, the sidewall, the first extension, and the second extension of the trench by a third oxidation.

In one embodiment, the method for preparing a trench array transistor structure further comprises: removing the insulating layer on the substrate base plate; forming a conductive layer on the gate oxide layer by deposition, wherein the conductive layer is positioned in the groove, and the top surface of the conductive layer is flush with the bottom end of the gate oxide layer; forming a filling insulating layer above the conductive layer in the groove; and forming a source electrode and a drain electrode on two sides of the groove in the active region.

In one embodiment, the method for preparing a trench array transistor structure further comprises: and the first oxidation, the second oxidation and the third oxidation respectively adopt one of a dry oxygen oxidation process and a wet oxygen oxidation process.

In one embodiment, the method for preparing a trench array transistor structure further comprises: and after the insulating layer is partially removed by etching, the removal depth of the insulating layer in the groove is 20 to 50 nanometers.

In one embodiment, the first sacrificial oxide layer has a thickness in a range from 1 nm to 4 nm.

In one embodiment, the length of the second sacrificial oxide layer extending from the first sacrificial oxide layer to the direction close to the drain and the source is 2 nm to 10 nm.

In one embodiment, the gate oxide layer has a thickness of 1 nm to 4 nm.

In one embodiment, the grooves are U-shaped, rectangular, inverted trapezoidal in shape.

The technical scheme provided by the embodiment of the disclosure can have the following beneficial effects:

the utility model provides a trench array transistor structure, trench of trench array transistor structure includes bottom, lateral wall, first extension and second extension, and first extension is located lateral wall upper portion is close to one side of source electrode and second extension is located lateral wall upper portion is close to one side of source electrode, and the design of first extension and second extension has increased the distance between trench upper portion both sides source electrode and the drain electrode, can effectively improve the problem that produces the leakage current easily.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic partial cross-sectional structure view of a trench array transistor structure in one embodiment of the present disclosure;

fig. 2A is a schematic partial cross-sectional structure diagram of a trench array transistor structure in another embodiment of the present disclosure;

FIG. 2B is an enlarged view of portion D of FIG. 2A;

fig. 3 is a flow chart of a method for fabricating a trench array transistor structure provided in an embodiment of the present disclosure;

fig. 4 is a flow chart of a method of manufacturing a partially removed insulating layer provided in an embodiment of the present disclosure;

fig. 5 to 16 are schematic partial cross-sectional views of the trench array transistor structure provided in one embodiment of the present disclosure at various steps in the manufacturing process.

Description of reference numerals:

100: substrate base plate

111: source electrode

112: drain electrode

120: groove

121: bottom part

122: side wall

123: first extension part

124: second extension part

130: grid oxide layer

140: conductive layer

150: filling the insulating layer

510: mask layer

520: active region

610: first sacrificial oxide layer

710: insulating layer

910: second sacrificial oxide layer

t 1: extension width of the extension part

t 2: depth of extension

d 1: width of opening of trench

d 2: depth of the trench

d 3: thickness of the first sacrificial oxide layer

d 4: depth of removal of insulating layer in trench

d 5: thickness of the second sacrificial oxide layer

d 6: first opening width of groove after forming extension part

d 7: second opening width of groove after forming extension part

t 3: thickness of gate oxide layer

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted.

Furthermore, the terms "first", "second", "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", "third" may explicitly or implicitly include one or more of the features.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, steps, etc. In other instances, well-known methods, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

Fig. 1 is a schematic partial cross-sectional structure diagram of a trench array transistor structure in an embodiment of the disclosure.

As shown in fig. 1, the trench array transistor structure includes a substrate 100, an active region, a trench 120, a gate oxide layer 130, a conductive layer 140, and a filling insulation layer 150. The material of the substrate 100 may be a single crystal or polycrystalline semiconductor material, for example, the substrate 100 is a single crystal silicon substrate or a polycrystalline silicon substrate, or a lightly doped silicon substrate, which is not limited in this disclosure. The substrate 100 has a source region, and the source region 111 and the drain region 112 are obtained by doping the source region with an ion implantation process, for example, doping N-type conductive impurities. P-type conductive impurities may also be doped herein, and the disclosure is not limited thereto. The source electrode 111 and the drain electrode 112 are oppositely disposed at two sides of the trench 120.

Continuing with fig. 1, trench 120 is situated in substrate 100 through the active region, and includes a bottom 121, a sidewall 122, and two extensions. The two extending portions are a first extending portion 123 and a second extending portion 124, respectively, and the cross-sectional shape of the trench 120 is, for example, a U shape as shown in fig. 1, in which the first extending portion 123 is located on a side of the sidewall 122 near the source 111 and the second extending portion 124 is located on a side of the sidewall 122 near the source 111. The gate oxide layer 130 covers the bottom 121, the sidewall 122, the first extension 123 and the second extension 124 of the trench 120. The gate oxide layer 130 is made of, for example, but not limited to, silicon oxide, which may include silicon oxide and silicon dioxide. In this embodiment, the gate oxide layer 130 may be formed by one of a dry oxidation process and a wet oxidation process. The conductive layer 140 is located in the trench 120, and the top surface of the conductive layer 140 is flush with the bottom end of the gate oxide layer 130. The conductive layer 140 is made of a conductive material containing metal, such as titanium nitride or gold tungsten, and the conductive layer 140 can be formed by electroplating, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. A fill insulating layer 150 is located over the conductive layer 140 within the trench 120. The material of the filling insulating layer 150 may be selected from suitable insulating materials, such as insulating oxide, nitride, oxynitride, and the like. The filling insulation layer 150 may be formed by a suitable preparation process such as chemical deposition, which is not limited in this disclosure. The top surface of the filling insulation layer 150 is flush with the top surface of the substrate base plate 100.

In some embodiments of the present disclosure, the cross-sectional shape of the trench 120 may also be rectangular, inverted trapezoidal, and the like, in various shapes that conform to device performance.

As shown in fig. 1, an extension width t1 of the extension portion, that is, a length of the first extension portion 123 extending from the sidewall 122 of the trench 120 toward the source 111 is in a range of 2 nm to 10 nm, and a length of the second extension portion 124 extending from the sidewall 122 of the trench 120 toward the drain 112 is in a range of 2 nm to 10 nm. The depth t2 of the extension portions, i.e., the depth of the first extension portion 123 and the second extension portion 124, ranges from 20 nm to 50 nm. The thickness t3 of the gate oxide layer 130 ranges from 1 nm to 4 nm.

In some embodiments of the present disclosure, the first extension part 123 and the second extension part 124 of the trench 120 are asymmetrically disposed on two sides of the trench 120. Specifically, the depths of the first extension portion 123 and the second extension portion 124 are different, or the extension widths of the depths of the first extension portion 123 and the second extension portion 124 are different. The present disclosure is not so limited.

In the trench array transistor structure provided in the above embodiment of the disclosure, the first extension portion 123 and the second extension portion 124 are formed on the upper portion of the sidewall 122 of the trench 120, the first extension portion 123 is located on a side close to the source 111, and the second extension portion 124 is located on a side close to the drain 112, and the formation of the first extension portion 123 and the second extension portion 124 increases the distance of the gate oxide layer 130 covered on two sides of the upper portion of the trench 120, so as to increase the distance between the source 111 and the drain 112, and effectively improve the problem of easily generating a leakage current.

Fig. 2A is a schematic partial cross-sectional structure diagram of a trench array transistor structure in another embodiment of the present disclosure. Fig. 2B is an enlarged view of a portion D in fig. 2A.

The difference between the trench array transistor structure of fig. 2A and that of fig. 1 is that: the bottom surfaces of the first extension portion 123 and the second extension portion 124 are changed from a horizontal plane to a slant plane, as shown in fig. 2B. The variation of the trench array transistor structure can still increase the distance between the gate oxide layers 130 covered on both sides of the upper portion of the trench 120, thereby increasing the distance between the source 111 and the drain 112, and effectively improving the problem of leakage current.

Fig. 3 is a flowchart of a method for manufacturing a trench array transistor structure according to an embodiment of the disclosure. The following will specifically describe a process flow for manufacturing the trench array transistor structure shown in fig. 1. The preparation method of the trench array transistor structure comprises the following steps.

Step S301, a trench is formed in the substrate base plate having the source region by etching.

In step S302, a first sacrificial oxide layer is formed on the bottom and sidewalls of the trench by a first oxidation.

Step S303, filling the trench with an insulating layer by deposition.

In step S304, the insulating layer is partially removed by etching to expose the first sacrificial oxide layer on the upper portion of the sidewall of the trench.

In step S305, a second sacrificial oxide layer is formed by second oxidation extending on the exposed first sacrificial oxide layer on the upper portion of the sidewall.

Step S306, removing the insulating layer in the groove by etching.

Step S307, removing the first sacrificial oxide layer and the second sacrificial oxide layer in the trench to form a first extension portion and a second extension portion on the upper portion of the sidewall, where the first extension portion is located on the upper portion of the sidewall near the source, and the second extension portion is located on the upper portion of the sidewall near the drain.

In step S308, a gate oxide layer is formed on the bottom, the sidewall, the first extension portion and the second extension portion of the trench by a third oxidation. Referring to fig. 5 to fig. 16, there are schematic partial cross-sectional structures of the trench array transistor structure provided in the embodiment of the present disclosure at various steps in the manufacturing process. A detailed process of preparing the trench array transistor structure will be given below.

In step S301, referring to fig. 5, a trench 120 is etched in the substrate 100 by using the mask layer 510, the trench 120 penetrates through the active region 520, and the trench 120 includes a bottom 121 and two opposite sidewalls 122. Specifically, the substrate base 100 may be etched using at least one of a dry etching process or a wet etching process. The shape of the trench 120 is, for example, but not limited to, a U shape, the opening width d1 of the trench 120 ranges from 30 nm to 80 nm, and the depth d2 of the trench 120 ranges from 100 nm to 200 nm.

In some embodiments of the present disclosure, the material of the mask layer 510 is, for example, but not limited to, nitride. The material of the substrate 100 may be a single crystal or polycrystalline semiconductor material, for example, the substrate 100 is a single crystal silicon substrate or a polycrystalline silicon substrate, or a lightly doped silicon substrate. The material of the substrate 100 is not limited as long as the requirement of the device performance is satisfied.

In some embodiments of the present disclosure, the number of trenches 120 may be set according to the actual requirements of the device. The cross-sectional shape of the trench 120 may also be rectangular, inverted trapezoidal, or the like.

In step S302, referring to fig. 6, a first sacrificial oxide layer 610 is formed on the bottom 121 and the sidewall 122 of the trench 120 by first oxidizing. Specifically, the wall of the trench 120 may be oxidized by one of a dry oxidation process and a wet oxidation process to form a first sacrificial oxide layer covering the bottom 121 and the sidewall 122 of the trench 120. In the preparation process of the dry oxygen oxidation process, hot oxygen flow is injected into the groove 120, the temperature range of the oxygen is between 800 ℃ and 1000 ℃, and an oxide layer with uniform thickness and few defects can be prepared. In the wet oxygen oxidation process, a water vapor process is adopted for preparation, and a large amount of gas-phase active free radicals are generated in the preparation process and participate in the oxidation of silicon, so that an oxide layer with uniform thickness and few defects is obtained. The main component of the first sacrificial oxide layer 610 is silicon oxide, and the thickness d3 of the first sacrificial oxide layer 610 ranges from 1 nm to 4 nm.

In step S303, an insulating layer 710 is filled in the trench 120 by deposition with reference to fig. 7; specifically, the insulating layer 710 may be filled in the trench 120 by chemical vapor deposition. The material of the insulating layer 710 may be any suitable insulating material, such as an insulating oxide, nitride, oxynitride, or the like. However, if the material of the insulating layer 710 is the same as the material of the mask layer 510, for example, nitride, the mask layer 510 on the substrate 100 in step S302 does not need to be processed, and step S303 can be performed directly. If the material of the insulating layer 710 is different from that of the mask layer 510, the mask layer 510 in step S302 may be etched away by a dry etching process or a wet etching process, and then step S303 is performed. The trench 120 will be completely filled with the insulating layer 710.

In step S304, a part of the insulating layer 710 formed in step S303 is etched away with reference to fig. 8. A dry etching process or a wet etching process may be employed. The center line of the removed region of the insulating layer 710 coincides with the center line of the trench 120, i.e., the insulating layer 710 is etched to expose the first sacrificial oxide layer 610 on the upper portion of the sidewall of the trench 120. The depth d4 of the removal of the insulating layer 710 within the trench 120 ranges from 20 nm to 50 nm.

Fig. 4 is a flowchart of a method for partially removing an insulating layer according to an embodiment of the disclosure.

Referring to fig. 4, the detailed steps of etching a portion of the insulating layer 710 are as follows.

In step S401, a photoresist layer is formed on the surface of the insulating layer 710.

In step S402, exposure is performed through a corresponding mask plate, and a pattern of the mask plate is transferred onto the photoresist layer.

In step S403, the photoresist layer is exposed to the region to be removed by development.

In step S404, a removal region is formed in the insulating layer by etching. Specifically, the insulating layer 710 may be etched by a dry etching process, and during the preparation process, an etching gas such as sulfur hexafluoride gas is used, and the etching depth of the insulating layer 710 is controlled by adjusting the flow rate and the etching time of the etching gas.

In step S405, the photoresist layer is removed to form the structure shown in fig. 8.

The etching method for the insulating layer provided in the above embodiment can control the etching depth of the insulating layer 710.

In step S305, referring to fig. 9, a second oxidation process is performed to oxidize the wall of the trench 120 by using one of a dry oxidation process and a wet oxidation process, so as to form a second sacrificial oxide layer 910 extending on the first sacrificial oxide layer 610 in two directions close to the drain and the drain. The thickness d5 of the second sacrificial oxide layer 910 ranges from 2 nm to 10 nm.

In step S306, referring to fig. 10, the insulating layer 710 in the trench 120 is etched to expose the first sacrificial oxide layer 610 on the wall surface of the trench 120. A dry etching process or a wet etching process may be employed.

In step S307, referring to fig. 11, the first sacrificial oxide layer 610 and the second sacrificial oxide layer 910 in the trench 120 are removed, and a dry etching process or a wet etching process may be used to form the second extension portion 124 on the upper portion of the sidewall of the trench 120 near the drain 112 and the first extension portion 123 on the side near the source 111. That is, the trench 120 is composed of a bottom 121, a sidewall 122, a first extension 123 and a second extension 124. At this time, the first opening width d6 of the trench 120 after forming the extension portion, i.e., the opening widths of the sidewalls of the trench 120 corresponding to the first extension portion 123 and the second extension portion 124, are the opening width d1 of the trench 120 in step S301 plus the thicknesses d3 of the two first sacrificial oxide layers 610 and the thicknesses d5 of the two second sacrificial oxide layers 510, and the second opening width d7 of the trench 120 after forming the extension portion, i.e., the opening widths of the trench 120 under the two extension portions, is the opening width d1 of the trench 120 in step S301 plus the thicknesses d3 of the two first sacrificial oxide layers 610. The extension width t1 of the extension portion is formed, that is, the length of the first extension portion 123 extending from the sidewall of the trench 120 to the source 111 is in a range of 2 nm to 10 nm, and the length of the second extension portion 124 extending from the sidewall of the trench 120 to the drain 112 is in a range of 2 nm to 10 nm. Here, the extension width t1 of the first extension 123 or the second extension 124 is the same as the thickness d5 of the second sacrificial oxide layer 510. The depth t2 of the first extension 123 ranges from 20 nm to 50 nm, and the depth t2 of the second extension 124 ranges from 20 nm to 50 nm.

In step S508, referring to fig. 12, a third oxidation process is performed to oxidize the wall of the trench 120 by using one of a dry oxidation process and a wet oxidation process, so as to form a gate oxide layer 130 on the bottom 121, the sidewall 122, the first extension 123 and the second extension 124 of the trench 120. The thickness t3 of the gate oxide layer 130 ranges from 1 nm to 4 nm.

In some embodiments of the present disclosure, the first oxidation, the second oxidation and the third oxidation may adopt one of a dry oxygen oxidation process or a wet oxygen oxidation process, and the processes adopted in the three oxidation processes may be the same or different, in other words, the three oxidation processes have no influence on each other.

In the above embodiments of the present disclosure, the first extension 123 and the second extension 124 of the trench 120 increase the distance between the gate oxide layers 130 on two sides of the upper portion of the trench 120, so as to effectively improve the problem that the trench array transistor is prone to generate leakage current.

As shown in fig. 13, the insulating layer 710 on the substrate 100 is removed, and the insulating layer 710 on the substrate 100 may be removed by chemical-mechanical planarization (CMP).

As shown in fig. 14, a conductive layer 140 is formed by deposition on the gate oxide layer 130, the conductive layer 140 is located in the trench 120, and the top surface of the conductive layer 140 is flush with the bottom end of the gate oxide layer 130. Specifically, the material of the conductive layer 140 is a conductive material containing metal, such as titanium nitride, gold tungsten, and can be prepared by electroplating, chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

As shown in fig. 15, a filling insulating layer 150 is formed over the conductive layer 140 within the trench 120. Specifically, the material of the filling insulating layer 150 may be selected from suitable insulating materials, such as insulating oxide, nitride, oxynitride, and the like. The filling insulation layer 150 may be formed by using a suitable preparation process such as chemical deposition. The top surface of the formed filled insulating layer is kept flush with the top of the substrate base plate 100.

As shown in fig. 16, the trench array transistor structure provided in the embodiment of fig. 1 is formed. Specifically, a source 111 and a drain 112 are formed in the substrate 100 at two sides of the trench 120, wherein the drain 112 is located at one side of the trench 120 close to the second extension 124, and the source 111 is located at the other side of the trench 120 far from the drain 112 close to the first extension 123. Specifically, the active region is doped by an ion implantation process, for example, N-type conductive impurities are doped, so as to obtain the source 111 and the drain 112. P-type conductive impurities may also be doped herein, and the disclosure is not limited thereto.

The embodiment shown in fig. 2 provides a method for manufacturing a trench array transistor structure, which is different from the above-mentioned method: the conditions of the oxidation process for forming the second sacrificial oxide layer are different, and the shapes of the first extension portion 123 and the second extension portion 124 formed finally are slightly different. And will not be described in detail herein.

In addition, other methods may be employed by those skilled in the art to form the trench array transistor structure provided by the embodiments of the present disclosure, and still fall within the scope of the present disclosure.

In summary, in the trench array transistor structure provided in the above embodiments of the disclosure, the first extension portion 123 and the second extension portion 124 are formed on the upper portion of the sidewall 122 of the trench 120, and the formation of the first extension portion 123 and the second extension portion 124 increases the distance between the gate oxide layer 130 covered on both sides of the upper portion of the trench 120, so as to effectively improve the problem that the trench array transistor is prone to generate leakage current.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. The present disclosure is not limited to the precise structures that have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (10)

1. A trench array transistor structure, comprising:

the substrate base plate is provided with an active region, wherein a source electrode and a drain electrode are arranged in the active region;

the groove is positioned in the substrate and penetrates through the active region, and comprises a bottom, a side wall, a first extension part and a second extension part, wherein the first extension part is positioned on one side, close to the source electrode, of the upper part of the side wall, and the second extension part is positioned on one side, close to the drain electrode, of the upper part of the side wall;

a gate oxide layer covering the bottom, the sidewall, the first extension and the second extension of the trench.

2. The trench array transistor structure of claim 1, further comprising:

the conducting layer is positioned in the groove, and the top surface of the conducting layer is flush with the bottom end of the grid oxide layer in the extension part;

and the filling insulating layer is positioned above the conductive layer in the groove.

3. The trench array transistor structure of claim 1, wherein the first extension extends from a sidewall of the trench to the source direction by a length of 2 nm to 10 nm; the length of the second extension part extending from the side wall of the groove to the drain electrode direction is 2-10 nanometers.

4. The trench array transistor structure of claim 1, wherein the first and second extensions have a depth of 20 nm to 50 nm.

5. The trench array transistor structure of claim 1, wherein the gate oxide layer has a thickness of 1 nm to 4 nm.

6. The trench array transistor structure of claim 1, wherein the trench is U-shaped, rectangular, inverted trapezoidal in shape.

7. The trench array transistor structure of claim 1, wherein the first extension and the second extension are asymmetrically disposed on two sides of the trench.

8. The trench array transistor structure of claim 1, wherein the trench has a depth of 100 nm to 200 nm.

9. The trench array transistor structure of claim 1, wherein a bottom surface of the first extension and the second extension is a horizontal surface.

10. The trench array transistor structure of claim 1, wherein bottom surfaces of the first and second extensions are sloped.