CN111987099A - Mask pattern forming method, mask pattern and semiconductor device - Google Patents
Mask pattern forming method, mask pattern and semiconductor device Download PDFInfo
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- CN111987099A CN111987099A CN201910435130.0A CN201910435130A CN111987099A CN 111987099 A CN111987099 A CN 111987099A CN 201910435130 A CN201910435130 A CN 201910435130A CN 111987099 A CN111987099 A CN 111987099A
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- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/80—Etching
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Abstract
The invention discloses a method for forming a mask pattern, which comprises the following steps: forming a plurality of first mandrel patterns, and forming first primary side walls on two sides of the first mandrel patterns; and the first primary side wall is not etched. Compared with the method for artificially increasing the spacing distance of different SRAM units in the prior art, the method for forming the first primary side wall between at least two adjacent first mandrel patterns can control the space occupied by the first storage unit in the side wall thickness direction. The problems that the first storage unit and the second storage unit occupy different spaces in the thickness direction of the side wall, so that the uniformity of a semiconductor device is poor and the performance is poor are solved. The uniformity of the semiconductor device is increased, and the quality of the semiconductor device is improved. The invention also provides a mask pattern with better performance and a semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for forming a mask pattern, and a semiconductor device.
Background
Static Random-Access Memory (SRAM) is a type of Random Access Memory, and data stored in the SRAM can be constantly maintained as long as the SRAM is powered on. In addition, because of the characteristics of high running speed, low power consumption and compatibility with standard processes, the SRAM is widely applied to the fields of electronic products, communication and the like. With the continuous development of semiconductor process technology, the integration level of the SRAM is continuously improved, and the size of the transistor in the SRAM is also continuously reduced, so that the transistor is easy to generate a short channel effect, and the performance of the SRAM is finally affected.
In a fin-type field effect transistor (FinFET), a gate can control a fin from both sides, so that the gate has a strong control capability on a trench and can suppress a short channel effect. Therefore, the SRAM formed by the fin field effect transistors can improve the performance of the SRAM.
A Static Random-Access Memory (SRAM) includes a plurality of SRAM cells arranged in an array, each cell requiring four to six transistors and other components. In actual operation, a plurality of devices with different transistor numbers are integrated on a circuit board, for example, a memory cell with a twelve-transistor (12T) structure and a memory cell with a six-transistor (6T) structure are integrated.
Current integrated circuit design and fabrication processes often work in division, for example, with SRAM and drain side Select Transistor (STD) designed separately, even within the SRAM. Eventually, however, the cells (cells) of these designs need to be connected to integrate the individual devices together.
As shown in fig. 1 and 2, the space occupied by the single or multiple 6T memory cells in the thickness direction of the sidewall is different from the space occupied by the single or multiple 12T memory cells in the thickness direction of the sidewall. Therefore, in the process of connecting the cells, the mandrel patterns of the 6T memory cell and the 12T memory cell may be uneven in thickness, and the mandrel patterns of the 6T memory cell and the 12T memory cell may not be aligned. As shown in fig. 1, in the prior art, the separation distance between the 6T memory cell and the 12T memory cell is usually artificially increased, but this increases the volume of the whole integrated circuit and degrades the performance of the semiconductor device. Further, as shown in fig. 2, when the internal spacing of the memory cell of 12T is small, the distance between the mandrel patterns is too close, and a problem occurs in that a self-aligned multi-pattern cannot be formed, which also degrades the performance of the semiconductor device.
Disclosure of Invention
The invention aims to solve the problem that the performance of a semiconductor device is poor in the prior art. The invention provides a method for forming a mask pattern, and the mask pattern and a semiconductor device prepared by the method, which can improve the quality of the semiconductor device.
In order to solve the above technical problem, an embodiment of the present invention discloses a method for forming a mask pattern, including: forming a plurality of first mandrel patterns; forming first primary side walls on two sides of the first mandrel pattern; s1 is more than or equal to S2/2, wherein S1 is the thickness of the adjacent first primary side wall between at least two adjacent first mandrel patterns, and S2 is the distance between the adjacent side walls of at least two adjacent first mandrel patterns; or S3 < S4, wherein S3 is a distance between adjacent first primary side walls between at least two adjacent first mandrel patterns, and S4 is an etching size of the first primary side walls.
According to another specific embodiment of the present invention, the method for forming a mask pattern according to the embodiment of the present invention further includes forming a plurality of second mandrel patterns; and forming second primary side walls on two sides of the second mandrel patterns, wherein the distance between the second primary side walls between every two adjacent second mandrel patterns is larger than or equal to the etching size of the second primary side walls.
According to another embodiment of the present invention, in the method for forming a mask pattern disclosed in the embodiment of the present invention, a first secondary sidewall is formed on a side, away from each other, of adjacent first primary sidewalls between at least two adjacent first mandrel patterns; first secondary side walls are formed on two sides of the rest first primary side walls, and the distance between every two adjacent first primary side walls is larger than or equal to the etching size of the first secondary side walls; second secondary side walls are formed on two sides of the second primary side walls, and the distance between every two adjacent second secondary side walls is larger than or equal to the etching size of the second secondary side walls.
According to another specific embodiment of the present invention, in the method for forming a mask pattern disclosed in the embodiments of the present invention, first tertiary spacers are formed on both sides of the first secondary spacers, and the distance between the first tertiary spacers between adjacent first secondary spacers is greater than or equal to the etchable size of the first tertiary spacers; and forming second third-stage side walls on two sides of the second-stage side walls, wherein the distance between every two adjacent second-stage side walls is larger than or equal to the etching size of the second third-stage side walls.
According to another embodiment of the present invention, an embodiment of the present invention discloses a method for forming a mask pattern, the first mandrel pattern is used for forming a first memory cell; the second mandrel patterns are used for forming second storage units, and when the first storage units and the second storage units occupy the same space in the thickness direction of the side wall, the distance between at least two adjacent first mandrel patterns is smaller than the distance between two adjacent second mandrel patterns corresponding to the first mandrel patterns.
According to another embodiment of the present invention, a method for forming a mask pattern is disclosed, wherein the first memory cell has a six-transistor structure and the second memory cell has a twelve-transistor structure.
According to another embodiment of the present invention, in the method for forming a mask pattern disclosed in the embodiments of the present invention, when the first mandrel pattern and the second mandrel pattern are both provided as two, the first memory cell includes six first secondary side walls, and the second memory cell includes eight second secondary side walls.
The embodiment of the invention also discloses a mask pattern, which comprises a plurality of first mandrel patterns and first primary side walls formed on two sides of the first mandrel patterns; s1 is more than or equal to S2/2, wherein S1 is the thickness of the adjacent first primary side wall between at least two adjacent first mandrel patterns, and S2 is the distance between the adjacent side walls of at least two adjacent first mandrel patterns; or S3 < S4, wherein S3 is a distance between adjacent first primary side walls between at least two adjacent first mandrel patterns, and S4 is an etching size of the first primary side walls.
According to another specific embodiment of the present invention, in the mask pattern disclosed in the embodiments of the present invention, the mask pattern further includes a plurality of second mandrel patterns and second primary side walls formed on two sides of the second mandrel patterns, wherein a distance between the second primary side walls between adjacent second mandrel patterns is greater than or equal to an etchable size of the second primary side walls.
According to the mask pattern formed by the scheme, the first primary side walls are formed on the two sides of the first mandrel pattern, the two adjacent first primary side walls between the at least two adjacent first mandrel patterns are in mutual contact or the distance between the two adjacent first primary side walls is smaller than the etchable size of the first primary side walls, so that when the two secondary side walls are further formed on the two sides of the first primary side walls, the two secondary side walls cannot be formed between the adjacent first primary side walls with the mutual contact or the distance smaller than the etchable size, the number of the secondary side walls can be effectively reduced, and the purpose of compressing the whole area of the mask pattern is achieved. The forming method of the mask pattern can be used for forming masks when unit cells of storage units of different specifications are connected, the area of the mask pattern formed by compression can be reduced, when the unit cells of the storage units of different specifications are connected, the mandrel patterns of the storage units of different specifications can be aligned as much as possible, the control of the space occupied by the storage units in the thickness direction of the side wall can be realized, the problem that different storage units occupy different spaces in the thickness direction of the side wall is solved, the problems that the uniformity of a semiconductor device is poor and the performance is poor are solved, the uniformity of the semiconductor device is improved, and the performance of the semiconductor device is improved.
The embodiment of the invention also discloses a semiconductor device which comprises a substrate, wherein one side of the substrate is provided with the mask pattern.
According to the semiconductor device formed by the technical scheme, the first primary side walls are formed on the two sides of the first mandrel pattern, the two adjacent first primary side walls between the at least two adjacent first mandrel patterns are in mutual contact or the distance between the two adjacent first primary side walls is smaller than the etchable size of the first primary side walls, so that when the two sides of the first primary side walls are further formed into the secondary side walls, the secondary side walls cannot be formed between the adjacent first primary side walls with the mutual contact or the distance smaller than the etchable size, the number of the secondary side walls can be effectively reduced, and the purpose of compressing the whole area of the mask pattern is achieved. The forming method of the mask pattern can be used for forming masks when unit cells of storage units of different specifications are connected, the area of the mask pattern formed by compression can be reduced, when the unit cells of the storage units of different specifications are connected, the mandrel patterns of the storage units of different specifications can be aligned as much as possible, the control of the space occupied by the storage units in the thickness direction of the side wall can be realized, the problem that different storage units occupy different spaces in the thickness direction of the side wall is solved, the problems that the uniformity of a semiconductor device is poor and the performance is poor are solved, the uniformity of the semiconductor device is improved, and the performance of the semiconductor device is improved.
Drawings
Fig. 1 and fig. 2 are schematic structural diagrams of a memory cell provided in the background of the invention;
FIG. 3 is a flowchart of a method for forming a mask pattern according to an embodiment of the present invention;
FIGS. 4 and 5 are schematic diagrams of a process flow for forming a memory cell according to an embodiment of the invention;
fig. 6 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
Reference numerals:
1. a first storage unit; 11. a first mandrel pattern; 12. a first primary side wall; 13. a first secondary side wall; 14. a first tertiary side wall; 2. a second storage unit; 21. a second mandrel pattern; 22. a second primary side wall; 23. a second secondary side wall; 24. a second third-level side wall; 3. a six transistor (6T) configuration; 4. a twelve transistor (12T) structure.
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure. While the invention will be described in conjunction with the preferred embodiments, it is not intended that features of the invention be limited to these embodiments. On the contrary, the invention is described in connection with the embodiments for the purpose of covering alternatives or modifications that may be extended based on the claims of the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The invention may be practiced without these particulars. Moreover, some of the specific details have been left out of the description in order to avoid obscuring or obscuring the focus of the present invention. It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
It should be noted that in this specification, like reference numerals and letters refer to like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings.
In the description of the present embodiment, it should be noted that the terms "upper", "lower", "inner", "bottom", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that are conventionally placed when the products of the present invention are used, and are only used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements indicated must have specific orientations, be configured in specific orientations, and operate, and thus, should not be construed as limiting the present invention.
The terms "first," "second," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
In the description of the present embodiment, it should be further noted that, unless explicitly stated or limited otherwise, the terms "disposed," "connected," and "connected" are to be interpreted broadly, e.g., as a fixed connection, a detachable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present embodiment can be understood in specific cases by those of ordinary skill in the art.
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Example 1:
in order to solve the problem of poor performance of a semiconductor device in the prior art, the present embodiment provides a method for forming a mask pattern, and specifically, please refer to fig. 1. The method for forming the mask pattern provided by the embodiment specifically includes the following steps:
step S1: a number of first mandrel patterns are formed.
Specifically, the number of the mandrel patterns is not specifically limited in this embodiment, and may be one, two, or even more. The method of forming the mandrel pattern includes, but is not limited to, the following steps:
firstly, an intermediate layer, a mask layer and a first mandrel material layer are sequentially formed on one side of a substrate.
It is noted that the material of the substrate includes, but is not limited to, silicon-on-insulator, germanium-on-insulator, etc.; the intermediate layer can be a wiring layer, an interlayer dielectric layer, a gate material layer, a mask layer or the like of an interconnection structure formed on the substrate, and the intermediate layer can be arranged or removed; the material of the mask layer includes, but is not limited to, oxide, silicon nitride, boron nitride, and the like.
It should be further noted that the material of the first mandrel material layer includes, but is not limited to, nitride, and those skilled in the art can select the material according to practical situations as long as the material is easy to form and remove, and this embodiment is not particularly limited thereto. The method for depositing each layer includes, but is not limited to, atomic layer deposition and chemical vapor deposition, and this embodiment is not limited thereto.
Then, the first mandrel material layer is patterned through a process of photolithography and etching to form a first mandrel pattern.
Specifically, a photoresist pattern may be coated on the first mandrel material layer, and then the photoresist pattern is used as a mask to etch the first mandrel material layer, so as to form a plurality of first mandrel patterns, and then the photoresist pattern is removed.
It is to be understood that the shape and size of the first mandrel patterns may be the same.
Step S2: forming first primary side walls on two sides of the first mandrel pattern; s1 is more than or equal to S2/2, wherein S1 is the thickness of the adjacent first primary side wall between at least two adjacent first mandrel patterns, and S2 is the distance between the adjacent side walls of at least two adjacent first mandrel patterns; or S3 < S4, wherein S3 is a distance between adjacent first primary side walls between at least two adjacent first mandrel patterns, and S4 is an etching size of the first primary side walls.
Specifically, the material of the first primary side wall includes, but is not limited to, amorphous silicon, and the first primary side wall may adopt a chemical vapor deposition method, an atomic layer deposition method, molecular beam epitaxy, or the like. More specifically, the size and shape of the first primary side wall may be set arbitrarily.
And at least the first primary side wall between two adjacent first mandrel patterns cannot be etched in the subsequent etching process. The method for forming the first primary side wall which cannot be etched comprises the following two methods:
the first method comprises the following steps: the thickness of the adjacent first primary side wall between the two adjacent first mandrel patterns is larger than or equal to half of the distance between the adjacent side walls of the two adjacent first mandrel patterns. That is to say, two adjacent first primary side walls of two adjacent first mandrel patterns are in contact with each other or partially overlap with each other, that is, the two first primary side walls jointly form the first primary side wall between the two adjacent first mandrel patterns.
And the second method comprises the following steps: two adjacent first primary side walls of two adjacent first mandrel patterns may not be in contact. However, it is only required to satisfy that the distance between the adjacent first primary side walls between two adjacent first mandrel patterns is smaller than the etchable size. The etchable size is a preset threshold value, and can be obtained by experimental measurement or empirical calculation by a person in the art, that is, when the distance between the two first primary side walls is smaller than the etchable size, the two first primary side walls are etched in the subsequent etching, and when the distance between the two first primary side walls is larger than the etchable size, the two first primary side walls are etched in the subsequent etching, so that the distance between the two first primary side walls is increased.
It should be noted that, on a semiconductor device, the number of the first mandrel patterns may be more than two, and in order to adjust the pitch, sometimes two adjacent first primary side walls need to be etched, while three adjacent first primary side walls remain, or other situations, so that a person skilled in the art needs to determine how to set the distance between two adjacent first primary side walls of two adjacent first mandrel patterns according to actual situations.
Further, the method for forming a mask pattern provided in this embodiment further includes: forming a plurality of second mandrel patterns; and forming second primary side walls on two sides of the second mandrel patterns, wherein the distance between the second primary side walls between every two adjacent second mandrel patterns is larger than or equal to the etching size of the second primary side walls.
Specifically, the forming method, material, shape, etc. of the second mandrel pattern are the same as or similar to those of the first mandrel pattern, and are not described herein again. More specifically, the material, deposition method, shape, etc. of the second primary sidewall are the same as or similar to those of the first primary sidewall, and are not described herein again.
It should be noted that the distance between the second-level sidewalls between each two adjacent second mandrel patterns is greater than or equal to the etchable size of the second-level sidewalls, that is, when the second-level sidewalls of the second mandrel patterns are etched, the adjacent second-level sidewalls are etched.
Further, the method for forming a mask pattern provided in this embodiment further includes: forming first secondary side walls on the sides, far away from each other, of the adjacent first primary side walls between the at least two adjacent first mandrel patterns; and first secondary side walls are formed on two sides of the rest first primary side walls, and the distance between the first secondary side walls and the adjacent first primary side walls is larger than the etching size of the first secondary side walls. That is to say, the first secondary side walls can be further formed on the two sides of the first primary side wall, the distance between two adjacent first secondary side walls between the first primary side walls is larger than the etching size of the first secondary side wall, and the first secondary side walls can be etched in the subsequent etching process. It should be noted that, because the first primary side walls that cannot be etched are formed between at least two adjacent first mandrel patterns, in actual operation, one or more pairs of first primary side walls that cannot be etched may be formed, and the remaining first primary side walls may be etched. At this time, the positions where the first primary side walls are formed are one side of two non-adjacent side walls of the pair of first primary side walls which cannot be etched, and two sides of the other first primary side walls.
Furthermore, second secondary side walls are formed on two sides of the second primary side walls, and the distance between every two adjacent second secondary side walls is larger than or equal to the etching size of the second secondary side walls. That is to say, second secondary side walls may be further formed on two sides of the second primary side wall, and a distance between two second secondary side walls between adjacent second primary side walls is greater than an etching dimension, and in a subsequent etching process, the second secondary side walls may be etched.
Further, the method for forming a mask pattern provided in this embodiment further includes: first tertiary side walls are formed on two sides of the first secondary side walls, and the distance between every two adjacent first tertiary side walls is larger than the etching size of the first tertiary side walls. That is to say, first tertiary side walls can be further formed on two sides of the first secondary side walls, the distance between two adjacent first tertiary side walls between the first secondary side walls is larger than the etching size, and the first tertiary side walls can be etched in the subsequent etching process.
Furthermore, second secondary side walls are formed on two sides of each second secondary side wall, and the distance between every two adjacent second secondary side walls are larger than or equal to the etching size of the second tertiary side walls. That is to say, second third-level side walls can be further formed on two sides of the second-level side walls, the distance between two second third-level side walls between adjacent second-level side walls is larger than the etching size, and in the subsequent etching process, the second third-level side walls can be etched.
It should be understood that the first secondary side wall and the first tertiary side wall may be arranged according to specific situations, and may not be arranged when not needed. The more the side walls, the more mask patterns are generated. The second secondary side wall and the second tertiary side wall can be optionally arranged or not arranged according to requirements.
Further, the first mandrel pattern is used to form a first memory cell and the second mandrel pattern is used to form a second memory cell. Specifically, one first memory cell may include two first mandrel patterns, three first mandrel patterns, or even more; two second mandrel patterns, three second mandrel patterns or even more may also be included in one second memory cell.
Furthermore, when the first storage unit and the second storage unit occupy the same space in the thickness direction of the sidewall, the distance between at least two adjacent first mandrel patterns is smaller than the distance between two adjacent second mandrel patterns corresponding to the first mandrel patterns. That is, in order to make the uniformity of the semiconductor device better, the first memory cell and the second memory cell should have the same size in the thickness direction of the sidewall. However, the number of the first mandrel patterns and the number of the second mandrel patterns included in the first storage unit and the second storage unit may be different, and in order to make the space occupied by the first storage unit and the second storage unit in the thickness direction of the sidewall the same, the distance between at least two adjacent first mandrel patterns in the first storage unit needs to be adjusted, so that the space occupied by the first storage unit and the second storage unit in the thickness direction of the sidewall the same.
Further, the first storage unit is of a six-transistor (6T) structure; the second memory cell is a twelve transistor (12T) structure. It should be understood that the number of the first memory cells and the number of the second memory cells in an integrated circuit may be the same or different.
Furthermore, when the first mandrel pattern and the second mandrel pattern are both provided as two, the first memory unit includes six first secondary side walls, and the second memory unit includes eight second secondary side walls. That is, two adjacent first primary side walls between two first mandrel patterns of the first memory cell cannot be etched, so that only two first secondary side walls can be formed on two sides of the two first primary side walls. For the second storage units, two second-stage side walls can be formed on two sides of each second-stage side wall, so that the number of the second-stage side walls formed by the second storage units is two more than that of the first second-stage side walls formed by the first storage units.
Example 2:
according to the method of forming a mask pattern provided in embodiment 1, this embodiment provides a specific method of forming a mask pattern. Specifically, as shown in fig. 6, the method for forming the mask pattern provided in this embodiment is composed of two first memory cells 1 and one second memory cell 2, where the first memory cell 1 includes two six-transistor (6T) structures 3, and the second memory cell includes one twelve-transistor (12T) structure 4.
First, as shown in fig. 4, a first memory cell 1 is formed.
Specifically, the formation of the first memory cell 1 includes the steps of:
the first step is as follows: two first mandrel patterns 11 are formed, and the method and material for forming the first mandrel patterns 11 have been described in detail in embodiment 1, and are not described in detail in this embodiment. And the first mandrel pattern 11 has a rectangular shape. However, the thickness of the first mandrel pattern 11 is not particularly limited in this embodiment.
The second step is that: first primary side walls 12 that cannot be etched are formed on both sides of the first mandrel pattern 11. The first primary side wall 12 which cannot be etched is formed by the following two methods:
the first method comprises the following steps: the thickness S1 of the adjacent first primary sidewall 12 between the adjacent first mandrel patterns 11 is greater than or equal to half of the distance S2 between the adjacent sidewalls of the adjacent first mandrel patterns 11; namely S1 is not less than S2/2. That is, the adjacent first primary side walls 12 between the adjacent first mandrel patterns 11 are in contact with or partially overlapped, so that the adjacent first primary side walls 12 cannot be etched due to connection together in the subsequent etching process.
And the second method comprises the following steps: the distance S3 between adjacent first primary sidewalls 12 between two adjacent first mandrel patterns 11 is smaller than the etchable dimension S4 of the first primary sidewalls 12, i.e., S3 < S4. That is, although there is no contact between the adjacent first primary side walls 12 between the adjacent first mandrel patterns 11, since the distance between the two first primary side walls 12 is smaller than the fixed threshold, the two adjacent first primary side walls 12 still cannot be etched away in the subsequent etching process. This fixed threshold is the etchable size.
The third step: first secondary side walls 13 are formed on both sides of the first primary side walls 12. Specifically, the forming method and material of the first secondary sidewall 13 have been described in detail in embodiment 1, and are not described in detail in this embodiment. The thickness of the first secondary sidewall 13 is not specifically limited in this embodiment, but should be less than or equal to the thickness of the first primary sidewall 12.
It should be noted that the distance between the first secondary side walls 13 and the adjacent first primary side walls 12 is greater than or equal to the etchable size of the first secondary side walls 13. That is, the distance between the two first secondary side walls 13 between the adjacent first primary side walls 12 is greater than the etchable size of the first secondary side walls 13, so that in the subsequent etching process, because the distance between the first secondary side walls 13 is large, the two adjacent first secondary side walls 13 can be etched.
It should be further noted that in this step, between at least two adjacent first mandrel patterns 11, first secondary side walls 13 are formed on the sides of the adjacent first primary side walls 12 away from each other, and first secondary side walls 13 are formed on the two sides of the remaining first primary side walls 12. That is, if the first secondary side walls 12 between the adjacent first mandrel patterns 11 cannot be etched, the first secondary side walls 13 cannot be formed on the sides of the two first secondary side walls 12 close to each other. Only when the first primary side walls 12 can be etched away, the first secondary side walls 13 can be formed on both sides of the first primary side walls 12.
The fourth step: first tertiary side walls 14 are formed on both sides of the first secondary side walls 13. Specifically, the forming method and material of the first level spacer 14 have been described in detail in embodiment 1, and are not described in detail in this embodiment. The thickness of the first tertiary spacers 14 is not specifically limited in this embodiment, but should be less than or equal to the thickness of the first secondary spacers 13.
It should be noted that the distance between the first tertiary spacers 14 and the adjacent first secondary spacers 13 is greater than or equal to the etchable dimension of the first tertiary spacers 14. That is, the distance between the two first third-level side walls 14 between the adjacent first second-level side walls 13 is greater than the etchable size of the first third-level side walls 14, so that in the subsequent etching process, because the distance between the first third-level side walls 14 is relatively large, the two adjacent first third-level side walls 14 can be etched.
Then, as shown in fig. 5, the second memory cell 2 is formed.
Specifically, the forming of the second memory cell 2 includes the steps of:
the first step is as follows: two second mandrel patterns 21 are formed, and the forming method and material of the second mandrel patterns 21 are described in detail in embodiment 1, and are not described in detail in this embodiment. And the second mandrel pattern 21 is rectangular in shape. However, the thickness of the second mandrel pattern 21 is not particularly limited in this embodiment.
The second step is that: second primary side walls 22 are formed on both sides of the second mandrel pattern 21. Specifically, the forming method and material of the second level sidewall 22 have been described in detail in embodiment 1, and are not described in detail in this embodiment. The thickness of the second primary sidewall 22 is not limited in this embodiment, but should be less than or equal to the thickness of the second mandrel pattern 21.
Note that the distance between the second primary side walls 22 of the adjacent second mandrel patterns 21 is greater than or equal to the etchable size of the second primary side walls 22. That is, the distance between the two second primary side walls 22 between the adjacent second mandrel patterns 21 is greater than the etchable dimension of the second primary side walls 22, so that in the subsequent etching process, because the distance between the second primary side walls 22 is larger, the two adjacent second primary side walls 22 can be etched.
The third step: second secondary side walls 23 are formed on both sides of the second primary side walls 22. Specifically, the forming method and material of the second level sidewall 23 have been described in detail in embodiment 1, and are not described in detail in this embodiment. The thickness of the second secondary sidewall 23 is not specifically limited in this embodiment, but should be less than or equal to the thickness of the second primary sidewall 22.
It should be noted that the distance between the second level spacers 23 between the adjacent second level spacers 22 is greater than or equal to the etchable size of the second level spacers 23. That is, the distance between the two second-level side walls 23 between the adjacent second-level side walls 22 is greater than the etchable size of the second-level side walls 23, so that in the subsequent etching process, because the distance between the second-level side walls 23 is large, the two adjacent second-level side walls 23 can be etched.
The fourth step: and forming second third-level side walls 24 on two sides of the second-level side walls 23. Specifically, the forming method and material of the second level spacer 24 have been described in detail in embodiment 1, and are not described in detail in this embodiment. The thickness of the second third-level sidewall 24 is not specifically limited in this embodiment, but should be less than or equal to the thickness of the second-level sidewall 23.
It should be noted that the distance between the second third-level sidewalls 24 and the adjacent second-level sidewalls 23 is greater than or equal to the etchable size of the second third-level sidewalls 24. That is, the distance between the two second third-level side walls 24 between the adjacent second-level side walls 23 is greater than the etchable size of the second third-level side walls 24, so that in the subsequent etching process, the two adjacent second third-level side walls 24 can be etched due to the larger distance between the second third-level side walls 24.
The first and second third level spacers 14 and 24 formed through the above steps may be used as mask patterns. Since the first primary side walls 12 between two adjacent first mandrel patterns 11 in the first memory cell 1 are not etched, the operations performed on the two first memory cells 1 are equivalent to the formation process of the self-aligned quadruple pattern (SAQP), and in the second memory cell 2, since the second primary side walls 22 between two adjacent second mandrel patterns 21 are etched, the operations performed on the second memory cell 2 are equivalent to the formation of the self-aligned octal pattern (SAOP).
According to the mask pattern formed by the method, the first primary side walls are formed on the two sides of the first mandrel pattern, and the two adjacent first primary side walls between the at least two adjacent first mandrel patterns are in mutual contact or the distance between the two adjacent first primary side walls is smaller than the etchable size of the first primary side walls, so that when the two secondary side walls are further formed on the two sides of the first primary side walls, the two secondary side walls cannot be formed between the adjacent first primary side walls with the mutual contact or the distance smaller than the etchable size, the number of the secondary side walls can be effectively reduced, and the purpose of compressing the whole area of the mask pattern is achieved. The forming method of the mask pattern can be used for forming masks when unit cells of storage units of different specifications are connected, the area of the mask pattern formed by compression can be reduced, when the unit cells of the storage units of different specifications are connected, the mandrel patterns of the storage units of different specifications can be aligned as much as possible, the control of the space occupied by the storage units in the thickness direction of the side wall can be realized, the problem that different storage units occupy different spaces in the thickness direction of the side wall is solved, the problems that the uniformity of a semiconductor device is poor and the performance is poor are solved, the uniformity of the semiconductor device is improved, and the performance of the semiconductor device is improved.
Example 3:
this embodiment provides a mask pattern according to the methods of forming the mask pattern provided in embodiments 1 and 2. Specifically, please refer to fig. 6. The mask pattern provided by the embodiment includes:
a plurality of first mandrel patterns 11, and first primary sidewalls 12 formed at both sides of the first mandrel patterns 11. Specifically, the materials, shapes, and forming methods of the first mandrel pattern 11 and the first primary sidewall 12 are described in embodiment 1, and are not described in detail in this embodiment. The thickness S1 of the adjacent first primary sidewall 12 between the adjacent first mandrel patterns 11 is greater than or equal to half of the distance S2 between the adjacent sidewalls of the adjacent first mandrel patterns 11; namely S1 is not less than S2/2. Or the distance S3 between adjacent first primary side walls 12 between two adjacent first mandrel patterns 11 is smaller than the etchable dimension S4 of the first primary side walls 12, i.e., S3 < S4.
Further, the mask pattern further includes a plurality of second mandrel patterns 21, and second first-level sidewalls 22 formed on two sides of the second mandrel patterns 21. Specifically, the materials, shapes, and forming methods of the second mandrel pattern 21 and the second primary sidewall 22 are described in embodiment 1, and are not described in detail in this embodiment. And the distance between the second primary side walls 22 between adjacent second mandrel patterns 21 is greater than or equal to the etchable size of the second primary side walls 22. That is, the distance between the two second primary side walls 22 between the adjacent second mandrel patterns 21 is greater than the etchable dimension of the second primary side walls 22, so that in the subsequent etching process, because the distance between the second primary side walls 22 is larger, the two adjacent second primary side walls 22 can be etched.
According to the mask pattern formed by the method, the first primary side walls are formed on the two sides of the first mandrel pattern, and the two adjacent first primary side walls between the at least two adjacent first mandrel patterns are in mutual contact or the distance between the two adjacent first primary side walls is smaller than the etchable size of the first primary side walls, so that when the two secondary side walls are further formed on the two sides of the first primary side walls, the two secondary side walls cannot be formed between the adjacent first primary side walls with the mutual contact or the distance smaller than the etchable size, the number of the secondary side walls can be effectively reduced, and the purpose of compressing the whole area of the mask pattern is achieved. The forming method of the mask pattern can be used for forming masks when unit cells of storage units of different specifications are connected, the area of the mask pattern formed by compression can be reduced, when the unit cells of the storage units of different specifications are connected, the mandrel patterns of the storage units of different specifications can be aligned as much as possible, the control of the space occupied by the storage units in the thickness direction of the side wall can be realized, the problem that different storage units occupy different spaces in the thickness direction of the side wall is solved, the problems that the uniformity of a semiconductor device is poor and the performance is poor are solved, the uniformity of the semiconductor device is improved, and the performance of the semiconductor device is improved.
Example 4:
this embodiment provides a semiconductor device according to the mask pattern forming methods and mask patterns provided in embodiments 1, 2, and 3.
The semiconductor device provided by the embodiment comprises a substrate, wherein a mask pattern is formed on one side of the substrate. The mask pattern is the mask pattern described above, namely: the first core pattern structure includes a plurality of first core patterns 11, and first primary side walls 12 formed on both sides of the first core patterns 11. The thickness S1 of the adjacent first primary sidewall 12 between the adjacent first mandrel patterns 11 is greater than or equal to half of the distance S2 between the adjacent sidewalls of the adjacent first mandrel patterns 11; namely S1 is not less than S2/2. Or the distance S3 between adjacent first primary side walls 12 between two adjacent first mandrel patterns 11 is smaller than the etchable dimension S4 of the first primary side walls 12, i.e., S3 < S4.
Further comprising: a plurality of second mandrel patterns 21, and second primary side walls 22 formed on both sides of the second mandrel patterns 21. And the distance between the second primary side walls 22 between adjacent second mandrel patterns 21 is greater than or equal to the etchable size of the second primary side walls 22.
According to the semiconductor device formed by the method, the first primary side walls are formed on the two sides of the first mandrel pattern, and the two adjacent first primary side walls between the at least two adjacent first mandrel patterns are in mutual contact or the distance between the two adjacent first primary side walls is smaller than the etchable size of the first primary side walls, so that when the two secondary side walls are further formed on the two sides of the first primary side walls, the two secondary side walls cannot be formed between the adjacent first primary side walls with the mutual contact or the distance smaller than the etchable size, the number of the secondary side walls can be effectively reduced, and the purpose of compressing the whole area of the mask pattern is achieved. The forming method of the mask pattern can be used for forming masks when unit cells of storage units of different specifications are connected, the area of the mask pattern formed by compression can be reduced, when the unit cells of the storage units of different specifications are connected, the mandrel patterns of the storage units of different specifications can be aligned as much as possible, the control of the space occupied by the storage units in the thickness direction of the side wall can be realized, the problem that different storage units occupy different spaces in the thickness direction of the side wall is solved, the problems that the uniformity of a semiconductor device is poor and the performance is poor are solved, the uniformity of the semiconductor device is improved, and the performance of the semiconductor device is improved.
In order to solve the problem of poor performance of a semiconductor device in the prior art, the invention provides a method for forming a mask pattern, which comprises the following steps: forming a plurality of first mandrel patterns; forming first primary side walls on two sides of the first mandrel pattern; s1 is more than or equal to S2/2, wherein S1 is the thickness of the adjacent first primary side wall between at least two adjacent first mandrel patterns, and S2 is the distance between the adjacent side walls of at least two adjacent first mandrel patterns; or S3 < S4, wherein S3 is a distance between adjacent first primary side walls between at least two adjacent first mandrel patterns, and S4 is an etching size of the first primary side walls.
According to another specific embodiment of the present invention, the method for forming a mask pattern according to the embodiment of the present invention further includes forming a plurality of second mandrel patterns; and forming second primary side walls on two sides of the second mandrel patterns, wherein the distance between the second primary side walls between every two adjacent second mandrel patterns is larger than or equal to the etching size of the second primary side walls.
According to another embodiment of the present invention, in the method for forming a mask pattern disclosed in the embodiment of the present invention, a first secondary sidewall is formed on a side, away from each other, of adjacent first primary sidewalls between at least two adjacent first mandrel patterns; first secondary side walls are formed on two sides of the rest first primary side walls, and the distance between every two adjacent first primary side walls is larger than or equal to the etching size of the first secondary side walls; second secondary side walls are formed on two sides of the second primary side walls, and the distance between every two adjacent second secondary side walls is larger than or equal to the etching size of the second secondary side walls.
According to another specific embodiment of the present invention, in the method for forming a mask pattern disclosed in the embodiments of the present invention, first tertiary spacers are formed on both sides of the first secondary spacers, and the distance between the first tertiary spacers between adjacent first secondary spacers is greater than or equal to the etchable size of the first tertiary spacers; and forming second third-stage side walls on two sides of the second-stage side walls, wherein the distance between every two adjacent second-stage side walls is larger than or equal to the etching size of the second third-stage side walls.
According to another embodiment of the present invention, an embodiment of the present invention discloses a method for forming a mask pattern, the first mandrel pattern is used for forming a first memory cell; the second mandrel patterns are used for forming second storage units, and when the first storage units and the second storage units occupy the same space in the thickness direction of the side wall, the distance between at least two adjacent first mandrel patterns is smaller than the distance between two adjacent second mandrel patterns corresponding to the first mandrel patterns.
According to another embodiment of the present invention, a method for forming a mask pattern is disclosed, wherein the first memory cell has a six-transistor structure and the second memory cell has a twelve-transistor structure.
According to another embodiment of the present invention, in the method for forming a mask pattern disclosed in the embodiments of the present invention, when the first mandrel pattern and the second mandrel pattern are both provided as two, the first memory cell includes six first secondary side walls, and the second memory cell includes eight second secondary side walls.
The embodiment of the invention also discloses a mask pattern, which comprises a plurality of first mandrel patterns and first primary side walls formed on two sides of the first mandrel patterns; s1 is more than or equal to S2/2, wherein S1 is the thickness of the adjacent first primary side wall between at least two adjacent first mandrel patterns, and S2 is the distance between the adjacent side walls of at least two adjacent first mandrel patterns; or S3 < S4, wherein S3 is a distance between adjacent first primary side walls between at least two adjacent first mandrel patterns, and S4 is an etching size of the first primary side walls.
According to another specific embodiment of the present invention, in the mask pattern disclosed in the embodiments of the present invention, the mask pattern further includes a plurality of second mandrel patterns and second primary side walls formed on two sides of the second mandrel patterns, wherein a distance between the second primary side walls between adjacent second mandrel patterns is greater than or equal to an etchable size of the second primary side walls.
The embodiment of the invention also discloses a semiconductor device which comprises a substrate, wherein one side of the substrate is provided with the mask pattern.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing is a more detailed description of the invention, taken in conjunction with the specific embodiments thereof, and that no limitation of the invention is intended thereby. Various changes in form and detail, including simple deductions or substitutions, may be made by those skilled in the art without departing from the spirit and scope of the invention.
Claims (10)
1. A method for forming a mask pattern, comprising:
forming a plurality of first mandrel patterns;
forming first primary side walls on two sides of the first mandrel pattern; and is
S1 is more than or equal to S2/2, wherein S1 is the thickness of the adjacent first primary side wall between at least two adjacent first mandrel patterns, and S2 is the distance between the adjacent side walls of the at least two adjacent first mandrel patterns; or
S3 < S4, where S3 is a distance between the adjacent first primary sidewalls between at least two adjacent first mandrel patterns, and S4 is an etching dimension of the first primary sidewalls.
2. The method of forming a mask pattern according to claim 1, further comprising:
forming a plurality of second mandrel patterns;
and forming second primary side walls on two sides of the second mandrel patterns, wherein the distance between the second primary side walls between every two adjacent second mandrel patterns is larger than or equal to the etching size of the second primary side walls.
3. The method for forming a mask pattern according to claim 2, wherein a first secondary sidewall is formed on a side of the first primary sidewall away from each other between the at least two adjacent first mandrel patterns; and is
Forming the first secondary side walls on two sides of the rest first primary side walls, wherein the distance between every two adjacent first primary side walls is larger than or equal to the etching size of the first secondary side walls;
second secondary side walls are formed on two sides of the second primary side walls, and the distance between every two adjacent second secondary side walls is larger than or equal to the etching size of each second secondary side wall.
4. The method for forming a mask pattern according to claim 3, wherein first tertiary spacers are formed on two sides of the first secondary spacers, and a distance between adjacent first tertiary spacers is greater than or equal to an etching dimension of the first tertiary spacers;
Second third-level side walls are formed on two sides of the second-level side walls, and the distance between every two adjacent second-level side walls of the second third-level side walls is larger than or equal to the etching size of the second third-level side walls.
5. The method of forming a mask pattern according to any one of claims 2 to 4, wherein the first mandrel pattern is used to form a first memory cell; the second mandrel patterns are used for forming second storage units, and when the first storage units and the second storage units occupy the same space in the thickness direction of the side wall, the distance between the at least two adjacent first mandrel patterns is smaller than the distance between the two adjacent second mandrel patterns corresponding to the first mandrel patterns.
6. The method as claimed in claim 5, wherein the first memory cell has a six-transistor structure and the second memory cell has a twelve-transistor structure.
7. The method of forming a mask pattern according to claim 6,
when the first mandrel pattern and the second mandrel pattern are both set to be two, the first storage unit comprises six first secondary side walls, and the second storage unit comprises eight second secondary side walls.
8. A mask pattern is characterized by comprising a plurality of first mandrel patterns and first primary side walls formed on two sides of the first mandrel patterns; and is
S1 is more than or equal to S2/2, wherein S1 is the thickness of the adjacent first primary side wall between at least two adjacent first mandrel patterns, and S2 is the distance between the adjacent side walls of the at least two adjacent first mandrel patterns; or
S3 < S4, where S3 is a distance between the adjacent first primary sidewalls between at least two adjacent first mandrel patterns, and S4 is an etching dimension of the first primary sidewalls.
9. The mask pattern of claim 8, further comprising a plurality of second mandrel patterns, and second primary sidewalls formed on two sides of the second mandrel patterns, wherein a distance between the second primary sidewalls between adjacent second mandrel patterns is greater than or equal to an etchable dimension of the second primary sidewalls.
10. A semiconductor device, characterized in that it comprises a substrate, which is provided on one side with a mask pattern according to claim 8 or 9.
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| CN201910435130.0A CN111987099A (en) | 2019-05-23 | 2019-05-23 | Mask pattern forming method, mask pattern and semiconductor device |
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| US20160260606A1 (en) * | 2015-03-02 | 2016-09-08 | Globalfoundries Inc. | Methods of forming a masking pattern and a semiconductor device structure |
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| CN103839781A (en) * | 2012-11-21 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming fine patterns on semiconductor |
| CN104078330A (en) * | 2013-03-28 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | Method for forming self-aligned triple graphs |
| US20160260606A1 (en) * | 2015-03-02 | 2016-09-08 | Globalfoundries Inc. | Methods of forming a masking pattern and a semiconductor device structure |
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