CN111987012A - Semiconductor hybrid etching device and method - Google Patents

Semiconductor hybrid etching device and method Download PDF

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Publication number
CN111987012A
CN111987012A CN201910789238.XA CN201910789238A CN111987012A CN 111987012 A CN111987012 A CN 111987012A CN 201910789238 A CN201910789238 A CN 201910789238A CN 111987012 A CN111987012 A CN 111987012A
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Prior art keywords
etching
wafer
chamber
etch
bevel
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尹镛赫
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Gti Korea Ltd
GTI Corp
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Gti Korea Ltd
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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    • H01L21/67011—Apparatus for manufacture or treatment
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67075—Apparatus for fluid treatment for etching for wet etching
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    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/6719—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers
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    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
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    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
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    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
    • H01L21/67766—Mechanical parts of transfer devices

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Abstract

The semiconductor hybrid etching apparatus of the present invention may include: a platform; a first etching unit disposed inside the stage and having a first etching chamber performing a first etching process on a wafer; a second etching unit disposed inside the stage and having a second etching chamber performing a second etching process on the wafer, the second etching process being different in etching manner from the first etching process; and a wafer transfer tool disposed in a wafer transfer passage formed between the first and second etching units, and transferring the wafer between the first and second etching units through the wafer transfer passage. A cleaning process may be performed on the wafer in one of the first and second etching units.

Description

Semiconductor hybrid etching device and method
Technical Field
The present invention relates to a semiconductor etching apparatus, and more particularly, to a semiconductor hybrid etching apparatus and method, in which a dry etching unit and a wet etching unit are combined in one stage, and a bevel region of a wafer can be etched by using the semiconductor hybrid etching apparatus through an easy and simple process.
Background
Fixed circuit patterns and the like required for a semiconductor manufacturing process such as a deposition process of a thin film, an etching process and the like are integrated on a semiconductor wafer (wafer) to manufacture various integrated circuit elements and the like. Such integrated circuit elements are integrated in a predetermined region of a semiconductor wafer, such as an element forming region. The edge region, other than the element forming region of the semiconductor wafer, is a region for transporting the wafer without additionally forming elements or circuit patterns, and may be referred to as a wafer bevel (level) region. The wafer bevel region is formed to a predetermined width at an edge of the wafer, including an upper surface of the wafer, a bevel surface including a side surface, and a back surface of the wafer.
In a manufacturing process of a semiconductor device, a thin film deposition process is to deposit a desired thin film to a fixed thickness on the entire surface of a wafer, and a thin film etching process is to be performed with a thin film formed in an element forming region of the wafer as a target in order to obtain a desired element pattern. In addition, when the etching process is performed using plasma, process byproducts such as particles are accumulated.
Therefore, if the subsequent process is performed in a state where a thin film, process by-products, or particles are accumulated on the wafer bevel region, a warpage phenomenon occurs to the wafer or wafer alignment becomes difficult due to defocus, and not only the film or process by-products, particles accumulated on the wafer bevel region as such act as defects in the process in the subsequent process, becomes a cause of lowering the yield.
In order to solve this problem, the related art performs a bevel etching process for removing deposits at a bevel region of a wafer, and forms plasma at an edge portion of the wafer to perform the bevel etching process. The deposition accumulated in the bevel region on the upper surface of the wafer can be removed by such a bevel etching process, but the deposition still remains on the back surface of the wafer, so that there still remain problems such as a wafer warpage phenomenon and a yield reduction due to defocusing. In addition, there is a problem that particles are easily generated by removing deposits in the bevel region by a dry etching process using plasma. Further, the conventional bevel etching method has a problem that it is difficult to precisely control particles and contamination on the upper surface and the back surface of the wafer.
Disclosure of Invention
(problem to be solved)
The present invention is directed to a semiconductor hybrid etching apparatus and method in which a dry etching unit and a wet etching unit suitable for an etching process of a bevel region of a wafer are combined in one platform (platform).
The invention aims to provide a semiconductor hybrid etching device for etching a bevel area of a wafer by an easy and simple process.
The invention provides a semiconductor hybrid etching method capable of etching a bevel region of a wafer by an easy and simple process in a semiconductor hybrid etching apparatus combining a dry etching unit and a wet etching unit.
The object of the present invention is to provide a hybrid etching method that can remove deposits formed on the bevel region of a wafer by dry etching and can remove deposits formed on the back surface by wet etching.
The purpose of the present invention is to provide a hybrid etching method comprising: after removing the deposits formed on the bevel region of the wafer by the dry etching process, a cleaning process is performed, which may be performed in situ in the same wet etching unit as the removal process of removing the deposits formed on the backside of the bevel region.
(means for solving the problems)
The semiconductor hybrid etching apparatus of the present invention may include: a platform; a first etching unit disposed inside the stage and having a first etching chamber performing a first etching process on a wafer; a second etching unit disposed inside the stage and having a second etching chamber performing a second etching process on the wafer, the second etching process being different in etching manner from the first etching process; and a wafer transfer tool disposed in a wafer transfer passage formed between the first and second etching units, and transferring the wafer between the first and second etching units through the wafer transfer passage. A cleaning process may be performed on the wafer in one of the first and second etching units.
The semiconductor hybrid etching method of the present invention uses a semiconductor hybrid etching apparatus including a stage, a first etching chamber and a second etching chamber disposed inside the stage, and may include the steps of: performing a first etch process on a front side of a wafer in a first etch chamber; performing a second etch process on the back side of the wafer in a second etch chamber; a cleaning process is performed on the wafer in one of the first and second etch chambers. The second etching process may be performed in an etching method different from the first etching process.
(Effect of the invention)
According to an embodiment of the present invention, an etching apparatus has a dry etching unit and a wet etching unit in one stage, and in the same etching apparatus, a deposition formed on a bevel region may be removed through a dry etching process and a deposition formed on a back surface may be removed through a wet etching process. Accordingly, there is an advantage in that fine control of particles and contamination (e.g., removal of 2mm from the front side of the wafer; complete removal of the side surface; removal of 7 to 10mm from the back side) is facilitated for the edge portion and the back side of the wafer. In addition, the problem that particles are likely to occur when the slope is etched by dry etching can be solved.
Further, in the deposition process for manufacturing the 3D NAND flash memory device, the film is deposited not only on the upper surface but also inside the back surface, resulting in a problem of occurrence of a warpage phenomenon to reduce yield, and thus, not only the problem can be solved by the back surface wet etching process, but also there is an advantage of easy control of back surface particles.
In addition, the bevel cleaning process is performed after the process of removing the deposits formed on the bevel region of the wafer through the dry etching process, and the cleaning process may be performed in situ in the same wet etching unit as the process of removing the deposits formed on the back of the bevel region, and thus the deposits of the bevel region may be easily removed. In addition, the method not only can simplify the process and shorten the process time, but also can improve the yield.
Furthermore, the dry etching process for bevel etching, the wet etching process and the cleaning process for cleaning the bevel are performed in the same etching apparatus, thereby minimizing the atmospheric exposure of the wafer, and further minimizing the exposure to particles and contaminants, thereby improving the yield.
Drawings
Fig. 1 is a cross-sectional view showing a semiconductor hybrid etching apparatus suitable for an etching process of a bevel region of a wafer according to an embodiment of the present invention.
Fig. 2 schematically shows a cross-sectional structure of a wet etching unit in the semiconductor hybrid etching apparatus according to the embodiment of the present invention.
Fig. 3 schematically shows a cross-sectional structure of a dry etching unit in the semiconductor hybrid etching apparatus according to the embodiment of the present invention.
Fig. 4 is a diagram for explaining an etching process of a wafer bevel region using the semiconductor hybrid etching apparatus according to the embodiment of the present invention.
Fig. 5 is a view for explaining an etching process of a wafer bevel region using a semiconductor hybrid etching apparatus according to another embodiment of the present invention.
Description of the reference numerals
100: hybrid etching apparatus 110: platform
200: wafer 215: FOUP
225. 250, 280: wafer conveyance tool 235: buffer piece
260: wet etching unit 265: wet process chamber
270: dry etching unit 275: dry etching chamber
271: load lock chamber 273: transport chamber
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Fig. 1 shows a cross-sectional view of a semiconductor hybrid etching apparatus 100 according to an embodiment of the present invention. The semiconductor hybrid etching apparatus 100 of fig. 1, which combines a wet etching unit and a dry etching unit, is an apparatus that can perform a bevel etching process in one apparatus for removing deposits accumulated in a bevel region of a semiconductor wafer.
Referring to fig. 1, a semiconductor hybrid etching apparatus 100 according to an embodiment of the present invention may include: a platform 110(platform) to which the etching units 260, 270 are to be configured; a controller 120 is disposed outside the stage 110 and controls an etching process of an etching unit disposed in the stage 110, for example, wafer transportation, etc.
The interior of the platform 110 is maintained in a clean environment and is roughly divided into four parts; for example, the system may be divided into an Equipment Front End Module (EFEM) portion 130, a buffer module portion 150, a wet etching unit portion 170, and a dry etching unit portion 190.
The EFEM portion 130 has a transport module 225 therein to function as a transport module for transporting a plurality of wafers (refer to 200 of fig. 2 and 3). The EFEM section 130 may have a load port 210 and a transport module 220. The EFEM part 130 may function to transport a wafer from the outside to a wet etching unit part 170 or a dry etching unit part 190 as a process module part. The inside of the EFEM part 130 forms a clean space to transport the wafer to the wet etching unit part 170 or the dry etching unit part 190 under a clean environment.
A plurality of FOUPs (front opening unified pods) 215 may be loaded as storage containers at the load port 210. The FOUP 215 may be a cassette-type integrated wafer storage container with a front opening, as an example of a sealed wafer storage container for storing semiconductor wafers. The wafer 200 is transported in a lot unit installed in the FOUP 215, and a single wafer 200 can be transported to the wet and dry etching unit parts 170 and 190.
In the embodiment of the present invention, it is illustrated that the wafer 200 is loaded on the loading portion 210 after the FOUP 215 is mounted as a loading container, but it is not necessarily limited thereto, and may be loaded on the loading portion 210 in various ways according to the size of the wafer, etc.
The transport module 220 functions to transport wafers stored in the FOUP 215 of the load port 210 to the etching units 260, 270. A transfer robot 225 may be disposed in the transfer module 220, and the transfer robot 225 is responsible for transferring the wafers to the etching units 260, 270. Although not shown in the drawings, a FOUP opener may be provided at the transport module 220 for opening the FOUP 215 of the load port 210.
The buffer module 230 may be disposed at the buffer module part 150, and the buffer module 230 serves to temporarily store wafers to be process-processed supplied to the etching units 260, 270 (process modules) or wafers processed supplied from the etching units 260, 270. The buffer module 230 may have a plurality of buffers 235. For example, among the FOUPs 215 arranged in the load port 210, the wafers stored in the first and second FOUPs are temporarily stored by being transferred to the first buffer among the buffers 235 of the buffer module 230 by the transfer robot 225, and the wafers stored in the third and fourth FOUPs among the FOUPs 215 can be temporarily stored by being transferred to the second buffer among the buffers 235 by the transfer robot 225.
In addition, in the semiconductor hybrid etching apparatus 100 according to the embodiment of the present invention, a wafer carrying passage 240 for carrying a wafer may be formed in the stage 110 between the buffer module part 150 and the etching unit parts 170 and 190. A Wafer Transfer Robot (WTR) may be disposed in the wafer transfer lane 240 as the wafer transfer tool 250 responsible for transferring the wafer 200 between the buffer 235 and the etching units 260, 270.
The wafer transfer robot 250 disposed in the wafer transfer passage 240 transfers the wafer 200 to be process-processed in the process module units 260 and 270 from the buffer member 235 of the buffer module 230 to the process module units 260 and 270, or supplies the wafer 200 process-processed in the process module units 260 and 270 from the process modules 260 and 270 to the buffer member 235.
A wet etch unit (module) 260 may be disposed in the wet etch unit portion 170. A plurality of process chambers 265 may be arranged in the wet etch unit 260 for a wet etch process. The process chamber 265 provides a space for performing a wet etching process on the wafer 200. Although not shown in the drawings, the wet etching unit 260 may further include: a chemical supply for supplying at least one kind of wet chemical to the wafer 200 in the process chamber 265; a loading device for loading wafers to be process-treated, which are transferred from the buffer 235 by the wafer transfer robot 250, into the process chamber 265; an unloading device for unloading the process-processed wafer 200 from the process chamber 265, and the like.
The wafer 200 temporarily stored in the buffer 235 is transferred to the process chambers 265 by the wafer transfer robot 250, so that the wet etching process can be performed in the process chambers 265. For example, an etching process may be performed on a bevel region of a wafer in the plurality of process chambers 265. Specifically, a wet etching process may be performed on the back side of the wafer in the wafer bevel region or the entire back side of the wafer in the plurality of process chambers 265. Additionally, the wafers may also be subjected to a cleaning process in the plurality of process chambers 265.
A dry etching unit (module) 270 may be disposed in the dry etching unit section 190. The dry etching unit 270 may include a load lock chamber 271, a transfer chamber 273, a plurality of process chambers 275, and the like. After the load lock chamber 271 is loaded with the wafer to be process-processed, which is transferred from the buffer 235 by the wafer transfer robot 250, the inside of the load lock chamber 271 may be brought into a vacuum state.
A wafer transfer robot 280 may be disposed in the transfer chamber 273, and the wafer transfer robot 280 may transfer the wafer loaded in the load lock chamber 271 in the vacuum state to the process chamber 275. A plurality of process chambers 275 for a dry etch process may be arranged in the dry etch unit 270. For the plurality of process chambers 275, the wafers loaded in the load lock chamber 271 are carried by the wafer carrying robot 280, and thus a dry etching process may be performed in the plurality of process chambers 275. For example, a dry etch process may be performed on the bevel region of the wafer in the plurality of process chambers 275. Specifically, a dry etch process may be performed on the front side of the wafer in the wafer bevel region in the plurality of process chambers 275.
Fig. 2 schematically shows a cross-sectional structure of a wet etching unit 260 in the semiconductor hybrid etching apparatus 100 according to the embodiment of the present invention. A cross-sectional configuration of one of the plurality of process chambers 265 disposed in the wet etch unit 260 is shown in fig. 2.
The process chamber 265 serves as a space for performing a wet etching process of the wafer 200, and may configure a substrate support frame 201 for supporting the wafer 200 to be process-treated. The wafer 200 may be mounted on the substrate support frame 201 and spaced apart from the substrate support frame 201 by a predetermined distance through a fixing member 202.
In an upper part of the process chamber 265, for example in an upper part of the wafer 200, a spray part 203 may be arranged, which spray part 203 is used for supplying wet chemicals 204 to the wafer 200. Although not shown in the drawings, the spraying part 203 may arrange a plurality of nozzles for spraying the wet chemicals 204 to face the wafer 200. It is shown for the ejection parts 203 to be arranged only on the upper portion of the wafer 200, but the ejection parts 203 may be arranged on the lower portion of the wafer 200.
The substrate holder 201 is rotatable with respect to the substrate holder 201 by a rotation shaft 206. The rotation shaft 206 may be connected with a rotation tool 205, and the rotation tool 205 is used for providing power, such as rotational force, to the rotation shaft 206. For example, the rotary tool 205 may include a motor. Accordingly, the rotational force provided by the rotation tool 205 is transmitted to the substrate support frame 201 through the rotation shaft 206 to rotate the wafer 200.
The wet etch unit 260 may perform a wet etch process on the wafer 200 in the process chamber 265. For example, in the bevel etching process, the back surface 200b of the wafer 200 may be etched by supplying the wet chemical 204 for etching the back surface of the wafer to the wafer 200 through the spray part 203 in a state where the substrate support frame 201 is rotated by the rotational force transmitted from the rotational tool 205 through the rotational shaft 206. At this time, the back surface of the bevel region of the wafer may be etched or the back surface of the wafer may be etched entirely. In the embodiment of the present invention, the wet etching process for etching the slope by spraying is exemplified, but is not necessarily limited thereto.
As another example, when a wafer cleaning process is performed after a bevel etching process, the wet chemicals 204 for cleaning a wafer are sprayed to the wafer 200 through the spraying part 203 in a state where the substrate supporting frame 201 is rotated by a rotational force transmitted from the rotation tool 205 through the rotation shaft 206, so that the wafer cleaning process can be performed.
When the wet etching process or the cleaning process is performed, the wafer 200 may be disposed in the process chamber 265 with the front surface 200a of the wafer 200 facing the rotary tool 205 and the rear surface 200b facing the upper side. For this purpose, although not shown in the drawings, a reverse kit for reversing the wafer 200 may be disposed in the process chamber 265. The flipping tool need not be disposed in the process chamber 265 of the wet process unit 260, but may also be disposed in the EFEM section 130; such as load port 210 or the buffer module 230.
Fig. 3 schematically shows a cross-sectional structure of a dry etching unit 270 for bevel etching according to an embodiment of the present invention. Referring to fig. 3, the dry etching unit 270 for bevel etching according to the embodiment of the present invention includes: a chamber 275; a substrate support frame 310 on which the wafer 200 is mounted and which is located in the chamber 271; a gas distribution plate 320 disposed at an upper side of the substrate support frame 310 in the chamber 275 to correspond to the wafer 200; and a ring-shaped electrode 330. The front face 200a of the wafer 200 is illustrated in the drawings as facing the upper side of the chamber 275, but is not necessarily limited thereto.
For example, the substrate support 310 coupled to the RF power source 340 may function as a conventional electrode; for example, the negative electrode. The electrode 330 may function as another electrode of the etching apparatus; such as the positive electrode. The electrode 330 may include an upper electrode 331 and a lower electrode 335, the upper electrode 331 may be disposed on an upper side with respect to the wafer 200, the lower electrode 335 may face the upper electrode 332, and the lower electrode 335 may correspond to the substrate holder 310.
The gas distribution plate 320 supplies an inert gas, such as N2 gas, to a component forming region where a component pattern (not shown) is formed in the wafer 200; while the edge region (i.e., bevel region) of the wafer may be supplied with an etching process gas.
Although not shown in the drawings, an insulating ring is arranged between the upper electrode 331 and the gas distribution plate 320 so that the upper electrode 331 can be electrically insulated from the gas distribution plate 320. In addition, a lower insulating ring is disposed between the lower electrode 335 and the substrate holder 310, so that the lower electrode 335 can be electrically insulated from the substrate holder 310.
The dry etching unit 270 forms a Capacitively Coupled Plasma (CCP) between the upper electrode 331 and the lower electrode 335 and an edge portion of the wafer 200 using the RF power applied through the RF power source 340, thereby performing bevel etching.
The dry etching unit and the wet etching unit constituting the hybrid etching apparatus according to the embodiment of the present invention are not limited to the structures shown in the drawings, but may be applied to various etching apparatuses used in a semiconductor process. For example, a dry etching apparatus or a wet etching apparatus may be disposed in the stage 100 in order to perform a dry etching process and a wet etching process on the front surface 200a or the back surface 200b of the wafer, respectively. In addition, the etched load may also perform an etching process on both the front and back sides of the wafer. Furthermore, the hybrid etching apparatus according to the embodiment of the present invention is not only suitable for bevel etching or cleaning of a wafer, but also suitable for various etching processes. For example, the hybrid etching apparatus of the present invention may also be applied to a separate wet etching process, a separate dry etching process, or a separate cleaning process.
Fig. 4 is a diagram for explaining an etching process of a wafer bevel region using the semiconductor hybrid etching apparatus according to the embodiment of the present invention. Referring to fig. 4 together with fig. 1 to 3, a hybrid bevel etching method according to an embodiment of the present invention will be described.
First, among a plurality of FOUPs 215 loaded in the EFEM part 130 of the hybrid etching apparatus, wafers to be processed (refer to 200 of fig. 2 and 3) are loaded in units of lot in the respective FOUPs 215 (S400); then, the wafer 200 loaded on the FOUP 215 is temporarily stored in the corresponding buffer member 235 among the plurality of buffer members 235 by a transfer robot (IR) serving as the wafer transfer tool 225 (S410).
Then, the wafer 200 stored in the buffer 235 is transferred to the process chamber 275 of the dry etching unit 270 by a Wafer Transfer Robot (WTR) (i.e., a wafer transfer tool 250) disposed in the wafer transfer passage 240 (S420).
Referring to fig. 1, the wafer 200 stored in the buffer 235 is transferred to the load-lock chamber 271 of the dry etching unit 270 by the Wafer Transfer Robot (WTR), and the wafer 200 transferred to the load-lock chamber 271 is transferred to a corresponding process chamber 275 among the plurality of process chambers 275 by a wafer transfer robot (DTR) (i.e., a wafer transfer tool 280) disposed at the transfer chamber 273.
In the process chamber 275 for dry etching, a bevel etching process is first performed using a dry etching process with respect to the front of the bevel region of the wafer 200 mounted on the substrate support frame 310 (S430).
As shown in fig. 3, an RF power is supplied to a substrate support stand 310 disposed in a process chamber 275 by an RF power source 340, and an etching gas is sprayed toward the wafer 200 through a spray nozzle of the gas distribution plate 320, thereby forming a plasma (CCP) at a bevel region (i.e., an edge portion) of the wafer 200. Accordingly, the first bevel etching process is performed on the front side of the bevel region of the wafer 200 through the dry etching process, and thus the film or particles, etc. accumulated in the bevel region of the wafer 200 may be removed.
The primarily bevel-etched wafer 200 is transferred to the process chamber 265 of the wet etching unit 260 through the wafer transfer passage 240 using the wafer transfer tool 250 (S440).
First, the primarily bevel-etched wafer 200 is transferred to the load lock chamber 271 by a wafer transfer robot (DTR) disposed in the transfer chamber 273. The wafer 200 loaded in the load lock chamber 271 is transferred to the wet etching unit 260 by a Wafer Transfer Robot (WTR), i.e., the wafer transfer tool 250. Although not shown in the drawings, the wafer transferred by the Wafer Transfer Robot (WTR) is transferred to the process chamber 265 for wet etching by a wafer loading tool of the wet etching unit 260.
In the process chamber 265 for wet etching, a bevel etching process is secondarily performed using a wet etching process with respect to the rear surface of the bevel region of the wafer 200 mounted on the substrate support frame 201 or the entire rear surface of the wafer 200 (S450). At this time, the secondary bevel etching process may be performed in a state where the back surface of the wafer 200 is mounted to face the upper side, as the case may be.
As shown in fig. 2, a wet chemical 204 is supplied to the wafer 200 mounted on the substrate support frame 201 disposed in the process chamber 265 through the spraying part 203, and a secondary bevel etching process is performed on the back surface of the wafer bevel region or the back surface of the wafer including the wafer bevel region in a full surface. Accordingly, film matter or particles and the like accumulated on the back surface of the wafer can be removed.
Then, a bevel clean process is performed in situ (in-situ) on the secondary bevel etched wafer 200 in the same chamber, such as process chamber 265 (S460). The cleaning process may be performed to remove particles generated due to a dry etching process (i.e., the first bevel etching process). At this time, the bevel cleaning process may be performed in a state where the back surface of the wafer 200 is mounted to face the upper side, as the case may be.
Since the bevel cleaning process is performed in situ in the same chamber as the wet etching process (i.e., the secondary bevel etching process) 265, the bevel cleaning process can be performed without increasing the wafer loading and transferring processes, thereby achieving a simplified process and reducing the exposure to contamination. In addition, if the wet etching process is performed by mounting the wafer with the back surface thereof facing upward, the wet etching process is performed in a state where the wafer 200 is flipped by the wafer flipping tool, and the cleaning process can be performed in a flipped state without adding the wafer flipping process, so that the process can be simplified and the process time can be shortened.
The wafer 200 having completed the bevel etching process and the cleaning process is transferred from the process chamber 265 to the buffer 235 by the Wafer Transfer Robot (WTR) (S470). Although not shown in the drawings, wafers may be unloaded from the process chamber 265 by a wafer unloading tool. Then, the wafer 200 stored in the buffer 235 is transported by a wafer transport tool (IR) and loaded into the FOUP 215 of the load port 210 of the EFEM part 130 (S480).
The dry etching process, the wet etching process, and the cleaning process for bevel etching according to an embodiment of the present invention are not limited to specific processes, respectively, but may be applied to various processes used in a semiconductor process and a display manufacturing process.
Fig. 5 is a view for explaining an etching process of a bevel region of a wafer using a semiconductor hybrid etching apparatus according to another embodiment of the present invention. A hybrid bevel etching method according to an embodiment of the present invention is described with reference to fig. 5 together with fig. 1 to 3.
First, among the FOUPs 215 of the EFEM part 130 of the hybrid etching apparatus, wafers to be process-processed (refer to 200 of fig. 2 and 3) are loaded in units of lot on the corresponding FOUPs 215 (S500); then, the wafer 200 loaded on the FOUP 215 is temporarily stored in the buffer 235 by a transfer robot (IR) (i.e., the wafer transfer tool 225) (S510).
The wafer 200 stored in the buffer 235 is transferred to the process chamber 265 of the wet etching unit 260 through the wafer transfer channel 240 by the wafer transfer tool 250 (S520). Although not shown in the drawings, the wafer transported by the Wafer Transport Robot (WTR) may be loaded into the process chamber 265 for wet etching by a wafer loading tool of the wet etching unit 260.
In the process chamber 265 for wet etching, a bevel etching process is first performed using a wet etching process with respect to the back surface of the bevel region of the wafer 200 mounted on the substrate support frame 201 or the entire back surface of the wafer 200 (S530). At this time, the primary bevel etching process may be performed in a state where the back surface of the wafer 200 is mounted toward the upper side, as the case may be.
As shown in fig. 2, the first bevel etching process may be performed on the entire back surface of the wafer bevel region or the back surface of the wafer including the wafer bevel region by supplying the wet chemicals 204 to the wafer 200 mounted on the substrate support frame 201 disposed in the process chamber 265 through the spraying part 203. Accordingly, film matter or particles and the like accumulated on the back surface of the wafer can be removed.
Then, the wafer 200 primarily bevel-etched in the process chamber 265 of the wet etching unit 260 may be transferred to the process chamber 275 of the dry etching unit 270 through the wafer transfer passage 240 using a Wafer Transfer Robot (WTR) (i.e., a wafer transfer tool 250) disposed at the wafer transfer passage 240 (S540). The wafer is unloaded by the substrate unloading tool of the wet etching unit 260 and may be transferred to the dry etching unit 270 through the wafer transfer passage by the Wafer Transfer Robot (WTR).
Referring to fig. 1, the wafer 200 stored in the buffer 235 is transferred to the load-lock chamber 271 of the dry etching unit 270 by the Wafer Transfer Robot (WTR), and the wafer 200 transferred in the load-lock chamber 271 is transferred to a corresponding process chamber 275 among the plurality of process chambers 275 by the wafer transfer robot (DTR) (i.e., wafer transfer tool 280) disposed at the transfer chamber 273.
In the process chamber 271 for dry etching, a bevel etching process is secondarily performed using a dry etching process with respect to the front surface of the bevel region of the wafer 200 mounted on the substrate support frame 310 (S550).
As shown in fig. 3, an RF power is supplied to a substrate support bracket 310 disposed in a process chamber 275 by an RF power source 340, and an etching gas is sprayed toward the wafer 200 through a spray nozzle of the gas distribution plate 320, thereby forming a plasma (CCP) at a bevel region (i.e., an edge portion) of the wafer 200. Accordingly, the secondary bevel etching process is performed for the front of the bevel region of the wafer 200 through the dry etching process, thereby removing film matter or particles, etc. accumulated in the front of the bevel region of the wafer 200.
Then, the secondary bevel-etched wafer 200 is carried to the process chamber 265 of the wet etching unit 260 through the wafer carrying passage 240 using the wafer carrying tool 250 (S560).
First, the wafer 200 subjected to the secondary bevel etching is transferred to the load lock chamber 271 by a wafer transfer robot (DTR) disposed in the transfer chamber 273. The wafer 200 loaded in the load lock chamber 271 is transferred to a wet etching unit 260 by a Wafer Transfer Robot (WTR), i.e., the wafer transfer tool 250.
Then, a bevel cleaning process is performed on the wafer 200 for the secondary bevel etching in the same chamber (S570). The cleaning process may be performed to remove particles when a dry etching process (i.e., a secondary bevel etching process) is performed. At this time, the bevel cleaning process may be performed in a state where the back surface of the wafer 200 is mounted toward the upper side, as the case may be. As shown in fig. 2, a cleaning process may be performed on a wafer 200 mounted on a substrate support bracket 201 disposed in a process chamber 265 by supplying a wet chemical 204 to the wafer through a spraying part 203.
The wafer 200 having completed the bevel etching process is transferred from the process chamber 265 to the buffer 235 by the Wafer Transfer Robot (WTR) (S580). Although not shown in the figures, the wafer 200 may be unloaded from the process chamber 265 by a wafer unload tool. Then, the wafer 200 stored in the buffer 235 is transported and loaded to the FOUP 215 of the load port 210 of the EFEM part by a wafer transport tool (IR) (S590).
The dry etching process, the wet etching process, and the cleaning process for bevel etching according to another embodiment of the present invention are not limited to a specific process, respectively, but may be applied to various processes used in a semiconductor process, a display manufacturing process, and the like.
The hybrid etching apparatus and method of the embodiments of the present invention combine a dry etching unit and a wet etching unit in one etching apparatus, thereby minimizing atmospheric exposure of a wafer to perform an etching process, and further minimizing particle contamination. In addition, wet etching and dry etching are performed in combination for the bevel region, so that etching of the bevel region can be finely controlled.
As another example, the semiconductor etching process may also be a wet etching process separately performed, the wet etching process including the steps of: transporting the wafer 200 loaded in the FOUP to the buffer module 230 to temporarily keep the wafer 200; transporting the wafer 200 stored in the buffer module 230 to the process chamber 265 of the wet etching unit 260 through the wafer transport passage 240 by the wafer transport tool 250; performing a wet etch process for the wafer 200; transporting the wafer wet etched in the process chamber 265 to the buffer module 230; loading the wafers of the buffer module to the FOUP.
As another example, the semiconductor etching process may also be a wet etching process separately performed, and the wet etching process includes the following steps: transporting the wafer 200 loaded in the FOUP to the buffer module 230 to temporarily keep the wafer 200; transporting the wafer 200 stored in the buffer module 230 to the process chamber 265 of the wet etching unit 260 through the wafer transport passage 240 by the wafer transport tool 250; performing a cleaning process for the wafer 200; transporting the wafers cleaned in the process chamber 265 to the buffer module 230; the wafers of the buffer module are loaded to the FOUP.
As another example, the semiconductor etching process may also be a wet etching process separately performed, and the wet etching process includes the following steps: transporting the wafer 200 loaded in the FOUP to the buffer module 230 to temporarily keep the wafer 200; transferring the wafer 200 stored in the buffer module 230 to the process chamber 275 of the dry etching unit 270 through the wafer transfer passage 240 by the wafer transfer tool 250; performing a dry etch process for the wafer 200; transferring the wafer in the process chamber 271 to the buffer module 230; the wafers of the buffer module are loaded to the FOUP.
Since other embodiments can be implemented by those skilled in the art without changing the technical idea or essential features of the present invention, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention should be determined by the claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and the equivalent concept thereof should be construed as being included in the scope of the present invention.

Claims (11)

1. A semiconductor hybrid etching apparatus, comprising:
A platform;
a first etching unit disposed inside the stage and having a first etching chamber performing a first etching process on a wafer;
a second etching unit disposed inside the stage and having a second etching chamber performing a second etching process on the wafer, the second etching process being different in etching manner from the first etching process;
and a wafer transfer tool disposed in a wafer transfer passage formed between the first and second etching units, and transferring the wafer between the first and second etching units through the wafer transfer passage.
2. The semiconductor hybrid etching device according to claim 1,
a cleaning process is performed on the wafer in one of the first and second etching units.
3. The semiconductor hybrid etching device according to claim 1 or 2,
the first etching unit is a dry etching unit, and the second etching unit is a wet etching unit;
a dry etch process is performed on a front side of a bevel region of the wafer in the first etch chamber, followed by a wet etch process performed on a back side of the bevel region of the wafer or the back side of the wafer in the second etch chamber.
4. The semiconductor hybrid etching device according to claim 3,
performing a cleaning process on the wafer in-situ in the second etch chamber after performing the wet etch process.
5. The semiconductor hybrid etching device according to claim 4,
after the first etching process is performed, the first etched wafer in the first etching chamber is carried to the second etching chamber through the wafer carrying passage by the wafer carrying tool.
6. The semiconductor hybrid etching apparatus according to claim 1, further comprising:
at least one FOUP arranged in the stage, loading the wafer to be process-processed, wherein the wafer to be process-processed is carried to the first etching unit or the second etching unit by the wafer carrying tool; and
a buffer member disposed between the FOUP on the stage and the first and second etching units, and temporarily storing the wafer transferred from the FOUP to the first or second etching unit;
wherein the wafer carrying passage is formed between the buffer in the stage and the first and second etching units.
7. The semiconductor hybrid etching apparatus according to claim 6, further comprising:
a transport module disposed between the FOUP in the stage and the buffer, and including a transport robot for transporting the wafer from the FOUP to the buffer.
8. A semiconductor hybrid etching method using a semiconductor hybrid etching apparatus including a stage, a first etching chamber and a second etching chamber disposed inside the stage, the semiconductor hybrid etching method comprising the steps of:
performing a first etch process on a front side of a wafer in a first etch chamber;
performing a second etch process on the back side of the wafer in a second etch chamber;
performing a cleaning process on the wafer in one of the first and second etch chambers;
wherein the second etching process is performed in an etching method different from the first etching process.
9. The semiconductor hybrid etching method according to claim 8,
the first etch chamber is a dry etch chamber and the second etch chamber is a wet etch chamber;
The first etching process is performed on a front surface of a bevel region of the wafer by the dry etching method, and the second etching process is performed on a rear surface of the bevel region of the wafer or the rear surface of the wafer by a wet etching method.
10. The semiconductor hybrid etching method according to claim 9,
the second etch process and the cleaning process are performed in-situ in the same second etch chamber.
11. The semiconductor hybrid etching method according to claim 9,
forming a wafer transfer passage between the first and second etching chambers in the stage, the wafer transfer passage being provided with a wafer transfer tool responsible for transferring the wafer to the first or second etching chamber;
and the method further comprises, after the step of performing the first etching process, the steps of: the first-etched wafer in the first etching chamber is carried to the second etching chamber through the wafer carrying passage using the wafer carrying tool.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102397244B1 (en) * 2020-03-11 2022-05-12 주식회사 지티아이코리아 Semiconductor hybrid etching apparatus and method
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1461046A (en) * 2002-05-20 2003-12-10 株式会社日立制作所 Semiconductor device and its mfg. method
KR20050106206A (en) * 2004-05-04 2005-11-09 세메스 주식회사 Apparatus and method for treating a substrate
KR20100052659A (en) * 2008-11-11 2010-05-20 세메스 주식회사 Apparatus for treating backside of substrate
KR20160149702A (en) * 2015-06-19 2016-12-28 주식회사 에이씨엔 Hybrid substrate processing system for dry and wet process and substrate processing method thereof
US20170186600A1 (en) * 2015-12-24 2017-06-29 Infineon Technologies Austria Ag Semiconductor wafer and method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060001235A (en) * 2004-06-30 2006-01-06 엘지.필립스 엘시디 주식회사 Etching equipment
KR100849366B1 (en) * 2006-08-24 2008-07-31 세메스 주식회사 Apparatus and method for treating substrate
KR101718519B1 (en) * 2014-07-24 2017-03-22 최도현 Single platform work piece processing apparatus for dry and wet processing
KR102129773B1 (en) * 2016-04-07 2020-07-03 최도현 Single platform work piece processing apparatus for dry and wet processing

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1461046A (en) * 2002-05-20 2003-12-10 株式会社日立制作所 Semiconductor device and its mfg. method
US20040026692A1 (en) * 2002-05-20 2004-02-12 Katsuhiro Ota Semiconductor apparatus and process for its production
KR20050106206A (en) * 2004-05-04 2005-11-09 세메스 주식회사 Apparatus and method for treating a substrate
KR20100052659A (en) * 2008-11-11 2010-05-20 세메스 주식회사 Apparatus for treating backside of substrate
KR20160149702A (en) * 2015-06-19 2016-12-28 주식회사 에이씨엔 Hybrid substrate processing system for dry and wet process and substrate processing method thereof
US20170186600A1 (en) * 2015-12-24 2017-06-29 Infineon Technologies Austria Ag Semiconductor wafer and method

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