CN111984464B - Programmable logic device monitoring and restarting method, device and system - Google Patents
Programmable logic device monitoring and restarting method, device and system Download PDFInfo
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- CN111984464B CN111984464B CN202010726580.8A CN202010726580A CN111984464B CN 111984464 B CN111984464 B CN 111984464B CN 202010726580 A CN202010726580 A CN 202010726580A CN 111984464 B CN111984464 B CN 111984464B
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- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1438—Restarting or rejuvenating
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/324—Display of status information
- G06F11/327—Alarm or error message display
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Abstract
The invention discloses a method, a device and a system for monitoring and restarting a programmable logic device, which are used for monitoring and judging whether the programmable logic device is abnormal or not in real time; if the programmable logic device is monitored to be abnormal and is not recovered after the first preset time, controlling the programmable logic device to be restarted again; continuously monitoring the programmable logic device, and controlling the programmable logic device to be in cold restart if the programmable logic device is not recovered after a second preset time; the second preset time length is longer than the first preset time length. The invention can carry out debugging modification on the programmable logic device by automatically monitoring and restarting the programmable logic device, automatically recover to normal as much as possible, shorten the fault time and reduce the influence on the system.
Description
Technical Field
The invention relates to a programmable logic device, in particular to a method, a device and a system for monitoring and restarting the programmable logic device.
Background
Programmable Logic Devices (PLDs) are important components in a server, and are mainly responsible for a boot-up time sequence memory part of the server to perform platform management, which means a series of monitoring and control. However, the programmable logic device has no state monitoring or restarting mode for itself, once a problem occurs, the whole system can be stopped, and the programmable logic device can not be restored by self after waiting for repair of maintenance personnel.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method, an apparatus, and a system for monitoring and restarting a programmable logic device, which can monitor the programmable logic device and automatically attempt to restart the programmable logic device when the programmable logic device is abnormal.
The technical scheme of the invention is as follows: a programmable logic device monitoring and restarting method comprises the following steps:
monitoring and judging whether the programmable logic device is abnormal or not in real time;
if the programmable logic device is monitored to be abnormal and is not recovered after the first preset time, controlling the programmable logic device to be restarted again;
and continuously monitoring the programmable logic device, and controlling the programmable logic device to be cold restarted if the programmable logic device is not recovered after a second preset time.
Furthermore, in the method, whether the programmable logic device is abnormal or not is judged by monitoring the heartbeat signal of the programmable logic device; and controlling the programmable logic device to be restarted again through the BMC chip.
Further, the method also includes: and sending an alarm signal when the programmable logic device is not recovered after the first preset time.
The technical scheme of the invention also comprises a programmable logic device monitoring and restarting device, which comprises,
a monitoring and judging module: monitoring and judging whether the programmable logic device is abnormal or not in real time;
a hot restart module: if the programmable logic device is abnormal and is not recovered after a first preset time, controlling the programmable logic device to be restarted again;
a cold restart module: and if the programmable logic device is not recovered after the second preset time, controlling the programmable logic device to be in cold restart.
Furthermore, the monitoring and judging module judges whether the programmable logic device is abnormal or not by monitoring the heartbeat signal of the programmable logic device;
the hot restart module controls the programmable logic device to be hot restarted through the BMC chip.
Further, the device also comprises an alarm module: and sending an alarm signal when the programmable logic device is not recovered after the first preset time.
The technical scheme of the invention also comprises a programmable logic device monitoring and restarting system, wherein the programmable logic device is connected with the BMC chip and comprises the following steps: the heartbeat signal judging circuit, the hot restart circuit and the cold restart circuit;
the input end of the heartbeat signal judging circuit is connected with the programmable logic device, the output end of the heartbeat signal judging circuit is respectively connected with the input end of the hot restarting circuit and the input end of the cold restarting circuit, the output end of the hot restarting circuit is connected with the BMC chip, and the output end of the cold restarting circuit is connected with the power supply of the programmable logic device; when the heartbeat signal judging circuit judges that the heartbeat signal of the programmable logic device is abnormal and does not recover to be normal after a first preset time, the hot restart circuit informs the BMC chip to carry out hot restart on the programmable logic device; and if the heartbeat signal judging circuit judges that the heartbeat signal does not recover to be normal after a second preset time, controlling the power supply of the programmable logic device to be restarted in a power failure mode through the cold restart circuit.
Further, the heartbeat signal determination circuit includes: the circuit comprises a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, an exclusive-OR gate U1 and an MOS (metal oxide semiconductor) tube M1;
the output end of the programmable logic device is respectively connected with the first end of the resistor R1 and the first input end of the exclusive-OR gate U1; one path of the second end of the resistor R1 is connected with the second input end of the exclusive-OR gate U1, and the other path of the second end of the resistor R1 is grounded through the capacitor C1; the output end of the exclusive-or gate U1 is connected with the grid electrode of the MOS tube M1, one path of the drain electrode of the MOS tube M1 is connected with a power supply voltage through a resistor R2, the other path of the drain electrode of the MOS tube M1 is grounded through a capacitor C2, and the source electrode of the MOS tube M1 is grounded.
Further, the warm restart circuit includes: the circuit comprises a resistor R3, a capacitor C3, a comparator U2, an inverter U3 and a NOR gate U4;
the positive input end of the comparator U2 is connected with a node between the resistor R2 and the capacitor C2, and the negative input end of the comparator U2 is connected with a first reference voltage; one path of the output end of the comparator U2 is connected with the input end of the phase inverter U3, and the other path of the output end of the comparator U2 is connected with the first end of the resistor R3; the output end of the phase inverter U3 is connected with the first input end of the NOR gate U4; one path of the second end of the resistor R3 is connected with the second input end of the NOR gate U4, and the other path of the second end of the resistor R3 is grounded through the capacitor C3; the output end of the NOR gate U4 is connected with the BMC chip;
the cold restart circuit includes: the circuit comprises a resistor R4, a capacitor C4, a comparator U5, an inverter U6 and a NOR gate U7;
the positive input end of the comparator U5 is connected with a node between the resistor R4 and the capacitor C4, and the negative input end is connected with a first reference voltage; one path of the output end of the comparator U5 is connected with the input end of the phase inverter U6, and the other path of the output end of the comparator U5 is connected with the first end of the resistor R4; the output end of the phase inverter U6 is connected with the first input end of the NOR gate U7; one path of the second end of the resistor R4 is connected with the second input end of the NOR gate U7, and the other path of the second end of the resistor R4 is grounded through the capacitor C4; and the output end of the NOR gate U7 is connected with a power supply of the programmable logic device.
Furthermore, the system also comprises an alarm circuit, and the output end of the NOR gate U4 is also connected with the alarm circuit; when the heartbeat signal is still not normal after the first preset duration, the alarm circuit gives an alarm.
The invention provides a method, a device and a system for monitoring and restarting a programmable logic device, which are used for monitoring the programmable logic device, wherein when the programmable logic device is abnormal (whether the programmable logic device is abnormal or not can be judged by monitoring a heartbeat signal of the programmable logic device), if the programmable logic device is not recovered to be normal after a first period of time, the programmable logic device is restarted again; and after the hot restart, if the normal state still can not be recovered, namely no normal heartbeat signal exists after the second period of time, the programmable logic device is subjected to cold restart. The invention can automatically monitor and restart the programmable logic device, and can debug and modify the programmable logic device, automatically recover to normal as much as possible, shorten the failure time and reduce the influence on the system.
Drawings
FIG. 1 is a schematic flow chart of a method according to an embodiment of the present invention.
Fig. 2 is a schematic block diagram of a second structure according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a three-circuit structure according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings by way of specific examples, which are illustrative of the present invention and are not limited to the following embodiments.
Example one
The embodiment provides a monitoring and restarting method for a programmable logic device, which monitors the programmable logic device in real time, and automatically repairs the programmable logic device through restarting when the programmable logic device is abnormal. The programmable logic device refers to an FPGA or a CPLD.
As shown in fig. 1, the method comprises the following steps:
s1, monitoring and judging whether a programmable logic device is abnormal or not in real time;
s2, if the programmable logic device is monitored to be abnormal and is not recovered after a first preset time, controlling the programmable logic device to be restarted again;
and S3, continuously monitoring the programmable logic device, and controlling the programmable logic device to be cold restarted if the programmable logic device is not recovered after a second preset time.
In this embodiment, whether the programmable logic device is abnormal may be specifically determined by monitoring a heartbeat signal of the programmable logic device. And when the heartbeat signal is not monitored, the programmable logic device is abnormal.
Further, when the heartbeat signal is still not monitored after the first preset time, the programmable logic device is restarted again. It should be noted that the programmable logic device can be controlled to be hot-restarted by the BMC chip. In addition, when the heartbeat signal cannot be monitored after the first preset time, an alarm is sent out to remind a worker to pay attention. The alarm is prevented from being sent out at the first time when the heartbeat signal cannot be monitored, so that the workload is prevented from being increased.
After a warm restart, the programmable logic device may still not be able to recover to normal. It should be noted that, in the whole process, the programmable logic device is continuously monitored, that is, the heartbeat signal of the programmable logic device is continuously monitored, and if the heartbeat signal cannot be monitored after the second preset time period, which indicates that the hot restart fails, the programmable logic device is cold restarted, that is, a power failure restart action occurs. It should be noted that the second preset time length is the same as the timing start point of the first preset time length when the programmable logic device is monitored to be started from the abnormal start, and the second preset time length is longer than the first preset time length.
According to the embodiment, the fault recovery is carried out on the programmable logic device in a hot restart and sub-cooling restart mode, so that the influence of the fault on a system can be reduced to the greatest extent.
Example two
As shown in fig. 2, on the basis of the first embodiment, the present embodiment provides a monitoring and restarting apparatus for a programmable logic device, which includes the following functional modules.
The monitoring and judging module 101: monitoring and judging whether the programmable logic device is abnormal or not in real time;
the hot restart module 102: if the programmable logic device is abnormal and is not recovered after the first preset time, controlling the programmable logic device to be restarted again;
the cold restart module 103: and if the programmable logic device is not recovered after the second preset time, controlling the programmable logic device to be in cold restart.
In this embodiment, the monitoring and determining module 101 determines whether the programmable logic device is abnormal by monitoring a heartbeat signal of the programmable logic device. And when the heartbeat signal is not monitored, the programmable logic device is abnormal.
The hot restart module 102 controls the programmable logic device to be hot restarted through the BMC chip.
In order to timely and effectively remind workers, the device is further provided with an alarm module, and when the programmable logic device is not recovered after a first preset time, an alarm signal is sent out.
EXAMPLE III
The embodiment provides a monitoring and restarting system for a programmable logic device, which realizes monitoring and restarting repair of the programmable logic device by using hardware. It should be noted that the programmable logic device is connected to the BMC chip.
As shown in fig. 3, the system includes: a heartbeat signal judging circuit 104, a hot restart circuit 105 and a cold restart circuit 106.
The input end of the heartbeat signal judging circuit 104 is connected with the programmable logic device, the output end of the heartbeat signal judging circuit is respectively connected with the input end of the hot restart circuit 105 and the input end of the cold restart circuit 106, the output end of the hot restart circuit 105 is connected with the BMC chip, and the output end of the cold restart circuit 106 is connected with the power supply of the programmable logic device; when the heartbeat signal judging circuit 104 judges that the heartbeat signal of the programmable logic device is abnormal and does not recover to be normal after a first preset time period, the hot restart circuit 105 informs the BMC chip of hot restart of the programmable logic device; if the heartbeat signal judging circuit 104 judges that the heartbeat signal does not return to normal after the second preset duration, the cold restart circuit 106 controls the power supply of the programmable logic device to be restarted in a power-down mode.
Specifically, the heartbeat signal determination circuit 104 of the present embodiment includes: the circuit comprises a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, an exclusive-OR gate U1 and an MOS (metal oxide semiconductor) tube M1.
The output end of the programmable logic device is respectively connected with the first end of the resistor R1 and the first input end of the exclusive-OR gate U1; one path of the second end of the resistor R1 is connected with the second input end of the exclusive-OR gate U1, and the other path of the second end of the resistor R1 is grounded through the capacitor C1; the output end of the exclusive-OR gate U1 is connected with the grid electrode of the MOS tube M1, one path of the drain electrode of the MOS tube M1 is connected with a power supply voltage through a resistor R2, the other path of the drain electrode of the MOS tube M1 is grounded through a capacitor C2, and the source electrode of the MOS tube M1 is grounded.
The warm restart circuit 105 is identical to the cold restart circuit 106 in this embodiment.
The warm restart circuitry 105 includes: the circuit comprises a resistor R3, a capacitor C3, a comparator U2, an inverter U3 and a NOR gate U4.
The positive input end of the comparator U2 is connected with a node between the resistor R2 and the capacitor C2, and the negative input end of the comparator U2 is connected with a first reference voltage; one path of the output end of the comparator U2 is connected with the input end of the phase inverter U3, and the other path of the output end of the comparator U2 is connected with the first end of the resistor R3; the output end of the phase inverter U3 is connected with the first input end of the NOR gate U4; one path of the second end of the resistor R3 is connected with the second input end of the NOR gate U4, and the other path of the second end of the resistor R3 is grounded through the capacitor C3; the output end of the NOR gate U4 is connected with the BMC chip.
The cold restart circuit 106 includes: the circuit comprises a resistor R4, a capacitor C4, a comparator U5, an inverter U6 and a NOR gate U7.
A positive input end of the comparator U5 is connected with a node between the resistor R4 and the capacitor C4, and a negative input end is connected with a first reference voltage; one path of the output end of the comparator U5 is connected with the input end of the phase inverter U6, and the other path of the output end of the comparator U5 is connected with the first end of the resistor R4; the output end of the inverter U6 is connected with the first input end of the NOR gate U7; one path of the second end of the resistor R4 is connected with the second input end of the NOR gate U7, and the other path of the second end of the resistor R4 is grounded through the capacitor C4; and the output end of the NOR gate U7 is connected with a power supply of the programmable logic device.
In addition, the system is also provided with an alarm circuit for effectively reminding workers in time, and the output end of the NOR gate U4 is also connected with the alarm circuit; when the heartbeat signal is still not normal after the first preset duration, the alarm circuit gives an alarm.
In specific implementation, the programmable logic device is started to load the firmware of the programmable logic device. After the firmware is loaded, the programmable logic device continuously sends a heartbeat signal similar to a clock signal to the heartbeat signal determining circuit 104 through the general-purpose input/output pin. If the heartbeat signal judging circuit 104 does not receive the heartbeat signal, it indicates that the programmable logic device is down, the RC charge and discharge of the heartbeat signal judging circuit 104 will be continuously charged, and when the voltage reaches the set VPH1 (the hot restart voltage of the hot restart circuit 105), the hot restart circuit 105 will be started to notify the BMC of shutdown, the hot restart programmable logic device, and at the same time, the alarm circuit will be notified of alarm. If the programmable logic device fails to be restarted, the programmable logic device still does not send out a heartbeat signal, the RC charge and discharge of the heartbeat signal judgment circuit 104 can continuously charge accumulated voltage, and when the voltage reaches a set VPH2 (cold restart voltage of the cold restart circuit 106), the cold restart circuit 106 is started, and the programmable logic device is restarted according to the power supply of the programmable logic device, so that the programmable logic device performs cold restart.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention, and the present invention is not limited thereto, and any modifications and variations which can be made by those skilled in the art without departing from the spirit of the present invention shall fall within the scope of the present invention.
Claims (2)
1. A programmable logic device monitoring restart system, the programmable logic device is connected with a BMC chip, characterized by comprising: the heartbeat signal judging circuit, the hot restart circuit and the cold restart circuit;
the input end of the heartbeat signal judging circuit is connected with the programmable logic device, the output end of the heartbeat signal judging circuit is respectively connected with the input end of the hot restarting circuit and the input end of the cold restarting circuit, the output end of the hot restarting circuit is connected with the BMC chip, and the output end of the cold restarting circuit is connected with the power supply of the programmable logic device; when the heartbeat signal judging circuit judges that the heartbeat signal of the programmable logic device is abnormal and does not recover to be normal after a first preset time period, the hot restart circuit informs the BMC chip to carry out hot restart on the programmable logic device; if the heartbeat signal judging circuit judges that the heartbeat signal does not return to normal after the second preset time, the cold restart circuit controls the power supply of the programmable logic device to be powered down and restarted;
the heartbeat signal judging circuit includes: the circuit comprises a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, an exclusive-OR gate U1 and an MOS (metal oxide semiconductor) tube M1;
the output end of the programmable logic device is respectively connected with the first end of the resistor R1 and the first input end of the exclusive-OR gate U1; one path of the second end of the resistor R1 is connected with the second input end of the exclusive-OR gate U1, and the other path of the second end of the resistor R1 is grounded through the capacitor C1; the output end of the exclusive-OR gate U1 is connected with the grid electrode of the MOS tube M1, one path of the drain electrode of the MOS tube M1 is connected with a power supply voltage through a resistor R2, the other path of the drain electrode of the MOS tube M1 is grounded through a capacitor C2, and the source electrode of the MOS tube M1 is grounded;
the warm restart circuit includes: the circuit comprises a resistor R3, a capacitor C3, a comparator U2, an inverter U3 and a NOR gate U4;
the positive input end of the comparator U2 is connected with a node between the resistor R2 and the capacitor C2, and the negative input end is connected with a first reference voltage; one path of the output end of the comparator U2 is connected with the input end of the phase inverter U3, and the other path of the output end of the comparator U2 is connected with the first end of the resistor R3; the output end of the phase inverter U3 is connected with the first input end of the NOR gate U4; one path of the second end of the resistor R3 is connected with the second input end of the NOR gate U4, and the other path of the second end of the resistor R3 is grounded through the capacitor C3; the output end of the NOR gate U4 is connected with the BMC chip;
the cold restart circuit includes: the circuit comprises a resistor R4, a capacitor C4, a comparator U5, an inverter U6 and a NOR gate U7;
a positive input end of the comparator U5 is connected with a node between the resistor R4 and the capacitor C4, and a negative input end is connected with a first reference voltage; one path of the output end of the comparator U5 is connected with the input end of the phase inverter U6, and the other path of the output end of the comparator U5 is connected with the first end of the resistor R4; the output end of the inverter U6 is connected with the first input end of the NOR gate U7; one path of the second end of the resistor R4 is connected with the second input end of the NOR gate U7, and the other path of the second end of the resistor R4 is grounded through the capacitor C4; and the output end of the NOR gate U7 is connected with a power supply of the programmable logic device.
2. The programmable logic device monitoring and restarting system of claim 1, wherein the system further comprises an alarm circuit, and the output terminal of the nor gate U4 is further connected with the alarm circuit; when the heartbeat signal does not return to normal after the first preset duration, the alarm circuit gives an alarm.
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| CN108038019A (en) * | 2017-12-25 | 2018-05-15 | 曙光信息产业(北京)有限公司 | A kind of automatically restoring fault method and system of baseboard management controller |
| CN209297143U (en) * | 2019-03-14 | 2019-08-23 | 杭州海康威视数字技术股份有限公司 | A kind of abnormality monitoring system |
| CN110908839A (en) * | 2019-11-22 | 2020-03-24 | 苏州浪潮智能科技有限公司 | Method, device and equipment for relieving fault of logic module |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108038019A (en) * | 2017-12-25 | 2018-05-15 | 曙光信息产业(北京)有限公司 | A kind of automatically restoring fault method and system of baseboard management controller |
| CN209297143U (en) * | 2019-03-14 | 2019-08-23 | 杭州海康威视数字技术股份有限公司 | A kind of abnormality monitoring system |
| CN110908839A (en) * | 2019-11-22 | 2020-03-24 | 苏州浪潮智能科技有限公司 | Method, device and equipment for relieving fault of logic module |
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