CN111969054A - Reverse conducting SiC GTO semiconductor device and preparation method thereof - Google Patents
Reverse conducting SiC GTO semiconductor device and preparation method thereof Download PDFInfo
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Abstract
The invention provides a reverse conducting SiC GTO semiconductor device and a preparation method thereof, belonging to the technical field of high-voltage power electronics. The semiconductor structure includes: a first doping type P + injection layer, a second doping type N + injection layer, a first doping type P buffer layer, a first doping type P-drift layer, a second doping type N base region, a second doping type isolation N base region 201-2 and a first doping type P + anode layer; the functions of forward conduction of a common GTO and reverse follow current of a Pin diode are integrated in a semiconductor device, compared with the parallel use of two devices, the packaging reliability is high, the chip area can be greatly saved, the parasitic impedance of connection is reduced, the switching speed of the device is improved, and the defects of large modular packaging volume and low power density are avoided; the preparation method can be completed by adding a small number of steps on the basis of the ordinary GTO process flow.
Description
Technical Field
The invention relates to the technical field of high-voltage power electronics, in particular to a reverse conducting SiC GTO semiconductor device and a preparation method thereof.
Background
The forbidden band width of the silicon carbide (SiC) material is about 3 times of that of silicon (Si), the critical breakdown electric field is about 10 times of that of the silicon, and the high-temperature resistance is about 4 times of that of the silicon. The silicon carbide power semiconductor device has lower power consumption and is more suitable for industrial application environments with higher switching frequency and temperature. In all SiC power semiconductor devices, a gate turn-off thyristor (GTO) has not only a high blocking voltage characteristic, but also a large current capacity and a low turn-on voltage drop. Compared with an Insulated Gate Bipolar Transistor (IGBT) with the same voltage level, the on-state voltage of the IGBT is reduced under the condition of the same current density, the on-state loss is smaller, and the electric energy conversion efficiency can be greatly improved. With the continuous improvement of the quality of an epitaxial layer, the current GTO with the withstand voltage of 22 kilovolts (kV) has been reported, can greatly reduce the number of series power semiconductor devices, reduce the system cost and volume, and has good application prospects in power conversion, pulse power and power system application.
In a switching power converter, when an inductive load is driven by using a GTO, a freewheeling path needs to be provided for an inductor, or in other applications, such as pulse power discharge, because a discharge current waveform shows periodic damped oscillation, the GTO is also required to have a function of bearing reverse current, while a general SiC GTO does not have self-freewheeling capability. In the prior art, the SiC GTO obtains reverse current conduction in two general ways: 1) the general GTO and the SiC PiN diode with the same voltage and current level are reversely connected in parallel for use, the manufacturing cost of the whole system is increased due to the fact that the PiN diode and the GTO are manufactured respectively, the parasitic inductance of the connection between the PiN diode and the GTO is large, the switching speed of the GTO is seriously influenced, extra power consumption is increased, and the manufacturing process is complex and long in time consumption due to the fact that the PiN diode and the GTO are packaged respectively; 2) the common GTO and SiC diodes are used for packaging modules, parasitic parameters can be reduced compared with the former method, but the sum volume of the GTO and the SiC diodes is larger, so that the power density and the integration level of a system are not improved, the cost is higher, and the practical application occasions of the method are further limited.
Disclosure of Invention
The invention aims to provide a reverse conducting SiC GTO semiconductor device and a preparation method thereof aiming at the defects of the prior art, wherein GTO and a Pin diode are integrated on the same chip, so that the RC-GTO has the capability of anode-cathode forward conduction and cathode-anode reverse follow current at the same time, and the functions of the two chips are integrated in one semiconductor device, thereby greatly reducing the chip area, effectively reducing the manufacturing cost and improving the system power density and the integration level.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a reverse conducting SiC GTO power semiconductor device, which is sequentially stacked from bottom to top and comprises a cathode metal electrode, a first doping type P + injection layer, a second doping type N + injection layer, a first doping type P buffer layer, a first doping type P-drift layer, a second doping type N base region, a second doping type isolation N base region, a first doping type P + anode layer, a first medium passivation layer and a second medium passivation layer.
Further, the first doping type P + implantation layer and the second doping type N + implantation layer are highly the same in the vertical direction.
Further, the region boundary of the second doping type N + injection layer in the vertical direction is aligned with the second doping type N base region.
Further, the first doping type P + implantation layer and the second doping type N + implantation layer are highly the same in the vertical direction.
Furthermore, deep grooves are etched on the left side and the right side of the second doping type isolation N base region, the deep grooves are electrically isolated from the second doping type N base region respectively, and the deep grooves are electrically isolated from the upper metal electrode through a filling medium layer.
Further, the method comprises the following preparation steps:
1) selecting a five-layer wafer with the thickness of 120-250 mu m and the doping concentration of 1e14-1e15cm-3, and thinning the substrate by adopting a CMP (chemical mechanical polishing) process;
2) etching the front surface of the SiC wafer to form a P + anode mesa, and exposing the upper surface of the N base region;
3) etching the front surface, and forming the second doping type N base region and the second doping type isolation N base region by the N base region obtained by the second step of process through etching medium filling grooves;
4) performing ion implantation on the front surface, forming an ohmic contact region of the metal electrode on the surface of the second doping type N base region, and simultaneously forming the ohmic contact region of the metal electrode and a terminal region of a device on the surface of the second doping type N base region;
5) turning over the wafer, and respectively forming the first doping type P + injection layer and the second doping type N + injection layer through two times of ion implantation, and simultaneously forming an ohmic contact region of the metal electrode 32;
6) sputtering metal layers on the front surface and the back surface respectively, and forming ohmic contacts of an A pole, a C pole and a G pole with good performance by adopting a stripping process and a rapid thermal annealing process at the same step;
7) forming G-electrode ohmic contact thick metal on the front surface, and simultaneously depositing a passivation layer to form filling of the left and right isolation grooves of the second doping type isolation N base region;
8) forming A-pole ohmic contact thick metal on the front surface, and simultaneously depositing a passivation layer to form electrical isolation between the first metal electrode 31 and the second metal electrode 33;
9) etching the oxide on the front surface to expose the pad of the G-pole ohmic contact thick metal;
tenth, coating a PI polymer on the front surface, and forming C-electrode ohmic contact thick metal on the back metal of the back electrode;
10) and performing PI etching on the front surface to expose pads of the G-pole ohmic contact thick metal and the A-pole ohmic contact thick metal to prepare the reverse conducting SiC GTO device.
The invention has the beneficial effects that: compared with the prior art, the invention has the following beneficial effects: the RC-GTO device realizes the functions of forward conduction and reverse conduction of the chip, so that on one hand, the area of the chip can be greatly reduced, and on the other hand, a single device structure with two discrete device functions is prepared by utilizing the process flow of one device, thereby effectively controlling the manufacturing cost in the aspects of reducing the area of the chip and reducing the process flow; the back of the RC-GTO device is a planar electrode, so that the obvious defects of large packaging stress and poor device reliability caused by the fact that a P + injection layer formed by conventional deep groove etching and an N + substrate are located on planes with different heights are avoided; packaging processes such as chip bonding and lead wire of the RC-GTO device are reduced, so that compared with a scheme of a discrete device, the reliability of the device is obviously improved due to the fact that the quantity of welding spots is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a reverse conducting SiC GTO semiconductor device provided by an embodiment of the present invention;
FIG. 2 is a graph of reverse conducting SiC GTO forward and reverse voltage-current curves provided by an embodiment of the present invention;
fig. 3 is a chip area when reverse conducting SiC GTO provided in the embodiment of the present invention realizes both forward and reverse conducting currents of 50A;
fig. 4 is a flowchart of a method for preparing a reverse conducting SiC GTO according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, those skilled in the art should be able to devise similar structural modes and embodiments without departing from the spirit of the present invention, and shall fall within the protection scope of the present patent.
In power applications, when using GTO to drive an inductive load, it is necessary to provide a freewheeling path to the inductor, or in other applications, such as pulsed power discharge, the GTO is also required to withstand the reverse current because the discharge current waveform exhibits periodic ringing. The G pole of the ordinary SiC GTO applies trigger current, the C pole applies negative voltage, namely a forward conduction mode, the voltage drop is started to be the built-in potential of the N + substrate/P buffer PN junction, if the G pole trigger current is removed, the C pole applies positive voltage, the N + substrate/Pbuffer PN junction is reversely biased, the reverse conduction process cannot be completed until the PN junction breaks down, and therefore the ordinary SiC GTO does not have the reverse self-follow current capability. Therefore, the invention provides a reverse conducting SiC GTO semiconductor device, which integrates the reverse follow current functions of a GTO device and a Pin diode on the same device, so that the reverse conducting SiC GTO has the functions of forward conduction and reverse follow current simultaneously, thereby effectively reducing the manufacturing cost, avoiding the defects of low switching speed and poor system reliability when two discrete devices are used in parallel, and simultaneously avoiding the disadvantages of large system volume, low power density and high packaging cost caused by modular packaging. For a specific analysis, see the examples below.
Fig. 1 shows a schematic diagram of a structure of a 15kV voltage class reverse conducting SiC GTO semiconductor device provided by an embodiment of the present invention. The structure of the reverse conducting SiC GTO device provided by the invention comprises:
an anode metal electrode 31 (marked as "A" in the figure), a cathode metal electrode 32 (marked as "C" in the figure) and a gate metal electrode 33 (marked as "G" in the figure) are arranged from top to bottom, and a first doping type P + anode 101 layer, second doping type N base layer 201-1, 201-2, 201-3 and first doping type P drift layer 102 are sequentially arranged from top to bottom, wherein the thickness of the first doping type P drift layer in the vertical direction is 120 mu m, and the doping concentration is 2e14 cm-3A first doping type P buffer layer 103, a second doping type N + injection layer 202, a first doping type P + injection layer 104;
the first doping type P + anode 101 layers are arranged on the upper surface of the second doping type N base region layer 201-1 at equal intervals;
the second doping type N base region layers 201-1, 201-2 and 201-3 are the same layer, and the material parameters, such as thickness and doping concentration, are the same;
because the N base region layer material of the RC-GTO device is used as a shared material layer of gate ohmic contact of a GTO part and cathode ohmic contact of a Pin part, in order to ensure reliable triggering of GTO, GTO triggering current injected by G is prevented from flowing out from the N base region through a diode cathode, namely, waste of forward triggering current is prevented, and in order to avoid adverse effects of diode part current on GTO in a reverse conduction process, preferably, the left side and the right side of the N base region 202 are electrically isolated from the N base region layers 201-1 and 201-3 through etching deep grooves;
the grid metal electrodes 33 are arranged between the P + anodes 101 at equal intervals, and the left, right and upper parts of the grid metal electrodes are electrically isolated from the P + anode 101 layer and the anode metal electrodes 31 through the filling of the dielectric layer 41-2;
the anode metal electrode 31 is led out by the P + anode 101 layer and the N base region 201-3 layer together, and has the functions of serving as an anode of a GTO in a forward conduction mode and serving as a cathode of a Pin diode in a reverse follow current mode;
the anode metal electrode 31 is electrically isolated from the N base region layers 201-1 and 201-2 through the dielectric layer 41-1;
the second doping type N + injection layer 202 and the first doping type P + injection layer 104 are both connected with the lower surface of the P buffer layer 103;
wherein the N + injection layer 202 and the P + injection layer 104 are connected to each other in the horizontal direction;
compared with silicon (Si) materials, silicon carbide (SiC) can provide 3.3 times of thermal conductivity, 2.5 times of saturated electron mobility and 10 times of breakdown electric field intensity, so that the voltage endurance capacity, the working frequency and the current density of the SiC device are greatly improved. Therefore, preferably, the reverse conducting semiconductor device structure is a silicon carbide reverse conducting GTO.
Compared with a P-type substrate used for manufacturing an N-type SiC GTO device, the SiC material is easier to obtain a high-quality and low-defect N-type epitaxial substrate, so that the first doping type is preferably P-type, and the second doping type is preferably N-type, namely, the device is silicon carbide P-type reverse-conducting GTO.
In order to eliminate the snapback effect in forward conduction to the maximum extent, the transverse conduction path of holes in the P buffer layer needs to be prolonged, and meanwhile, in order to accurately control the proportion of the GTO and PiN diodes in the reverse conducting device, the forward and reverse trade-off performance of the reverse conducting SiC GTO device is improved, and the forward and reverse conduction currents are matched with each other, so that preferably, the region boundary of the N + injection layer 202 in the vertical direction is aligned with the N base region 201-3;
since the back process is to form the cathode metal electrode 32 on both the N + and P + doped layers through the same process step, in order to avoid the defects of large stress of the electrode metal film layer, poor package reliability and short device lifetime caused by the uneven height of the two layers, it is preferable that the N + injection layer 202 and the P + injection layer 104 have the same height in the vertical direction.
FIG. 2 is a graph showing forward and reverse voltage-current curves of a reverse conducting SiC GTO according to an embodiment of the present invention; the material parameters and the size information of each layer are set as follows: referring to FIG. 1, the concentration of the P +101 layer is 1e19 cm-32 μm thick, 2e17 cm concentration of N base layer (201-1, 201-2 and 201-3)-32.5 μm thick, 2e14 cm concentration of P-102 layer-3120 μm thick, 2e17 cm concentration of P buffer 103 layer-31.3 μm thick, 2e19 cm concentration of N +202 layer-30.7 μm thick, 2e19 cm concentration of P +104 layer-30.7 μm thick; the transverse lengths of the N +202 layer and the N base region 201-3 layer are 130 micrometers, the transverse length of the P +104 layer is 358 micrometers, the length of the N base region 201-1 is 255 micrometers, the transverse length of the N base region 201-2 is 100 micrometers, and the width of the left groove and the width of the right groove of the N base region 201-2 are 1.5 micrometers.
It can be seen that forward voltage-current characteristics of the reverse conducting type SiC GTO provided by the embodiment of the present invention are very close to those of a forward voltage-current characteristic used by a common GTO antiparallel PiN diode, and through careful comparison, forward conduction voltage drop of the reverse conducting type SiC GTO under a current of 50A is very small, less than 1%, and reverse conduction voltage drop is slightly higher than that of a discrete PiN diode, but not higher than 6.2%.
Fig. 3 shows the chip area when the reverse conducting SiC GTO provided by the present invention realizes both the forward and reverse conducting currents of 50A, and it can be seen that, compared with the use of the ordinary GTO antiparallel PiN diode, the reverse conducting GTO can save about 84% of the chip area, thereby effectively controlling the chip manufacturing cost and meeting the requirements of various application occasions of the chip.
The reverse conducting SiC GTO provided by the invention can roughly determine a range by simulating the device characteristics through semiconductor device simulation software, such as parameters of doping concentration, thickness, transverse size and the like of each layer, the optimal parameters generally need to be verified according to voltage, current capacity and working frequency in the practical application of the device, and the verification and selection of actual measurement data are needed.
Referring to FIG. 4, another object of the present invention is to provide a method for fabricating a reverse conducting SiC GTO device
First, selectingThe thickness of the drift layer is 120-250 μm, and the doping concentration is 1e14-1e15cm-3Thinning the substrate by adopting a CMP process;
secondly, etching the front surface of the SiC wafer to form a P + anode mesa and expose the upper surface of the N base region;
thirdly, etching the front side, and forming N base regions 201-1 and 201-3 and an isolation N base region 201-2 by using the N base region obtained by the process in the second step through an etching medium filling groove;
fourthly, ion implantation is carried out on the front surface, an ohmic contact region of the metal electrode 33 is formed on the surface of the N base region layer 201-1, and an ohmic contact region of the metal electrode 31 and a terminal region of the device are formed on the surface of the N base region 201-3;
fifthly, turning the wafer, forming a P + injection layer 104 and an N + injection layer 202 through two times of ion injection, and simultaneously forming an ohmic contact area of the metal electrode 32;
sixthly, respectively sputtering metal layers on the front surface and the back surface, and forming an A pole, a C pole and a G pole with good performances by a stripping process and a rapid thermal annealing process at the same step to form ohmic contacts;
seventhly, forming G-pole ohmic contact thick metal 33 on the front surface, and depositing a passivation layer to form filling of left and right isolation grooves of the isolation N base region 201-2;
eighthly, forming an A-pole ohmic contact thick metal 31 on the front surface, and depositing a passivation layer to form electrical isolation between the metal electrode 31 and the metal electrode 33;
ninth, etching the oxide on the front surface to expose the pad of the G-pole ohmic contact thick metal 33;
tenth, coating a PI polymer on the front surface, and forming a C electrode ohmic contact thick metal 32 on the back metal of the back electrode;
step ten, performing PI etching on the front surface to expose pads of the G pole ohmic contact thick metal 33 and the A pole ohmic contact thick metal 31;
and finally, preparing the reverse conducting SiC GTO device.
Therefore, since the activation temperature of ion implantation annealing in the SiC material is high (>1500 ℃), and the melting point of most metal materials is lower than this value, in order to ensure reliable formation and good performance of the metal electrode, preferably, the back surface ion implantation process precedes the ohmic contact electrode process of the front surface of the device;
because the reverse conducting SiC GTO needs to synchronously form P + and N + ohmic electrode contacts on a P buffer layer on the back of the wafer, and needs to perform high-dose ion implantation after removing redundant semiconductor layers by back substrate thinning, preferably, the back thinning process is prior to the back ion implantation process; in order to avoid excessively increasing the number of process steps and masks required for photolithography, preferably, the ions implanted into the front and back surfaces are activated by a single high temperature annealing process;
because the forming temperature of the P-type ohmic contact of the SiC material is generally higher than that of the N-type ohmic contact, the A pole, the C pole and the G ohmic contact are synchronously formed, so that the process steps are reduced, the manufacturing cost is saved, the performance of the SiC ohmic contact on P-type doping is improved, the parasitic impedance of a device is further reduced, and the overall performance of the device is improved.
In summary, embodiments of the present invention provide a reverse conducting SiC GTO device and a method for manufacturing the same, in which functions of forward conduction of a general GTO and reverse freewheeling of a PiN diode are integrated in a semiconductor device, and compared with parallel connection of two devices, chip area can be greatly saved, parasitic impedance of connection can be reduced, switching speed of the device can be increased, and disadvantages of large module package volume and low power density can be avoided; the preparation method can be completed by adding a small number of steps on the basis of the ordinary GTO process flow.
In the description of the present invention, it should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts of the present invention. The foregoing is only a preferred embodiment of the present invention, and it should be noted that there are objectively infinite specific structures due to the limited character expressions, and it will be apparent to those skilled in the art that a plurality of modifications, decorations or changes may be made without departing from the principle of the present invention, and the technical features described above may be combined in a suitable manner; such modifications, variations, combinations, or adaptations of the invention using its spirit and scope, as defined by the claims, may be directed to other uses and embodiments.
Claims (6)
1. A reverse conducting SiCGTO power semiconductor device is characterized in that: the cathode metal electrode, the first doping type P + injection layer, the second doping type N + injection layer, the first doping type P buffer layer, the first doping type P-drift layer, the second doping type N base region, the second doping type isolation N base region, the first doping type P + anode layer, the first medium passivation layer and the second medium passivation layer are sequentially arranged from bottom to top in a laminated mode.
2. The reverse conducting SiCGTO power semiconductor device according to claim 1, characterized in that the first doping type P + injection layer and the second doping type N + injection layer are highly the same in the vertical direction.
3. The reverse conducting SiCGTO power semiconductor device according to claim 1, wherein the region boundary of the second doping type N + implant layer in the vertical direction is aligned with the second doping type N base region.
4. The reverse conducting SiCGTO power semiconductor device according to claim 3, characterized in that the first doping type P + injection layer and the second doping type N + injection layer are highly the same in the vertical direction.
5. The reverse conducting SiCGTO power semiconductor device as in claim 4, wherein the second doping type isolation N base region is etched with deep trenches on the left and right, electrically isolated from the second doping type N base region, and electrically isolated from the upper metal electrode by a filling dielectric layer.
6. The reverse conducting SiCGTO power semiconductor device according to claim 5, characterized by comprising the following preparation steps:
1) selecting a five-layer wafer with the thickness of 120-250 mu m and the doping concentration of 1e14-1e15cm-3, and thinning the substrate by adopting a CMP (chemical mechanical polishing) process;
2) etching the front surface of the SiC wafer to form a P + anode mesa, and exposing the upper surface of the N base region;
3) etching the front surface, and forming the second doping type N base region and the second doping type isolation N base region by the N base region obtained by the second step of process through etching medium filling grooves;
4) performing ion implantation on the front surface, forming an ohmic contact region of the metal electrode on the surface of the second doping type N base region, and simultaneously forming the ohmic contact region of the metal electrode and a terminal region of a device on the surface of the second doping type N base region;
5) turning over the wafer, and respectively forming the first doping type P + injection layer and the second doping type N + injection layer through two times of ion implantation, and simultaneously forming an ohmic contact region of the metal electrode 32;
6) sputtering metal layers on the front surface and the back surface respectively, and forming ohmic contacts of an A pole, a C pole and a G pole with good performance by adopting a stripping process and a rapid thermal annealing process at the same step;
7) forming G-electrode ohmic contact thick metal on the front surface, and simultaneously depositing a passivation layer to form filling of the left and right isolation grooves of the second doping type isolation N base region;
8) forming A-pole ohmic contact thick metal on the front surface, and simultaneously depositing a passivation layer to form electrical isolation between the first metal electrode 31 and the second metal electrode 33;
9) etching the oxide on the front surface to expose the pad of the G-pole ohmic contact thick metal;
tenth, coating a PI polymer on the front surface, and forming C-electrode ohmic contact thick metal on the back metal of the back electrode;
10) and PI etching on the front surface to expose pads of the G-pole ohmic contact thick metal and the A-pole ohmic contact thick metal, thus preparing the reverse conducting SiCGTO device.
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| CN112993063A (en) * | 2021-01-28 | 2021-06-18 | 湖北光安伦芯片有限公司 | Method for manufacturing ohmic contact electrode of optical communication chip |
| CN113270493A (en) * | 2021-05-17 | 2021-08-17 | 湖南大学 | Reverse conducting silicon carbide n-GTO thyristor and preparation method thereof |
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