CN111968945A - Manufacturing method and structure of BCE structure TFT - Google Patents

Manufacturing method and structure of BCE structure TFT Download PDF

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Publication number
CN111968945A
CN111968945A CN202010755484.6A CN202010755484A CN111968945A CN 111968945 A CN111968945 A CN 111968945A CN 202010755484 A CN202010755484 A CN 202010755484A CN 111968945 A CN111968945 A CN 111968945A
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layer
photoresist layer
active layer
negative photoresist
positive photoresist
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CN202010755484.6A
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Chinese (zh)
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阮桑桑
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Fujian Huajiacai Co Ltd
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Fujian Huajiacai Co Ltd
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Priority to CN202010755484.6A priority Critical patent/CN111968945A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention discloses a manufacturing method and a structure of a BCE structure TFT, wherein a negative photoresist layer is coated on an active layer, the negative photoresist layer is exposed and developed, the negative photoresist layer on the active layer is reserved, the middle of a photomask is provided with a transparent area corresponding to the upper position of the middle of the active layer, and the two sides of the photomask are provided with light shading areas corresponding to the positions of a source drain electrode; depositing a source drain metal layer; coating a positive photoresist layer, exposing and developing the positive photoresist layer, and removing part of the positive photoresist layer; etching the source and drain metal film by using the positive photoresist layer as a mask; removing the positive photoresist layer. According to the method, through 2 times of exposure and development, a negative photoresist is adopted to leave a photoresist in a channel region above an active layer, the active layer is protected from being damaged by acid liquor or plasma in the process of etching a source drain electrode metal layer, an SD metal layer is deposited firstly, then a positive photoresist is used, and an SD is formed. The active layer can be protected from being influenced by SD etching at the channel without increasing the compatibility of a photomask with the existing process flow, so that the electrical uniformity and the stability of the TFT are improved.

Description

Manufacturing method and structure of BCE structure TFT
Technical Field
The invention relates to the field of oxide semiconductor display, in particular to a manufacturing method and a structure of a BCE structure TFT.
Background
The IGZO active layer is an amorphous oxide containing indium, gallium and zinc, the carrier mobility is 20-30 times of that of amorphous silicon, the charge-discharge rate of a TFT to a pixel electrode can be greatly improved, the response speed of a pixel is improved, the panel refreshing frequency is higher, and the ultrahigh-resolution TFT-LCD can be realized. The IGZO active layer TFT with the BCE structure has higher electron mobility than ESL, reduces the manufacturing process of ESL layers and has lower manufacturing cost.
Referring to fig. 1 to 2, a Back Channel Etching (BCE) amorphous indium gallium zinc oxide thin film transistor (a-IGZO active layer TFT) has the advantages of simple process, small parasitic capacitance, high aperture ratio, and the like, but the back channel of the IGZO active layer device in the BCE is easily damaged by acid liquid and plasma, thereby causing problems in the uniformity and stability of the TFT.
Disclosure of Invention
Therefore, it is desirable to provide a method and a structure for manufacturing a BCE TFT, which can protect an IGZO active layer at a channel from being damaged by acid solution and plasma in a subsequent process, and improve electrical uniformity and stability of the TFT.
In order to achieve the above object, the inventors provide a method for fabricating a TFT having a BCE structure, comprising the steps of:
coating a negative photoresist layer on the active layer, exposing and developing the negative photoresist layer by adopting a photomask, and reserving the negative photoresist layer on the active layer, wherein the position of the middle upper part of the active layer corresponding to the middle of the photomask is a transparent area, and the positions of the two sides of the photomask corresponding to the source and the drain are light-shielding areas;
depositing a source drain metal layer;
coating a positive photoresist layer, exposing and developing the positive photoresist layer by using the photomask, and removing the positive photoresist layer at the upper position in the middle of the active layer;
etching the source/drain metal film at the upper part of the middle of the active layer by using the positive photoresist layer as a mask;
removing the positive photoresist layer.
Further, before the step of coating the negative photoresist layer on the active layer, exposing and developing the negative photoresist layer by using the photomask and retaining the negative photoresist layer on the active layer, the method further comprises the following steps:
forming a grid metal layer on the substrate by exposure and development and etching;
depositing a gate insulating layer;
an active layer is formed on the gate insulating layer.
Further, the active layer is an IGZO active layer.
The inventors also provide a TFT structure made by the method of any of the above embodiments.
Different from the prior art, the method for manufacturing the BCE structure TFT in the technical scheme comprises the following steps: coating a negative photoresist layer on the active layer, exposing and developing the negative photoresist layer above the active layer, and reserving the negative photoresist layer on the active layer; depositing a source drain metal film; coating a positive photoresist layer, exposing and developing the positive photoresist layer above the negative photoresist layer, and removing the positive photoresist layer above the negative photoresist layer; etching the source and drain metal film by using the positive photoresist layer as a mask; removing the positive photoresist layer. According to the technical proposal, through 2 times of exposure and development processes, a negative photoresist is firstly adopted to leave a photoresist on an upper channel region, so as to protect a source drain metal layer (SD) from being damaged by acid liquor or plasma in the etching process, an SD metal film is firstly deposited, and then a positive photoresist is used for photoetching the source drain metal layer to form the SD. Under the condition of not additionally increasing a photomask and being compatible with the prior process flow, the process of exposure and development is added once, so that the channel can be protected from being influenced by SD etching, and the electrical uniformity and the stability of the TFT are improved.
Drawings
FIG. 1 is a flow chart of a manufacturing process of a BCE structure TFT in the background art;
FIG. 2 is a flow chart of a process for fabricating a source-drain metal layer in the prior art;
FIG. 3 is a diagram of a gate metal layer structure according to an embodiment;
FIG. 4 is a diagram of a gate insulation layer structure according to the embodiment;
FIG. 5 is a schematic diagram of an IGZO active layer structure according to an embodiment;
FIG. 6 is a diagram of a mask and negative photoresist layer structure according to an embodiment;
FIG. 7 is a schematic diagram of the negative photoresist layer after exposure and development in accordance with the embodiment;
FIG. 8 is a diagram of a source/drain metal layer structure according to the embodiment;
FIG. 9 is a diagram of a mask and a positive photoresist layer structure according to the embodiment;
FIG. 10 is a schematic diagram of the positive photoresist layer after exposure and development according to the embodiment;
fig. 11 shows the structure of the negative photoresist layer after etching the source/drain metal layer.
Description of reference numerals:
1. a negative photoresist layer; 2. a positive photoresist layer; 3. an active layer; 4. a source drain metal layer; 5. a gate metal layer; 6. a gate insulating layer; 7. a substrate; 8. a mask is provided.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1 to 11, the present embodiment provides a method for manufacturing a TFT with a BCE structure, including the steps of: coating a negative photoresist layer on the active layer, exposing and developing the negative photoresist layer by adopting a photomask, and reserving the negative photoresist layer on the active layer, wherein the position of the middle upper part of the active layer corresponding to the middle of the photomask is a transparent area, and the positions of the two sides of the photomask corresponding to the source and the drain are light-shielding areas; depositing a source drain metal layer; coating a positive photoresist layer, exposing and developing the positive photoresist layer by using the photomask, and removing the positive photoresist layer at the upper position in the middle of the active layer; etching the source/drain metal film at the upper part of the middle of the active layer by using the positive photoresist layer as a mask; removing the positive photoresist layer. The active layer is an IGZO active layer. According to the technical proposal, through 2 times of exposure and development processes, a negative photoresist is firstly adopted to leave a photoresist in a channel region above an active layer 3, the active layer 3 is protected from being damaged by acid liquor or plasma in the etching process of a source drain metal layer 4(SD), the source drain metal layer 4 is firstly deposited, and then the source drain metal layer 4 is formed after photoetching is carried out on the source drain metal layer 4 by using a positive photoresist. Under the condition that the photomask 8 is compatible with the existing process flow without additionally increasing, namely, the same photomask is adopted, and one exposure and development process is added, the active layer 3 at the channel can be protected from being influenced by etching of the source/drain electrode metal layer 4, so that the electrical uniformity and the stability of the TFT are improved.
Referring to fig. 3, 4 and 5, before the step of coating the negative photoresist layer on the active layer, exposing and developing the negative photoresist layer by using the mask and retaining the negative photoresist layer on the active layer, the method further includes the steps of: forming the gate metal layer 5 on the substrate 7 by exposure and development and etching; depositing the gate insulating layer 6; the active layer 3 is fabricated on the gate insulating layer 6.
Referring to fig. 3 to 11, a layer of negative photoresist is coated on the active layer 3, and through an exposure process, a photosensitive portion of the negative photoresist remains and an unexposed portion develops, leaving a layer of negative photoresist as a protective layer in the channel region of the active layer 3. And then depositing the source/drain metal layer 4, coating a positive photoresist, exposing through the same photomask 8, wherein the photosensitive part of the positive photoresist is developed, the non-photosensitive part is remained to form a source/drain pattern, and the patterns of the positive photoresist and the negative photoresist are complementary. The channel region uncovered by the source and drain is protected by the negative photoresist, and the source and drain metal layer 4(SD) can not be damaged by acid liquor and plasma in the etching process. After etching, the unexposed photoresist is removed by using a positive photoresist stripping liquid, and the negative photoresist is reserved in the channel region to protect the back channel from being influenced by the post-processing.
Referring to fig. 6 and 9, in order to further prevent the back channel of the active layer 3 from being damaged by acid solution and plasma, in this embodiment, the through holes of the masks 8 for exposing the positive photoresist layer 2 and the negative photoresist layer 1 have the same size, that is, the masks used for exposing and developing the positive photoresist layer 2 and the negative photoresist layer 1 are the same. The areas of the positive photoresist layer 2 and the negative photoresist layer 1 irradiated by light are the same. However, the position of development differs depending on the type of resist. It should be noted that, in fig. 11, the negative photoresist layer 1 and the source/drain metal layer 4 are complementary to each other, so as to prevent the active layer 3 from being damaged in the subsequent process. Meanwhile, in order to complement the negative photoresist layer 1 and the source/drain metal layer 4, the following process is necessarily involved, referring to fig. 9, after the negative photoresist layer 1 is manufactured, the negative photoresist layer 1 is positioned on the active layer 3; then, manufacturing the source drain metal layer 4, and removing the negative photoresist layer 1 on the source drain metal layer 4; coating the positive photoresist layer 2, and performing exposure and development, wherein when the positive photoresist layer 2 is manufactured, the same photomask 8 as that used for manufacturing the negative photoresist layer 1 is used, so that the size of a light through hole developed in the positive photoresist layer 2 is the same as that of the negative photoresist layer 1, that is, the positive photoresist layer 2 and the negative photoresist layer 1 are exposed and developed by using the same photomask 8 to form two patterns complementary to each other. It should be noted that, in this embodiment, the positive and negative photoresist layers may be applied in an alternative coating sequence, that is, the positive photoresist layer 2 may be applied first, and then the negative photoresist layer 1 may be applied. If the exposed portion of the positive photoresist layer 2 is removable by the developer, the unexposed portion of the negative photoresist layer 1 is removable by the developer. In the embodiment, through secondary exposure and development, a negative photoresist is firstly adopted to leave a photoresist in a channel region above an IGZO to protect the IGZO from being damaged by acid liquor or plasma in the etching process of a source drain metal layer (SD), an SD metal film is firstly deposited, then a positive photoresist is used, and the SD is formed after photoetching of the source drain metal layer. Under the condition of not additionally increasing a photomask and being compatible with the existing process flow, the IGZO can be protected from being influenced by SD etching at the channel by adding one exposure and development process, and the electrical uniformity and the stability of the TFT are improved.
In some embodiments, the TFT structure is made by the method of any one of the above-described methods. Namely, a grid metal layer is arranged on a substrate, the grid insulating layer is arranged on the grid metal layer, an IGZO active layer is arranged in the middle of the grid insulating layer, source and drain metal layers are arranged on two sides of the active layer, and a negative photoresist layer is coated between the source and drain metal layers on the two sides.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.

Claims (4)

1. A manufacturing method of a BCE structure TFT is characterized by comprising the following steps:
coating a negative photoresist layer on the active layer, exposing and developing the negative photoresist layer by adopting a photomask, and reserving the negative photoresist layer on the active layer, wherein the position of the middle upper part of the active layer corresponding to the middle of the photomask is a transparent area, and the positions of the two sides of the photomask corresponding to the source and the drain are light-shielding areas;
depositing a source drain metal layer;
coating a positive photoresist layer, exposing and developing the positive photoresist layer by using the photomask, and removing the positive photoresist layer at the upper position in the middle of the active layer;
etching the source/drain metal film at the upper part of the middle of the active layer by using the positive photoresist layer as a mask;
removing the positive photoresist layer.
2. The method as claimed in claim 1, wherein the step of coating a negative photoresist layer on the active layer, exposing and developing the negative photoresist layer using a mask and retaining the negative photoresist layer on the active layer comprises the steps of:
forming a grid metal layer on the substrate by exposure and development and etching;
depositing a gate insulating layer;
an active layer is formed on the gate insulating layer.
3. The method of claim 1, wherein the active layer is an IGZO active layer.
4. A TFT structure produced by the method of any one of claims 1 to 3.
CN202010755484.6A 2020-07-31 2020-07-31 Manufacturing method and structure of BCE structure TFT Pending CN111968945A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8574821B1 (en) * 2011-12-21 2013-11-05 The United States Of America As Represented By The Secretary Of The Air Force MEMS fabrication process base on SU-8 masking layers
CN110634748A (en) * 2019-09-04 2019-12-31 深圳市华星光电技术有限公司 Preparation method of thin film transistor and thin film transistor
CN111048592A (en) * 2019-11-19 2020-04-21 福建华佳彩有限公司 Thin film field effect transistor structure and manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8574821B1 (en) * 2011-12-21 2013-11-05 The United States Of America As Represented By The Secretary Of The Air Force MEMS fabrication process base on SU-8 masking layers
CN110634748A (en) * 2019-09-04 2019-12-31 深圳市华星光电技术有限公司 Preparation method of thin film transistor and thin film transistor
CN111048592A (en) * 2019-11-19 2020-04-21 福建华佳彩有限公司 Thin film field effect transistor structure and manufacturing method

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